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CHAPTER 10 SERIAL INTERFACE FUNCTION
(3) Asynchronous serial interface status registers 1, 2 (ASIS1, ASIS2)
The ASISn register is a register that is configured of a UARTn transmission status flag (SOTn), reception
status flag (SIRn), a bit (RB8) indicating the 9th bit when extension bit addition is enabled, and 3-bit error
flags (PEn, FEn, OVEn) that indicate the error status at reception end (n = 1, 2).
The status flag that indicates reception errors always indicates the most recent error status. In other words, if
the same error occurs several times before receive data is read, this flag holds only the status of the error
that occurred last.
Each time the ASISn register is read after a receive completion interrupt (INTSRn), read the receive buffer
(RXBn or RXBLn). The error flag is cleared when the receive buffer (RXBn or RXBLn) is read.
Also, clear the error flag by reading the receive buffer (RXBn or RXBLn) when a reception error occurs.
This register is read-only, in 8-bit or 1-bit units.
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User's Manual U14492EJ5V0UD
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