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CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION
Remarks 1. Default priority:
Restored PC:
nextPC:
2. The execution address of the illegal instruction when an illegal opcode exception occurs is
calculated by (Restored PC – 4).
The priority order when two or more maskable interrupt requests are generated at
the same time. The highest priority is 0.
The value of the program counter (PC) saved to EIPC, FEPC, or DBPC of CPU
when interrupt servicing is started. Note, however, that the restored PC when a
non-maskable or maskable interrupt is acknowledged while one of the following
instructions is being executed does not become the nextPC. (If an interrupt is
acknowledged during instruction execution, execution stops, and then resumes
after the interrupt servicing has finished. In this case, the address of the aborted
instruction is the restore PC.)
• Load instructions (SLD.B, SLD.BU, SLD.H, SLD.HU, SLD.W)
• Division instructions (DIV, DIVH, DIVU, DIVHU)
• PREPARE, DISPOSE instructions (only if an interrupt is generated before the
stack pointer is updated)
The PC value that starts the processing following interrupt/exception processing.
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