Page 1 User’s Manual V850E/IA2 32-Bit Single-Chip Microcontrollers Hardware µ PD703114 µ PD703114(A) µ PD70F3114 µ PD70F3114(A) Document No. U15195EJ5V0UD00 (5th edition) Date Published August 2005 N CP(K) 2001 Printed in Japan...
Page 2 [MEMO] User’s Manual U15195EJ5V0UD...
Page 3 NOTES FOR CMOS DEVICES VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between V (MAX) and V (MIN) due to noise, etc., the device may malfunction.
Page 4 NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Page 5 Regional Information Some information contained in this document may vary from country to country. Before using any NEC Electronics product in your application, pIease contact the NEC Electronics office in your country to obtain a list of authorized representatives and distributors. They will verify: •...
Page 6 2. When using this manual as a manual for a special grade product, read the part numbers as follows. µ PD703114 → 703114(A) µ PD70F3114 → 70F3114(A) • To find the details of a register where the name is known →...
Page 7 • To understand the overall functions of the V850E/IA2 → Read this manual according to the CONTENTS. • How to read register formats → The name of a bit whose number is in angle brackets (<>) is defined as a reserved word in the device file.
Page 8 Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents related to V850E/IA2 Document Name Document No. V850E1 Architecture User’s Manual U14559E V850E/IA2 Hardware User’s Manual This manual V850E/IA1, V850E/IA2 AC Motor Inverter Control Using Vector U14868E Operation Application Note...
Page 9: Table Of Contents
CONTENTS CHAPTER 1 INTRODUCTION .........................17 Outline............................17 Features ............................. 19 Applications..........................21 Ordering Information ........................ 21 Pin Configuration (Top View)....................22 Configuration of Function Block..................... 25 1.6.1 Internal block diagram ........................25 1.6.2 Internal units..........................26 CHAPTER 2 PIN FUNCTIONS ........................28 List of Pin Functions ........................ 28 Pin Status...........................
Page 10 4.3.1 Chip select control function......................82 Bus Cycle Type Control Function ................... 85 Bus Access ..........................86 4.5.1 Number of access clocks......................86 4.5.2 Bus sizing function........................87 4.5.3 Bus width ............................. 88 Wait Function..........................94 4.6.1 Programmable wait function ......................94 4.6.2 External wait function ........................
Page 11 6.12 Forcible Termination ......................129 6.12.1 Restrictions on forcible termination of DMA transfer ..............130 6.13 Time Required for DMA Transfer ..................131 6.14 Cautions........................... 132 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION..........134 Features ........................... 134 Non-Maskable Interrupt......................138 7.2.1 Operation ...........................139 7.2.2 Restore............................141 7.2.3 Non-maskable interrupt status flag (NP) ..................142...
Page 12 8.5.5 Software STOP mode........................ 191 Securing Oscillation Stabilization Time................193 8.6.1 Oscillation stabilization time security specification..............193 8.6.2 Time base counter (TBC) ......................194 CHAPTER 9 TIMER/COUNTER FUNCTION ..................195 Timer 0............................195 9.1.1 Features (timer 0) ........................195 9.1.2 Function overview (timer 0) .......................
Page 13 CHAPTER 10 SERIAL INTERFACE FUNCTION ................406 10.1 Features ........................... 406 10.1.1 Selecting UART1 or CSI1 mode....................407 10.2 Asynchronous Serial Interface 0 (UART0) ................408 10.2.1 Features .............................408 10.2.2 Configuration ..........................409 10.2.3 Control registers .........................411 10.2.4 Interrupt requests ........................418 10.2.5 Operation ...........................419 10.2.6 Dedicated baud rate generator 0 (BRG0)...................431 10.2.7...
Page 14 11.10.2 Operation in scan mode ......................540 11.11 Operation Cautions ......................... 541 11.11.1 Stopping A/D conversion operation ................... 541 11.11.2 Trigger input during A/D conversion operation ................541 11.11.3 External or timer trigger interval....................541 11.11.4 Operation in standby modes...................... 541 11.11.5 Compare match interrupt in timer trigger mode .................
Page 15 µ CHAPTER 15 FLASH MEMORY ( PD70F3114).................603 15.1 Features ........................... 603 15.2 Writing Using Flash Programmer..................603 15.3 Programming Environment....................606 15.4 Communication Mode ......................606 15.5 Pin Connection........................608 15.5.1 MODE1/V pin ..........................608 15.5.2 Serial interface pin........................608 15.5.3 RESET pin ..........................610 15.5.4 NMI pin............................610 15.5.5...
Page 16 CHAPTER 18 RECOMMENDED SOLDERING CONDITIONS............662 APPENDIX A NOTES ON TARGET SYSTEM DESIGN ..............664 APPENDIX B REGISTER INDEX ......................666 APPENDIX C INSTRUCTION SET LIST ..................... 675 Conventions..........................675 Instruction Set (Alphabetical Order) ..................678 APPENDIX D REVISION HISTORY ..................... 684 Major Revisions in This Edition.....................
Page 17: Chapter 1 Introduction
CHAPTER 1 INTRODUCTION The V850E/IA2 is a product in NEC Electronics’ V850 Series of single-chip microcontrollers. This chapter provides an overview of the V850E/IA2. 1.1 Outline The V850E/IA2 is a 32-bit single-chip microcontroller that uses high-speed operations to realize high-precision inverter control of motors.
Page 18 100-pin plastic LQFP 100-pin plastic QFP Note The maximum operating frequency of the in-circuit emulator is 40 MHz. A frequency of 50 MHz can be supported by upgrading the in-circuit emulator, so contact an NEC Electronics sales representative or distributor. Remark For details, refer to the user’s manual of each product.
Page 19: Features
16-bit data bus (address/data multiplexed) 16-/8-bit bus sizing function External wait function Internal memory Part Number Internal ROM Internal RAM µ PD703114 128 KB (mask ROM) 6 KB µ PD70F3114 128 KB (flash memory) 6 KB Interrupts/exceptions External interrupts: 16 (including NMI)
Page 20 CHAPTER 1 INTRODUCTION DMA controller 4-channel configuration Transfer unit: 8 bits/16 bits Maximum transfer count: 65,536 (2 Transfer type: 2-cycle transfer Transfer modes: Single transfer, single-step transfer, block transfer Memory ↔ Memory, Memory ↔ I/O, I/O ↔ I/O Transfer subjects: Transfer requests: On-chip peripheral I/O, software Next address setting function...
Page 21: Applications
• PD703114, 70F3114: Consumer equipment (inverter air conditioners) Industrial equipment (motor control, general-purpose inverters) • µ PD703114(A), 70F3114(A): Automobile applications (electrical power steering) 1.4 Ordering Information Part Number Package Quality Grade µ 100-pin plastic LQFP (fine pitch) (14 × 14) PD703114GC-×××-8EU...
Page 22: Pin Configuration (Top View)
CHAPTER 1 INTRODUCTION 1.5 Pin Configuration (Top View) • 100-pin plastic LQFP (fine pitch) (14 × 14) µ µ PD703114GC-×××-8EU PD70F3114GC-8EU µ µ PD703114GC-×××-8EU-A PD70F3114GC-8EU-A µ µ PD703114GC(A)-×××-8EU PD70F3114GC(A)-8EU µ µ PD703114GC(A)-×××-8EU-A PD70F3114GC(A)-8EU-A ANI05 ESO0/INTP0/P01 Note 2 NMI/P00 TCLR10/INTP101/P12 ANI10 TCUD10/INTP100/P11 ANI11 TIUD10/TO10/P10...
Page 23 CHAPTER 1 INTRODUCTION • 100-pin plastic QFP (14 × 20) µ µ PD703114GF-×××-3BA PD70F3114GF-3BA µ µ PD703114GF-×××-3BA-A PD70F3114GF-3BA-A ANI03 ADTRG1/INTP3/P04 ANI04 ADTRG0/INTP2/P03 ANI05 ESO1/INTP1/P02 ESO0/INTP0/P01 Note 2 NMI/P00 ANI10 TCLR10/INTP101/P12 ANI11 TCUD10/INTP100/P11 ANI12 TIUD10/TO10/P10 ANI13 PCM1/CLKOUT ANI14 PCM0/WAIT ANI15 PCT6/ASTB ANI16 PCT4/RD ANI17...
Page 24 CHAPTER 1 INTRODUCTION Pin Identification A16 to A21: Address bus PDH0 to PDH5: Port DH AD0 to AD15: Address/data bus PDL0 to PLD15: Port DL ADTRG0, ADTRG1: A/D trigger input Read strobe ANI00 to ANI05, RESET: Reset ANI10 to ANI17: Analog input REGIN: Regulator input...
Page 25: Configuration Of Function Block
ADC1 RXD0 SO1/TXD1 SI1/RXD1 UART1 SCK1/ASCK1 MODE0, MODE1 /V Note 2 CSI1 System RESET controller CSI0 REGIN SCK0 REGOUT Regulator µ Notes 1. PD703114: 128 KB (mask ROM) µ PD70F3114: 128 KB (flash memory) µ PD70F3114 only User’s Manual U15195EJ5V0UD...
Page 26: Internal Units
(5) ROM µ µ PD703114 includes mask ROM (128 KB), and the PD70F3114 includes flash memory (128 KB). On an instruction fetch, the ROM can be accessed by the CPU in one clock. When single-chip mode or flash memory programming mode is set, ROM is mapped starting from address 00000000H.
Page 27 CHAPTER 1 INTRODUCTION (9) Timer/counter function This unit incorporates a 2-channel 16-bit timer (TM0) for 3-phase sine wave PWM inverter control, a 1- channel 16-bit up/down counter (TM1) that can be used for 2-phase encoder input or as a general-purpose timer, a 2-channel 16-bit general-purpose timer unit (TM2), a 1-channel 16-bit timer/event counter (TM3), and a 1-channel 16-bit interval timer (TM4) on-chip, and can measure the pulse interval or frequency and can output a programmable pulse.
Page 28: Chapter 2 Pin Functions
CHAPTER 2 PIN FUNCTIONS The names and functions of the V850E/IA2 pins are shown below. These pins can be divided by function into port pins and non-port pins. 2.1 List of Pin Functions (1) Port pins (1/2) Pin Name Function Alternate Function Input Port 0...
Page 29 CHAPTER 2 PIN FUNCTIONS (2/2) Pin Name Function Alternate Function PCT0 Port CT 4-bit I/O port PCT1 Input or output can be specified in 1-bit units PCT4 PCT6 ASTB PDH0 Port DH 6-bit I/O port PDH1 Input or output can be specified in 1-bit units PDH2 PDH3 PDH4...
Page 30 CHAPTER 2 PIN FUNCTIONS (2) Non-port pins (1/3) Pin Name Function Alternate Function − TO000 Output Timer 00 pulse signal output − TO001 − TO002 − TO003 − TO004 − TO005 − TO010 Output Timer 01 pulse signal output − TO011 −...
Page 31 CHAPTER 2 PIN FUNCTIONS (2/3) Pin Name Function Alternate Function INTP20 Input External maskable interrupt request input and timer 2 external capture P20/TI2 trigger input INTP21 P21/TO21 INTP22 P22/TO22 INTP23 P23/TO23 INTP24 P24/TO24 INTP25 P25/TCLR2 INTP30 Input External maskable interrupt request input and timer 3 external capture P26/TI3/TCLR3 trigger input INTP31...
Page 32 CHAPTER 2 PIN FUNCTIONS (3/3) Pin Name Function Alternate Function CLKOUT Output System clock output PCM1 − CKSEL Input Input specifying clock generator operation mode − − , AV Positive power supply for A/D converter − − , AV Ground potential for A/D converter −...
Page 33: Pin Status
CHAPTER 2 PIN FUNCTIONS 2.2 Pin Status The following table shows the status of each pin after a reset, in power-saving mode (software STOP mode, IDLE, HALT), and during a DMA transfer. Operating Status Reset Reset IDLE Mode/ HALT Mode/ (Single-Chip Mode) (ROMless Mode) Software STOP Mode...
Page 34: Description Of Pin Functions
CHAPTER 2 PIN FUNCTIONS 2.3 Description of Pin Functions (1) P00 to P05 (Port 0) … Input P00 to P05 function as a 6-bit input-only port in which all pins are fixed to input. Besides functioning as an input port, in control mode, P00 to P05 operate as NMI input, timer/counter output stop signal input, external interrupt request input, A/D converter (ADC) external trigger input, and timer 3 output stop signal input.
Page 35 CHAPTER 2 PIN FUNCTIONS (2) P10 to P12 (Port 1) … I/O P10 to P12 function as a 3-bit I/O port in which input or output can be set in 1-bit units. Besides functioning as an I/O port, in control mode, P10 to P12 operate as timer/counter I/O and external interrupt request input.
Page 36 CHAPTER 2 PIN FUNCTIONS (3) P20 to P27 (Port 2) … I/O P20 to P27 function as an 8-bit I/O port in which input or output can be set in 1-bit units. Besides functioning as an I/O port, in control mode, P20 to P27 operate as timer/counter I/O and external interrupt request input.
Page 37 CHAPTER 2 PIN FUNCTIONS (4) P30 to P34 (Port 3) … I/O P30 to P34 function as a 5-bit I/O port in which input or output can be set in 1-bit units. Besides functioning as an I/O port, in control mode, P30 to P34 operate as serial interface (UART0, UART1/CSI1) I/O.
Page 38 CHAPTER 2 PIN FUNCTIONS (5) P40 to P42 (Port 4) … I/O P40 to P42 function as a 3-bit I/O port in which input or output can be set in 1-bit units. Besides functioning as an I/O port, in control mode, P40 to P42 operate as serial interface (CSI0) I/O. Port or control mode can be selected as the operation mode for each bit, specified by the port 4 mode control register (PMC4).
Page 39 CHAPTER 2 PIN FUNCTIONS (7) PCT0, PCT1, PCT4, PCT6 (Port CT) … I/O PCT0, PCT1, PCT4, and PCT6 function as a 4-bit I/O port in which input or output can be set in 1-bit units. Besides functioning as a port, in control mode, these pins operate as control signal output for when memory is expanded externally.
Page 40 CHAPTER 2 PIN FUNCTIONS (8) PDH0 to PDH5 (Port DH) … I/O PDH0 to PDH5 function as a 6-bit I/O port in which input or output can be set in 1-bit units. Besides functioning as a port, in control mode (external expansion mode), these pins operate as the address bus (A16 to A21) for when memory is expanded externally.
Page 41 ROMless mode (see 3.3 Operation Modes for details). The operation mode is determined by sampling the status of each of the MODE0 and MODE1 pins on a reset. Fix these pins so that the input level does not change during operation. µ PD703114 MODE1 MODE0 Operation Mode...
Page 42 CHAPTER 2 PIN FUNCTIONS (20) RV (Regulator power supply) This is the positive power supply pin for the regulator. Supply 5 V system power to this pin. (21) V (Ground) This is the internal 3.3 V system ground pin. (22) REGOUT (Regulator output) … Output This is the regulator output pin.
Page 43: Types Of Pin I/O Circuits And Connection Of Unused Pins
CHAPTER 2 PIN FUNCTIONS 2.4 Types of Pin I/O Circuits and Connection of Unused Pins Connection of a 1 to 10 kΩ resistor is recommended when connecting to V , or CV via a resistor. (1/2) I/O Circuit Type Recommended Connection P00/NMI Connect directly to V P01/ESO0/INTP0...
Page 44 CHAPTER 2 PIN FUNCTIONS (2/2) I/O Circuit Type Recommended Connection − MODE0 Note /MODE1 RESET CKSEL − Leave open. − , AV Connect to V − , AV Connect to V − REGOUT Leave open. µ Note PD70F3114 only User’s Manual U15195EJ5V0UD...
Page 45: Pin I/O Circuits
CHAPTER 2 PIN FUNCTIONS 2.5 Pin I/O Circuits Type 2 Type 5-AC Data P-ch IN/OUT Output N-ch disable Input Schmitt-triggered input with hysteresis characteristics enable Type 4 Type 7 Data P-ch P-ch Comparator Output N-ch N-ch disable (threshold voltage) Push-pull output with possible high-impedance output (P-ch, N-ch both off) Type 5 Data...
Page 46: Chapter 3 Cpu Function
CHAPTER 3 CPU FUNCTION The CPU of the V850E/IA2 is based on RISC architecture and executes almost all instructions in one clock cycle, using 5-stage pipeline control. 3.1 Features • Minimum instruction execution time: 25 ns (@ internal 40 MHz operation) •...
Page 47: Cpu Register Set
CHAPTER 3 CPU FUNCTION 3.2 CPU Register Set The registers of the V850E/IA2 can be classified into two categories: a general-purpose program register set and a dedicated system register set. The width of all the registers is 32 bits. For details, refer to V850E1 Architecture User’s Manual. (1) Program register set (2) System register set (Zero register)
Page 48: Program Register Set
CHAPTER 3 CPU FUNCTION 3.2.1 Program register set The program register set includes general-purpose registers and a program counter. (1) General-purpose registers Thirty-two general-purpose registers, r0 to r31, are available. Any of these registers can be used as a data variable or address variable.
Page 49: System Register Set
CHAPTER 3 CPU FUNCTION 3.2.2 System register set System registers control the status of the CPU and hold interrupt information. To read/write these system registers, specify a system register number indicated below using the system register load/store instruction (LDSR or STSR instruction). Table 3-2.
Page 50 CHAPTER 3 CPU FUNCTION (1) Interrupt status saving registers (EIPC, EIPSW) There are two interrupt status saving registers, EIPC and EIPSW. Upon occurrence of a software exception or a maskable interrupt, the contents of the program counter (PC) are saved to EIPC and the contents of the program status word (PSW) are saved to EIPSW (upon occurrence of a non-maskable interrupt (NMI), the contents are saved to the NMI status saving registers (FEPC, FEPSW)).
Page 51 CHAPTER 3 CPU FUNCTION (2) NMI status saving registers (FEPC, FEPSW) There are two NMI status saving registers, FEPC and FEPSW. Upon occurrence of a non-maskable interrupt (NMI), the contents of the program counter (PC) are saved to FEPC and the contents of the program status word (PSW) are saved to FEPSW. The address of the next instruction following the instruction executed when a non-maskable interrupt occurs is saved to FEPC, except for some instructions.
Page 52 CHAPTER 3 CPU FUNCTION (4) Program status word (PSW) The program status word (PSW) is a collection of flags that indicate the program status (instruction execution result) and the CPU status. When the contents of this register are changed using the LDSR instruction, the new contents become valid immediately following completion of LDSR instruction execution.
Page 53 CHAPTER 3 CPU FUNCTION (2/2) Note During saturated operation, the saturated operation results are determined by the contents of the OV flag and S flag. The SAT flag is set (to 1) only when the OV flag is set (to 1) during saturated operation. Saturated Operation result status Flag status...
Page 54 CHAPTER 3 CPU FUNCTION (6) Exception/debug trap status saving registers (DBPC, DBPSW) There are two exception/debug trap status saving registers, DBPC and DBPSW. Upon occurrence of an exception trap or debug trap, the contents of the program counter (PC) are saved to DBPC, and the program status word (PSW) contents are saved to DBPSW.
Page 55: Operation Modes
CHAPTER 3 CPU FUNCTION 3.3 Operation Modes 3.3.1 Operation modes The V850E/IA2 has the following operation modes. Mode specification is carried out by the MODE0 and MODE1 pins. (1) Normal operation mode (a) Single-chip mode Access to the internal ROM is enabled. In single-chip mode, after the system reset is cleared, each pin related to the bus interface enters the port mode, program execution branches to the reset entry address of the internal ROM, and instruction processing starts.
Page 56: Operation Mode Specification
The operation mode is specified according to the status of the MODE0 and MODE1 pins. In an application system, fix the specification of these pins and do not change them during operation. Operation is not guaranteed if these pins are changed during operation. µ PD703114 MODE1 MODE0 Operation Mode...
Page 57: Address Space
CHAPTER 3 CPU FUNCTION 3.4 Address Space 3.4.1 CPU address space The V850E1 CPU of the V850E/IA2 is of 32-bit architecture and supports up to 4 GB of linear address space (data space) during operand addressing (data access). Also, in instruction address addressing, a maximum of 64 MB of linear address space (program space) is supported.
Page 58: Image
CHAPTER 3 CPU FUNCTION 3.4.2 Image 16 images, each containing a 256 MB physical address space, are seen in the 4 GB CPU address space. In actuality, the same 256 MB physical address space is accessed regardless of the values of bits 31 to 28 of the CPU address.
Page 59: Wrap-Around Of Cpu Address Space
CHAPTER 3 CPU FUNCTION 3.4.3 Wrap-around of CPU address space (1) Program space Of the 32 bits of the PC (program counter), the higher 6 bits are fixed to 0, and only the lower 26 bits are valid. Even if a carry or borrow occurs from bit 25 to 26 as a result of branch address calculation, the higher 6 bits ignore the carry or borrow.
Page 60: Memory Map
CHAPTER 3 CPU FUNCTION 3.4.4 Memory map The V850E/IA2 reserves areas as shown in Figure 3-3. Each mode is specified by the MODE0 and MODE1 pins. Figure 3-3. Memory Map Single-chip mode ROMless mode xFFFFFFFH On-chip peripheral On-chip peripheral 4 KB I/O area I/O area xFFFF000H...
Page 61: Area
CHAPTER 3 CPU FUNCTION 3.4.5 Area (1) Internal ROM/internal flash memory area (a) Memory map 1 MB of internal ROM/internal flash memory area, addresses 00000H to FFFFFH, is reserved. Actually, internal ROM/internal flash memory of 128 KB is mapped to addresses 000000H to 01FFFFH. Addresses 020000H to 0FFFFFH are undefined.
Page 62 CHAPTER 3 CPU FUNCTION (b) Interrupt/exception table The V850E/IA2 increases the interrupt response speed by assigning handler addresses corresponding to interrupts/exceptions. The collection of these handler addresses is called an interrupt/exception table, which is located in the internal ROM area. When an interrupt/exception request is acknowledged, execution jumps to the handler address, and the program written at that memory location is executed.
Page 63 CHAPTER 3 CPU FUNCTION (2) Internal RAM area 12 KB of memory, addresses FFFC000H to FFFEFFFH, are reserved for the internal RAM area. The 12 KB area of 3FFC000H to 3FFEFFFH can be seen as an image of FFFC000H to FFFEFFFH. In the V850E/IA2, 6 KB of memory, addresses FFFC000H to FFFD7FFH, are provided as physical internal RAM.
Page 64 CHAPTER 3 CPU FUNCTION (3) On-chip peripheral I/O area 4 KB of memory, addresses FFFF000H to FFFFFFFH, are provided as an on-chip peripheral I/O area. An image of addresses FFFF000H to FFFFFFFH can be seen in the area between addresses 3FFF000H and Note 3FFFFFFH Note Access to the area of addresses 3FFF000H to 3FFFFFFH is prohibited.
Page 65: External Memory Expansion
CHAPTER 3 CPU FUNCTION 3.4.6 External memory expansion By setting the port n mode control register (PMCn) to control mode, an external device can be connected to the external memory space using each pin of ports DH, DL, CT, and CM. Each register is set by selecting control mode for each pin of these ports using PMCn (n = DH, DL, CT, CM).
Page 66: Recommended Use Of Address Space
CHAPTER 3 CPU FUNCTION 3.4.7 Recommended use of address space The architecture of the V850E/IA2 requires that a register that serves as a pointer be secured for address generation when accessing operand data in the data space. Operand data access from instruction can be directly executed at the address in this pointer register ±32 KB.
Page 67 CHAPTER 3 CPU FUNCTION Figure 3-5. Recommended Memory Map Program space Data space FFFFFFFFH On-chip peripheral I/O FFFFFA78H FFFFFA77H FFFFF000H FFFFEFFFH Internal RAM FFFFD800H FFFFD7FFH xFFFFFFFH On-chip xFFFFA78H peripheral I/O FFFFC000H xFFFFA77H FFFFBFFFH xFFFF000H xFFFEFFFH Internal RAM xFFFD800H xFFFD7FFH xFFFC000H 04000000H xFFFBFFFH 03FFFFFFH...
Page 68: On-Chip Peripheral I/O Registers
CHAPTER 3 CPU FUNCTION 3.4.8 On-chip peripheral I/O registers (1/10) Address Function Register Name Symbol Bit Units for Manipulation After Reset 1 Bit 8 Bits 16 Bits √ FFFFF004H Port DL Undefined √ √ FFFFF004H Port DLL PDLL Undefined √ √...
Page 69 CHAPTER 3 CPU FUNCTION (2/10) Address Function Register Name Symbol Bit Units for Manipulation After Reset 1 Bit 8 Bits 16 Bits √ FFFFF09EH DMA destination address register 3H DDA3H Undefined √ FFFFF0C0H DMA transfer count register 0 DBC0 Undefined √...
Page 70 CHAPTER 3 CPU FUNCTION (3/10) Address Function Register Name Symbol Bit Units for Manipulation After Reset 1 Bit 8 Bits 16 Bits √ √ FFFFF12AH Interrupt control register CC10IC0 √ √ FFFFF12CH Interrupt control register CC10IC1 √ √ FFFFF12EH Interrupt control register CM10IC0 √...
Page 71 CHAPTER 3 CPU FUNCTION (4/10) Address Function Register Name Symbol Bit Units for Manipulation After Reset 1 Bit 8 Bits 16 Bits √ √ FFFFF1FEH Power save control register √ FFFFF200H A/D scan mode register 00 ADSCM00 0000H √ √ FFFFF200H A/D scan mode register 00L ADSCM00L √...
Page 72 CHAPTER 3 CPU FUNCTION (5/10) Address Function Register Name Symbol Bit Units for Manipulation After Reset 1 Bit 8 Bits 16 Bits √ √ FFFFF404H Port 2 Undefined √ √ FFFFF406H Port 3 Undefined √ √ FFFFF408H Port 4 Undefined √...
Page 73 CHAPTER 3 CPU FUNCTION (6/10) Address Function Register Name Symbol Bit Units for Manipulation After Reset 1 Bit 8 Bits 16 Bits √ FFFFF59EH Buffer register CM05 BFCM05 FFFFH √ FFFFF5B0H Dead time timer reload register 1 DTRR1 0FFFH √ FFFFF5B2H Buffer register CM10 BFCM10...
Page 74 CHAPTER 3 CPU FUNCTION (7/10) Address Function Register Name Symbol Bit Units for Manipulation After Reset 1 Bit 8 Bits 16 Bits √ √ FFFFF635H Timer 2 input filter mode register 5 FEM5 √ FFFFF640H Timer 2 clock stop register 0 STOPTE0 0000H √...
Page 75 CHAPTER 3 CPU FUNCTION (8/10) Address Function Register Name Symbol Bit Units for Manipulation After Reset 1 Bit 8 Bits 16 Bits √ FFFFF65EH Timer 2 subchannel 4 main capture/compare CVPE40 0000H register √ FFFFF660H Timer 2 subchannel 0 capture/compare CVSE00 0000H register...
Page 76 √ FFFFF91AH Serial I/O shift register 1 SIO1 0000H √ √ FFFFF91AH Serial I/O shift register L1 SIOL1 µ Note PD703114: µ PD70F3114: 08H or 0CH (For details, refer to 15.7.12 Flash programming mode control register (FLPMC).) User’s Manual U15195EJ5V0UD...
Page 77 CHAPTER 3 CPU FUNCTION (10/10) Address Function Register Name Symbol Bit Units for Manipulation After Reset 1 Bit 8 Bits 16 Bits √ √ FFFFF920H Prescaler mode register 3 PRSM3 √ FFFFF922H Prescaler compare register 3 PRSCM3 √ √ FFFFFA00H Asynchronous serial interface mode register 0 ASIM0 √...
Page 78: Specific Registers
CHAPTER 3 CPU FUNCTION 3.4.9 Specific registers Specific registers are registers that are protected from being written with illegal data due to inadvertent program loop (runaway), etc. The V850E/IA2 has three specific registers, the power save control register (PSC) (refer to 8.5.2 (3) Power save control register (PSC)), clock control register (CKC) (refer to 8.3.4 Clock control register (CKC)), and flash programming mode control register (FLPMC) (refer to 15.7.12 Flash programming mode control register (FLPMC)).
Page 79 CHAPTER 3 CPU FUNCTION (2) Restriction on conflict between sld instruction and interrupt request (a) Description If a conflict occurs between the decode operation of an instruction in <2> immediately before the sld instruction following an instruction in <1> and an interrupt request before the instruction in <1> is complete, the execution result of the instruction in <1>...
Page 80: Chapter 4 Bus Control Function
CHAPTER 4 BUS CONTROL FUNCTION The V850E/IA2 is provided with an external bus interface function by which external I/O and memories, such as ROM and RAM, can be connected. 4.1 Features • 16-bit/8-bit data bus sizing function • Wait function •...
Page 81: Memory Block Function
CHAPTER 4 BUS CONTROL FUNCTION 4.3 Memory Block Function In the V850E/IA1, the 256 MB memory space is divided into memory blocks of 2 MB and 64 MB units. The programmable wait function and bus cycle operation mode can be independently controlled for each block. The area that can be used as program area is the 64 MB space of addresses 0000000H to 3FFFFFFH.
Page 82: Chip Select Control Function
CHAPTER 4 BUS CONTROL FUNCTION 4.3.1 Chip select control function Of the 256 MB memory area, the lower 8 MB (0000000H to 07FFFFFH) and the higher 8 MB (F800000H to FFFFFFFH) can be divided into 2 MB memory blocks by chip area selection control registers 0 and 1 (CSC0, CSC1) to control the chip select signal.
Page 83 CHAPTER 4 BUS CONTROL FUNCTION Address After reset CSC0 CS33 CS32 CS31 CS30 CS23 CS22 CS21 CS20 CS13 CS12 CS11 CS10 CS03 CS02 CS01 CS00 FFFFF060H 2C11H Address After reset CSC1 CS43 CS42 CS41 CS40 CS53 CS52 CS51 CS50 CS63 CS62 CS61 CS60...
Page 84 CHAPTER 4 BUS CONTROL FUNCTION The following diagram shows the CS signal that is enabled for area 0 when the CSC0 register is set to 0703H. When the CSC0 register is set to 0703H, CS0 and CS2 are output to block 0 and block 1, but since CS0 has priority over CS2, CS0 is output if the addresses of block 0 and block 1 are accessed.
Page 85: Bus Cycle Type Control Function
CHAPTER 4 BUS CONTROL FUNCTION 4.4 Bus Cycle Type Control Function In the V850E/IA2, the following external devices can be connected directly to each memory block. • SRAM, external ROM, external I/O Connected external devices are specified by bus cycle type configuration registers 0 and 1 (BCT0 and BCT1). (1) Bus cycle type configuration registers 0, 1 (BCT0, BCT1) These registers can be read/written in 16-bit units.
Page 86: Bus Access
CHAPTER 4 BUS CONTROL FUNCTION 4.5 Bus Access 4.5.1 Number of access clocks The number of basic clocks required to access each resource is shown below. Bus Cycle Status Instruction Fetch Operand Data Access Resource (Bus Width) Note 1 Internal ROM (32 bits) Note 2 Internal RAM (32 bits) −...
Page 87: Bus Sizing Function
CHAPTER 4 BUS CONTROL FUNCTION 4.5.2 Bus sizing function The bus sizing function controls the data bus width for each CS space. The data bus width is specified by using the bus size configuration register (BSC). (1) Bus size configuration register (BSC) This register can be read/written in 16-bit units.
Page 88: Bus Width
CHAPTER 4 BUS CONTROL FUNCTION 4.5.3 Bus width The V850E/IA2 accesses on-chip peripheral I/O and external memory in 8-bit, 16-bit, or 32-bit units. The following shows the operation for each type of access. Access all data in order starting from the lower side. (1) Byte access (8 bits) (a) When the data bus width is 16 bits (little endian) <1>...
Page 89 CHAPTER 4 BUS CONTROL FUNCTION (2) Halfword access (16 bits) (a) When the bus width is 16 bits (little endian) <1> Access to even address (2n) <2> Access to odd address (2n + 1) 1st access 2nd access Address Address Address 2n + 1 2n + 1...
Page 90 CHAPTER 4 BUS CONTROL FUNCTION (3) Word access (32 bits) (a) When the bus width is 16 bits (little endian) (1/2) <1> Access to address 4n 1st access 2nd access Address Address 4n + 1 4n + 3 4n + 2 Word data External Word data...
Page 91 CHAPTER 4 BUS CONTROL FUNCTION (a) When the bus width is 16 bits (little endian) (2/2) <3> Access to address 4n + 2 1st access 2nd access Address Address 4n + 3 4n + 5 4n + 2 4n + 4 Word data External Word data...
Page 92 CHAPTER 4 BUS CONTROL FUNCTION (b) When the data bus width is 8 bits (little endian) (1/2) <1> Access to address 4n 1st access 2nd access 3rd access 4th access Address Address Address Address 4n + 1 4n + 2 4n + 3 Word data External...
Page 93 CHAPTER 4 BUS CONTROL FUNCTION (b) When the data bus width is 8 bits (little endian) (2/2) <3> Access to address 4n + 2 1st access 2nd access 3rd access 4th access Address Address Address Address 4n + 2 4n + 3 4n + 4 4n + 5 Word data...
Page 94: Wait Function
CHAPTER 4 BUS CONTROL FUNCTION 4.6 Wait Function 4.6.1 Programmable wait function (1) Data wait control registers 0, 1 (DWC0, DWC1) To facilitate interfacing with low-speed memory or with I/Os, it is possible to insert up to 7 data wait states in the bus cycle activated for each CS space.
Page 95 CHAPTER 4 BUS CONTROL FUNCTION (2) Address wait control register (AWC) In the V850E/IA2, address setup wait and address hold wait states can be inserted before and after the T1 cycle, respectively. These wait states can be set for each CS space via the AWC register. This register can be read/written in 16-bit units.
Page 96: External Wait Function
CHAPTER 4 BUS CONTROL FUNCTION 4.6.2 External wait function When an extremely slow device, an I/O, or an asynchronous system is connected, an arbitrary number of wait states can be inserted in the bus cycle by the external wait pin (WAIT) for synchronization with the external device. Just as with programmable waits, accessing internal ROM, internal RAM, and on-chip peripheral I/O areas cannot be controlled by external waits.
Page 97: Idle State Insertion Function
CHAPTER 4 BUS CONTROL FUNCTION 4.7 Idle State Insertion Function To facilitate interfacing with low-speed memory devices, a set number of idle states (T1) can be inserted into the bus cycle to be activated after the T3 state to secure the data output float delay time (t ) of the memory when each CS space is read-accessed.
Page 98: Bus Priority Order
CHAPTER 4 BUS CONTROL FUNCTION 4.8 Bus Priority Order There are three external bus cycles: DMA cycle, operand data access, and instruction fetch. In order of priority, DMA cycle is the highest, followed by operand data access and instruction fetch, in that order. An instruction fetch may be inserted between a read access and write access during a read modify write access.
Page 99: Boundary Operation Conditions
CHAPTER 4 BUS CONTROL FUNCTION 4.9 Boundary Operation Conditions 4.9.1 Program space (1) Branching to the on-chip peripheral I/O area or successive fetches from the internal RAM area to the on-chip peripheral I/O area are prohibited. If the above is performed (branching or successive fetch), the data to be fetched is undefined and the operation is not guaranteed.
Page 100: Chapter 5 Memory Access Control Function
CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION 5.1 SRAM, External ROM, External I/O Interface 5.1.1 Features • SRAM is accessed in a minimum of 3 states. • A maximum of 7 programmable data wait states can be inserted according to DWC0 and DWC1 register settings.
Page 101: Sram, External Rom, External I/O Access
CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION 5.1.2 SRAM, external ROM, external I/O access Figure 5-1. SRAM, External ROM, External I/O Access Timing (1/4) (a) When reading (1 wait inserted) CLKOUT (output) Address A16 to A21 (output) AD0 to AD15 (I/O) Address Data ASTB (output)
Page 102 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-1. SRAM, External ROM, External I/O Access Timing (2/4) (b) When reading (0 waits, address setup waits, address hold wait states inserted) TASW TAHW CLKOUT (output) Address A16 to A21 (output) AD0 to AD15 (I/O) Address Data ASTB (output)
Page 103 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-1. SRAM, External ROM, External I/O Access Timing (3/4) (c) When writing (1 wait inserted) CLKOUT (output) Address A16 to A21 (output) Note Address Data AD0 to AD15 (I/O) ASTB (output) RD (output) UWR, LWR (output) WAIT (input) Note AD0 to AD7 output invalid data when odd-numbered address byte data is accessed.
Page 104 CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION Figure 5-1. SRAM, External ROM, External I/O Access Timing (4/4) (d) When writing (0 waits inserted, for 8-bit data bus) CLKOUT (output) Address A16 to A21 (output) Address AD8 to AD15 (I/O) Note Address Data AD0 to AD7 (I/O) ASTB (output)
Page 105: Chapter 6 Dma Functions (Dma Controller)
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) The V850E/IA2 includes a direct memory access (DMA) controller (DMAC) that executes and controls DMA transfer. The DMAC controls data transfer between memory and peripheral I/O, between memories or between peripheral I/Os, based on DMA requests issued by the on-chip peripheral I/O (serial interface, timer/counter, and A/D converter), or software triggers (memory refers to internal RAM or external memory).
Page 106: Configuration
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.2 Configuration On-chip Internal RAM peripheral I/O Internal bus On-chip peripheral I/O bus DMA source address Data Address register (DSAnH/DSAnL) control control DMA destination address register (DDAnH/DDAnL) DMA transfer count Count register (DBCn) control DMA channel control register (DCHCn) DMA addressing control...
Page 107: Control Registers
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.3 Control Registers 6.3.1 DMA source address registers 0 to 3 (DSA0 to DSA3) These registers are used to set the DMA source addresses (28 bits each) for DMA channel n (n = 0 to 3). They are divided into two 16-bit registers, DSAnH and DSAnL.
Page 108 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) (2) DMA source address registers 0L to 3L (DSA0L to DSA3L) These registers can be read/written in 16-bit units. Address After reset DSA0L SA15 SA14 SA13 SA12 SA11 SA10 FFFFF080H Undefined Address After reset DSA1L SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0...
Page 109: Dma Destination Address Registers 0 To 3 (Dda0 To Dda3)
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.3.2 DMA destination address registers 0 to 3 (DDA0 to DDA3) These registers are used to set the DMA destination address (28 bits each) for DMA channel n (n = 0 to 3). They are divided into two 16-bit registers, DDAnH and DDAnL.
Page 110 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) (2) DMA destination address registers 0L to 3L (DDA0L to DDA3L) These registers can be read/written in 16-bit units. Address After reset DDA0L DA15 DA14 DA13 DA12 DA11 DA10 FFFFF084H Undefined Address After reset DDA1L DA15 DA14 DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0...
Page 111: Dma Transfer Count Registers 0 To 3 (Dbc0 To Dbc3)
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.3.3 DMA transfer count registers 0 to 3 (DBC0 to DBC3) These 16-bit registers are used to set the byte transfer counts for DMA channels n (n = 0 to 3). They store the remaining transfer counts during DMA transfer.
Page 112: Dma Addressing Control Registers 0 To 3 (Dadc0 To Dadc3)
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.3.4 DMA addressing control registers 0 to 3 (DADC0 to DADC3) These 16-bit registers are used to control the DMA transfer modes for DMA channel n (n = 0 to 3). These registers cannot be accessed during DMA operation. They can be read/written in 16-bit units.
Page 113 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) (2/2) Bit position Bit name Function 7, 6 SAD1, Sets the count direction of the source address for DMA channel n (n = 0 to 3). SAD0 SAD1 SAD0 Count direction Increment Decrement Fixed Setting prohibited 5, 4 DAD1,...
Page 114: Dma Channel Control Registers 0 To 3 (Dchc0 To Dchc3)
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.3.5 DMA channel control registers 0 to 3 (DCHC0 to DCHC3) These 8-bit registers are used to control the DMA transfer operating mode for DMA channel n (n = 0 to 3). These registers can be read/written in 8-bit or 1-bit units. (However, bit 7 is read only and bits 2 and 1 are write only.
Page 115 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) <7> <3> <2> <1> <0> Address After reset DCHC0 MLE0 INIT0 STG0 FFFFF0E0H <7> <3> <2> <1> <0> Address After reset DCHC1 MLE1 INIT1 STG1 FFFFF0E2H <7> <3> <2> <1> <0> Address After reset DCHC2 MLE2 INIT2...
Page 116: Dma Disable Status Register (Ddis)
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.3.6 DMA disable status register (DDIS) This register holds the contents of the Enn bit of the DCHCn register when DMA is forcibly suspended (during NMI input) (n = 0 to 3). This register is read-only, in 8-bit units. Be sure to set bits 7 to 4 to 0.
Page 117: Dma Trigger Factor Registers 0 To 3 (Dtfr0 To Dtfr3)
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.3.8 DMA trigger factor registers 0 to 3 (DTFR0 to DTFR3) These 8-bit registers are used to control the DMA transfer start trigger via interrupt requests from on-chip peripheral I/O. The interrupt requests set with these registers serve as DMA transfer start factors. These registers can be read/written in 8-bit units.
Page 118 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) (2/3) Bit position Bit name Function 5 to 0 IFCn5 to Sets the interrupt source that serves as the DMA transfer start factor. IFCn0 IFCn5 IFCn4 IFCn3 IFCn2 IFCn1 IFCn0 Interrupt source DMA request from on-chip peripheral I/O disabled INTP0 INTP1...
Page 119 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) (3/3) Bit position Bit name Function 5 to 0 IFCn5 to IFCn0 IFCn5 IFCn4 IFCn3 IFCn2 IFCn1 IFCn0 Interrupt source INTDMA3 INTCSI0 INTCSI1 INTSR0 INTST0 INTSER0 INTSR1 INTST1 INTAD0 INTAD1 INTCM010 INTCM011 INTCM012 INTCM014 INTCM015 Other than above Setting prohibited...
Page 120: Transfer Modes
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.4 Transfer Modes 6.4.1 Single transfer mode In single transfer mode, the DMAC releases the bus at each byte/halfword transfer. If there is a subsequent DMA transfer request, transfer is performed again once. This operation continues until a terminal count occurs. When the DMAC has released the bus, if another higher priority DMA transfer request is issued, the higher priority DMA request always takes precedence.
Page 121 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) Figure 6-3 shows a single transfer mode example in which a lower priority DMA transfer request is generated within one clock after the end of a single transfer. DMA channels 0 and 3 are used for a single transfer. When two DMA transfer request signals are activated at the same time, the two DMA transfers are performed alternately.
Page 122: Single-Step Transfer Mode
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.4.2 Single-step transfer mode In single-step transfer mode, the DMAC releases the bus at each byte/halfword transfer. Once a DMA transfer request signal has been received, transfer continues until a terminal count occurs. When the DMAC has released the bus, if another higher priority DMA transfer request is issued, the higher priority DMA request always takes precedence.
Page 123: Block Transfer Mode
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.4.3 Block transfer mode In the block transfer mode, once transfer starts, the DMAC continues the transfer operation without releasing the bus until a terminal count occurs. No other DMA requests are acknowledged during block transfer. After the block transfer ends and the DMAC releases the bus, another DMA transfer can be acknowledged.
Page 124: Transfer Target
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.6 Transfer Target 6.6.1 Transfer type and transfer target Table 6-1 lists the relationship between the transfer type and transfer target (√: Transfer enabled, ×: Transfer disabled). Table 6-1. Relationship Between Transfer Type and Transfer Target Destination Internal ROM On-Chip...
Page 125: External Bus Cycles During Dma Transfer (Two-Cycle Transfer)
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.6.2 External bus cycles during DMA transfer (two-cycle transfer) The external bus cycles during DMA transfer (two-cycle transfer) are shown below. Table 6-2. External Bus Cycles During DMA Transfer (Two-Cycle Transfer) Transfer Target External Bus Cycle On-chip peripheral I/O, internal RAM None –...
Page 126 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) Figure 6-8 shows the configuration of the buffer register. Figure 6-8. Buffer Register Configuration Data read Address/ Data write Master Slave count register register controller The actual DMA transfer is performed based on the settings of the slave register. The settings incorporated in the master and slave registers differ as follows according to the timing (time) at which the settings were made.
Page 127: Dma Transfer Start Factors
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.9 DMA Transfer Start Factors There are two types of DMA transfer start factors, as shown below. Cautions 1. Do not use both start factors ((1) and (2)) in combination for the same channel (if these two start factors are generated at the same time, only one of them is valid, but the valid start factor cannot be identified).
Page 128: Forcible Suspension
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.10 Forcible Suspension DMA transfer can be forcibly suspended by NMI input during DMA transfer. At such a time, the DMAC resets the Enn bit of the DCHCn register of all channels to 0 and the DMA transfer disabled state is entered.
Page 129: Forcible Termination
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.12 Forcible Termination In addition to the forcible interruption operation by means of NMI input, DMA transfer can be forcibly terminated by the INITn bit of the DCHCn register (n = 0 to 3). An example of forcible termination by the INITn bit of the DCHCn register is illustrated below (n = 0 to 3).
Page 130: Restrictions On Forcible Termination Of Dma Transfer
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.12.1 Restrictions on forcible termination of DMA transfer During the procedure to forcibly terminate DMA transfer using the INITn bit of the DCHCn register, the transfer may not be terminated and suspended instead even if the INITn bit has been set to 1. Consequently, when the DMA transfer of the channel that should have been forcibly terminated is resumed, DMA transfer may end after completion of an unexpected transfer count, generating a DMA transfer end interrupt (INTDMAn) (n = 0 to 3).
Page 131: Time Required For Dma Transfer
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) (2) Repetitively setting the INITn bit of the DCHCn register until the transfer is forcibly terminated successfully The preventive processing steps are shown below. <1> Copy the initial transfer count of the channel to be forcibly terminated to a general-purpose register. <2>...
Page 132: Cautions
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) 6.14 Cautions (1) Memory boundary The transfer operation is not guaranteed if the source or the destination address exceeds the area of DMA targets (external memory, internal RAM, or on-chip peripheral I/O) during DMA transfer. (2) Transfer of misaligned data DMA transfer of 16-bit bus width misaligned data is not supported.
Page 133 CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) (7) Read values of DSAn and DDAn registers If the values of the DSAn and DDAn registers are read during DMA transfer, the values in the middle of being updated may be read (n = 0 to 3). For example, if the DSAnH register and the DSAnL register are read in that order when the value of the DMA transfer source address (DSAn register) is “0000FFFFH”...
Page 134: Chapter 7 Interrupt/Exception Processing Function
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION The V850E/IA2 is provided with an interrupt controller (INTC) that can process a total of 48 interrupt requests. An interrupt is an event that occurs independently of program execution, and an exception is an event whose occurrence is dependent on program execution.
Page 135 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 7-1. Interrupt/Exception Source List (1/2) Type Classification Interrupt/Exception Source Default Exception Handler Restored PC Priority Code Address Name Controlling Generating Source Generating Register Unit − − Reset Interrupt RESET RESET input 0000H 00000000H Undefined −...
Page 136 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 7-1. Interrupt/Exception Source List (2/2) Type Classification Interrupt/Exception Source Default Exception Handler Restored PC Priority Code Address Name Controlling Generating Source Generating Register Unit Maskable Interrupt INTP30/INTCC30 CC3IC0 INTP30 pin/ Pin/TM3 0260H 00000260H nextPC CC30 match Interrupt INTP31/INTCC31 CC3IC1...
Page 137 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Remarks 1. Default priority: The priority order when two or more maskable interrupt requests are generated at the same time. The highest priority is 0. Restored PC: The value of the program counter (PC) saved to EIPC, FEPC, or DBPC of CPU when interrupt servicing is started.
Page 138: Non-Maskable Interrupt
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.2 Non-Maskable Interrupt A non-maskable interrupt request is acknowledged unconditionally, even when interrupts are in the interrupt disabled (DI) status. An NMI is not subject to priority control and takes precedence over all the other interrupts. A non-maskable interrupt request is input from the NMI pin.
Page 139: Operation
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.2.1 Operation If a non-maskable interrupt is generated, the CPU performs the following processing, and transfers control to the handler routine. (1) Saves the restored PC to FEPC. (2) Saves the current PSW to FEPSW. (3) Writes exception code 0010H to the higher halfword (FECC) of ECR.
Page 140 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 7-2. Acknowledging Non-Maskable Interrupt Request (a) If a new NMI request is generated while an NMI service program is being executed Main routine (PSW.NP = 1) NMI request held pending regardless NMI request NMI request of the value of the NP bit of the PSW Pending NMI request processed (b) If a new NMI request is generated twice while an NMI service program is being executed...
Page 141: Restore
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.2.2 Restore Execution is restored from the non-maskable interrupt servicing by the RETI instruction. When the RETI instruction is executed, the CPU performs the following processing, and transfers control to the address of the restored PC. (1) Restores the values of the PC and the PSW from FEPC and FEPSW, respectively, because the EP bit of the PSW is 0 and the NP bit of the PSW is 1.
Page 142: Non-Maskable Interrupt Status Flag (Np)
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.2.3 Non-maskable interrupt status flag (NP) The NP flag is a status flag that indicates that non-maskable interrupt (NMI) servicing is under execution. This flag is set when an NMI interrupt has been acknowledged, and masks all interrupt requests and exceptions to prohibit multiple interrupts from being acknowledged.
Page 143: Maskable Interrupts
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.3 Maskable Interrupts Maskable interrupt requests can be masked by interrupt control registers. The V850E/IA2 has 47 maskable interrupt sources. If two or more maskable interrupt requests are generated at the same time, they are acknowledged according to the default priority.
Page 144 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 7-4. Maskable Interrupt Servicing INT input INTC acknowledged xxIF = 1 xxMK = 0 Is the interrupt mask released? Priority higher than that of interrupt currently being serviced? Priority higher than that of other interrupt request? Highest default priority of interrupt requests...
Page 145: Restore
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.3.2 Restore Recovery from maskable interrupt servicing is carried out by the RETI instruction. When the RETI instruction is executed, the CPU performs the following steps, and transfers control to the address of the restored PC. (1) Restores the values of the PC and the PSW from EIPC and EIPSW because the EP bit of the PSW is 0 and the NP bit of the PSW is 0.
Page 146: Priorities Of Maskable Interrupts
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.3.3 Priorities of maskable interrupts The V850E/IA2 provides multiple interrupt servicing in which an interrupt is acknowledged while another interrupt is being serviced. Multiple interrupts can be controlled by priority levels. There are two types of priority level control: control based on the default priority levels, and control based on the programmable priority levels that are specified by the interrupt priority level specification bit (xxPRn) of the interrupt control register (xxICn).
Page 147 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 7-6. Example of Servicing in Which Another Interrupt Request Is Issued While an Interrupt Is Being Serviced (1/2) Main routine Servicing of a Servicing of b Interrupt Interrupt request a request b Interrupt request b is acknowledged because the (level 3) (level 2) priority of b is higher than that of a and interrupts are...
Page 148 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 7-6. Example of Servicing in Which Another Interrupt Request Is Issued While an Interrupt Is Being Serviced (2/2) Main routine Servicing of i Servicing of k Interrupt request j Interrupt request i (level 3) (level 2) Interrupt request j is held pending because its Interrupt request k...
Page 149 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 7-7. Example of Servicing Interrupt Requests Generated Simultaneously Main routine Interrupt request a (level 2) Interrupt request b (level 1) Interrupt request b and c are Servicing of interrupt request b NMI request Interrupt request c (level 1) acknowledged first according to their priorities.
Page 150: Interrupt Control Register (Xxicn)
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.3.4 Interrupt control register (xxICn) An interrupt control register is assigned to each interrupt request (maskable interrupt) and sets the control conditions for each maskable interrupt request. This register can be read/written in 8-bit or 1-bit units. Caution Read the xxIFn bit of the xxICn register in the interrupt disabled (DI) state.
Page 151 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 7-2. Addresses and Bits of Interrupt Control Registers (1/2) Address Register <7> <6> <2> <1> <0> FFFFF110H P0IC0 P0IF0 P0MK0 P0PR02 P0PR01 P0PR00 FFFFF112H P0IC1 P0IF1 P0MK1 P0PR12 P0PR11 P0PR10 FFFFF114H P0IC2 P0IF2 P0MK2 P0PR22 P0PR21 P0PR20...
Page 152 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 7-2. Addresses and Bits of Interrupt Control Registers (2/2) Address Register <7> <6> <2> <1> <0> FFFFF150H CM4IC0 CM4IF0 CM4MK0 CM4PR02 CM4PR01 CM4PR00 FFFFF152H DMAIC0 DMAIF0 DMAMK0 DMAPR02 DMAPR01 DMAPR00 FFFFF154H DMAIC1 DMAIF1 DMAMK1 DMAPR12 DMAPR11 DMAPR10...
Page 153: Interrupt Mask Registers 0 To 3 (Imr0 To Imr3)
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.3.5 Interrupt mask registers 0 to 3 (IMR0 to IMR3) These registers set the interrupt mask state for the maskable interrupts. The xxMKn bit of the IMR0 to IMR3 registers is equivalent to the xxMKn bit of the xxICn register. IMRm can be read/written in 16-bit units (m = 0 to 3).
Page 154: In-Service Priority Register (Ispr)
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.3.6 In-service priority register (ISPR) This register holds the priority level of the maskable interrupt currently acknowledged. When an interrupt request is acknowledged, the bit of this register corresponding to the priority level of that interrupt request is set to 1 and remains set while the interrupt is serviced.
Page 155: Maskable Interrupt Status Flag (Id)
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.3.7 Maskable interrupt status flag (ID) The ID flag is bit 5 of the PSW and this controls the maskable interrupt’s operating state, and stores control information regarding enabling or disabling of interrupt requests. After reset 00000020H Bit position Bit name...
Page 156 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION (1) External interrupt mode registers 1, 2 (INTM1, INTM2) These registers specify the valid edge for external interrupt requests (INTP0 to INTP4), input via external pins. The correspondence between each register and the external interrupt requests that register controls is shown below.
Page 157 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION (2) Signal edge selection register 10 (SESA10) These registers specify the valid edge of external interrupt requests (INTP100, INTP101, TIUD10, TCUD10, and TCLR10), input via external pins. The valid edge can be specified independently for each pin (rising edge, falling edge, or both rising and falling edges).
Page 158 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION (2/2) Bit position Bit name Function 5, 4 CESUD01, Specifies the valid edge of the TLCR10 pin CESUD00 CESUD01 CESUD00 Valid edge Falling edge Rising edge Low level High level The setting values of the CESUD01 and CESUD00 bits and the operation of TM10 are as follows.
Page 159 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION (3) Valid edge selection register (SESC) This register specifies the valid edge for external interrupt requests (INTP30, INTP31, TCLR3, TI3), input via external pins. The valid edge can be specified independently for each pin (rising edge, falling edge, or both rising and falling edges).
Page 160 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION (4) Timer 2 input filter mode registers 0 to 5 (FEM0 to FEM5) These registers specify the valid edge for external interrupts input to timer 2 (INTP20 to INTP25). correspondence between each register and the external interrupt request that register controls is shown below.
Page 161 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION (1/2) Address After reset FEM0 DFEN00 EDGE010 EDGE000 TMS010 TMS000 FFFFF630H INTP20 Address After reset FEM1 DFEN01 EDGE011 EDGE001 TMS011 TMS001 FFFFF631H INTP21 Address After reset FEM2 DFEN02 EDGE012 EDGE002 TMS012 TMS002 FFFFF632H INTP22 Address After reset FEM3 DFEN03...
Page 162 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION (2/2) Bit position Bit name Function Note 1, 0 TMS01n, Selects the capture input TMS00n TMS01n TMS00n Operation Used as a pin Digital filter (noise eliminator specification) Timer-based capture to subchannel 1 Timer-based capture to subchannel 2 Note Selection of capture input based on INTCM100 and INTCM101 is valid only for the FEM1 and FEM2 registers.
Page 163: Software Exception
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.4 Software Exception A software exception is generated when the CPU executes the TRAP instruction, and can be always acknowledged. 7.4.1 Operation If a software exception occurs, the CPU performs the following processing, and transfers control to the handler routine: (1) Saves the restored PC to EIPC.
Page 164: Restore
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.4.2 Restore Returning from software exception processing is carried out by the RETI instruction. By executing the RETI instruction, the CPU carries out the following processing and shifts control to the restored PC’s address. (1) Loads the restored PC and PSW from EIPC and EIPSW because the EP bit of the PSW is 1. (2) Transfers control to the address of the restored PC and PSW.
Page 165: Exception Status Flag (Ep)
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.4.3 Exception status flag (EP) The EP flag is bit 6 of PSW, and is a status flag used to indicate that exception processing is in progress. It is set when an exception occurs. After reset 00000020H Bit position Bit name...
Page 166: Exception Trap
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.5 Exception Trap An exception trap is an interrupt that is requested when an illegal execution of an instruction takes place. In the V850E/IA2, an illegal opcode exception (ILGOP: Illegal Opcode Trap) is considered as an exception trap. 7.5.1 Illegal opcode definition The illegal instruction has an opcode (bits 10 to 5) of 111111B, sub-opcodes of 0111B to 1111B (bits 26 to 23), and 0B (bit 16).
Page 167 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 7-10. Exception Trap Processing Exception trap (ILGOP) occurs DBPC Restored PC DBPSW PSW.NP PSW.EP CPU processing PSW.ID 00000060H Exception processing (2) Restore Returning from exception trap processing is carried out by the DBRET instruction. By executing the DBRET instruction, the CPU carries out the following processing and controls the address of the restored PC.
Page 168: Debug Trap
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.5.2 Debug trap The debug trap is an exception that can be acknowledged every time and is generated by execution of the DBTRAP instruction. When the debug trap is generated, the CPU performs the following processing. (1) Operation When the debug trap is generated, the CPU performs the following processing, transfers control to the debug monitor routine, and shifts to debug mode.
Page 169 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION (2) Restore Returning from debug trap processing is carried out by the DBRET instruction. By executing the DBRET instruction, the CPU carries out the following processing and controls the address of the restored PC. (1) Loads the restored PC and PSW from DBPC and DBPSW. (2) Transfers control to the address indicated by the restored PC and PSW.
Page 170: Multiple Interrupt Servicing Control
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.6 Multiple Interrupt Servicing Control Multiple interrupt servicing control is a process by which an interrupt request that is currently being processed can be interrupted during processing if there is an interrupt request with a higher priority level, and the higher priority interrupt request is received and processed first.
Page 171 CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION (2) Generation of exception in service program Service program of maskable interrupt or exception • EIPC saved to memory or register • EIPSW saved to memory or register • TRAP instruction ← Exception such as TRAP instruction acknowledged. •...
Page 172: Interrupt Response Time
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.7 Interrupt Response Time The following table describes the V850E/IA2 interrupt response time (from interrupt generation to start of interrupt servicing). Figure 7-14. Pipeline Operation at Interrupt Request Acknowledgment (Outline) 4 system clocks Internal clock Interrupt request Instruction 1 Instruction 2...
Page 173: Periods In Which Cpu Does Not Acknowledge Interrupts
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION 7.8 Periods in Which CPU Does Not Acknowledge Interrupts The CPU acknowledges an interrupt while an instruction is being executed. However, no interrupt will be acknowledged between an interrupt non-sample instruction and the next instruction (interrupt is held pending). The interrupt request non-sampling instructions are as follows.
Page 174: Chapter 8 Clock Generation Function
CHAPTER 8 CLOCK GENERATION FUNCTION The clock generator (CG) generates and controls the internal system clock (f ) that is supplied to each internal unit, such as the CPU. 8.1 Features • Multiplier function using a phase locked loop (PLL) synthesizer •...
Page 175: Input Clock Selection
CHAPTER 8 CLOCK GENERATION FUNCTION 8.3 Input Clock Selection The clock generator consists of an oscillator and a PLL synthesizer. For example, connecting a 4.0 MHz crystal resonator or ceramic resonator to the X1 and X2 pins enables a 40 MHz internal system clock (f ) to be generated when the multiplier is 10.
Page 176: Peripheral Command Register (Phcmd)
CHAPTER 8 CLOCK GENERATION FUNCTION value for which 10 × f Caution Only an f does not exceed the system clock maximum frequency (40 MHz) (i.e. 4 MHz) can be used for the oscillation frequency or external clock frequency. When 5 × f , 2.5 ×...
Page 177: Clock Control Register (Ckc)
CHAPTER 8 CLOCK GENERATION FUNCTION 8.3.4 Clock control register (CKC) The clock control register is an 8-bit register that controls the internal system clock (f ) in PLL mode. It can be written to only by a specific sequence combination so that it cannot easily be overwritten by mistake due to erroneous program execution.
Page 178 CHAPTER 8 CLOCK GENERATION FUNCTION Data is set in the clock control register (CKC) according to the following sequence. <1> Disable interrupts (set the NP bit of PSW to 1) <2> Prepare data in any one of the general-purpose registers to set in the specific register. <3>...
Page 179: Peripheral Status Register (Phs)
CHAPTER 8 CLOCK GENERATION FUNCTION 8.3.5 Peripheral status register (PHS) If a write operation is not performed in the correct sequence including access to the command register for the protection-targeted internal registers, writing is not performed and a protection error is generated, setting the status flag (PRERR) to 1.
Page 180: Pll Lockup
CHAPTER 8 CLOCK GENERATION FUNCTION 8.4 PLL Lockup The lockup time (frequency stabilization time) is the time from when the power is turned on or the software STOP mode is released until the phase locks at the prescribed frequency. The state until this stabilization occurs is called a lockup state, and the stabilized state is called a lock state.
Page 181: Power Save Control
CHAPTER 8 CLOCK GENERATION FUNCTION 8.5 Power Save Control 8.5.1 Overview The power save function has the following three modes. (1) HALT mode In this mode, the clock generator (oscillator and PLL synthesizer) continues to operate, but the CPU's operation clock stops. Since the supply of clocks to on-chip peripheral functions other than the CPU continues, operation continues.
Page 182 CHAPTER 8 CLOCK GENERATION FUNCTION Figure 8-1 shows the operation of the clock generator in normal operation mode, HALT mode, IDLE mode, and software STOP mode. An effective low power consumption system can be realized by combining these modes and switching modes according to the required use.
Page 183 CHAPTER 8 CLOCK GENERATION FUNCTION Table 8-1. Clock Generator Operation Using Power Save Control Clock Source Power Save Mode Oscillator Clock Supply Clock Synthesizer to Peripheral Supply to √ √ √ √ PLL mode Oscillation with Normal operation resonator √ √...
Page 184: Control Registers
CHAPTER 8 CLOCK GENERATION FUNCTION 8.5.2 Control registers (1) Power save mode register (PSMR) This is an 8-bit register that controls the power save mode. It is effective only when the STB bit of the PSC register is set to 1. Writing to the PSMR is executed by store instructions (ST/SST instruction) and bit manipulation instructions (SET1/CLR1/NOT1 instruction).
Page 185 CHAPTER 8 CLOCK GENERATION FUNCTION (3) Power save control register (PSC) This is an 8-bit register that controls the power save function. If releasing of interrupts are enabled by the setting of the NMIM and INTM bits, the software STOP mode can be released by an interrupt request (except when interrupt servicing is disabled by the interrupt mask registers (IMR0 to IMR3)).
Page 186 CHAPTER 8 CLOCK GENERATION FUNCTION [Sample coding] <1> ST.B r11, PSMR [r0] ; Set PSMR register <2> MOV 0×04, r10 ; Prepare data for setting specific register in general-purpose register <3> ST.B r10, PRCMD [r0] ; Write PRCMD register <4> ST.B r10, PSC [r0] ;...
Page 187: Halt Mode
CHAPTER 8 CLOCK GENERATION FUNCTION 8.5.3 HALT mode (1) Setting and operation status In the HALT mode, the clock generator (oscillator and PLL synthesizer) continues to operate, but the operation clock of the CPU is stopped. Since the supply of clocks to on-chip peripheral I/O units other than the CPU continues, operation continues.
Page 188 CHAPTER 8 CLOCK GENERATION FUNCTION (2) Release of HALT mode HALT mode is released by a non-maskable interrupt request, an unmasked maskable interrupt request, or RESET pin input. (a) Release by a non-maskable interrupt request or an unmasked maskable interrupt request HALT mode is released by a non-maskable interrupt request or by an unmasked maskable interrupt request regardless of the priority.
Page 189: Idle Mode
CHAPTER 8 CLOCK GENERATION FUNCTION 8.5.4 IDLE mode (1) Setting and operation status In the IDLE mode, the clock generator (oscillator and PLL synthesizer) continues to operate, but the supply of internal system clocks is stopped which causes the overall system to stop. When IDLE mode is released, the system can be switched to normal operation mode quickly because the oscillator's oscillation stabilization time or the PLL lockup time do not need to be secured.
Page 190 CHAPTER 8 CLOCK GENERATION FUNCTION (2) Release of IDLE mode IDLE mode is released by a non-maskable interrupt request, an unmasked maskable interrupt request Note (INTPn) , or RESET pin input (n = 0 to 4, 20 to 25). Note When a digital filter using clock sampling is selected as the noise eliminator for INTP20 to INTP25, IDLE mode cannot be released.
Page 191: Software Stop Mode
CHAPTER 8 CLOCK GENERATION FUNCTION 8.5.5 Software STOP mode (1) Setting and operation status In the software STOP mode, the clock generator (oscillator and PLL synthesizer) is stopped. The overall system is stopped, and ultra-low power consumption is achieved in which only leak current is lost. The system is switched to software STOP mode by using a store instruction (ST or SST instruction) or bit manipulation instruction (SET1, CLR1, or NOT1 instruction) to set the PSC and PSMR registers (see 8.5.2 Control registers).
Page 192 CHAPTER 8 CLOCK GENERATION FUNCTION (2) Release of software STOP mode Software STOP mode is released by a non-maskable interrupt request, an unmasked maskable interrupt Note request (INTPn) , or RESET pin input. Also, to release software STOP mode when PLL mode (CKSEL pin = low level) and resonator connection mode (CESEL bit of CKC register = 0) are used, the oscillator’s oscillation stabilization time must be secured (n = 0 to 4, 20 to 25) Moreover, the oscillation stabilization time must be secured even when an external clock is connected...
Page 193: Securing Oscillation Stabilization Time
CHAPTER 8 CLOCK GENERATION FUNCTION 8.6 Securing Oscillation Stabilization Time 8.6.1 Oscillation stabilization time security specification Two specification methods can be used to secure the time from when software STOP mode is released until the stopped oscillator stabilizes. (1) Securing the time using an on-chip time base counter Software STOP mode is released when a valid edge is input to the NMI pin or a maskable interrupt request is input (INTPn).
Page 194: Time Base Counter (Tbc)
CHAPTER 8 CLOCK GENERATION FUNCTION (2) Securing the time according to the signal level width (RESET pin input) Software STOP mode is released by falling edge input to the RESET pin. The time until the clock output from the oscillator stabilizes is secured based on the low-level width of the signal that is input to the pin.
Page 195: Chapter 9 Timer/Counter Function
CHAPTER 9 TIMER/COUNTER FUNCTION 9.1 Timer 0 9.1.1 Features (timer 0) Timers 00 and 01 (TM00, TM01) are 16-bit timer/counters ideal for controlling high-speed inverters such as motors. • 3-phase PWM output function PWM mode 0 (symmetric triangular wave) PWM mode 1 (asymmetric triangular wave) PWM mode 2 (sawtooth wave) •...
Page 196: Function Overview (Timer 0)
CHAPTER 9 TIMER/COUNTER FUNCTION 9.1.2 Function overview (timer 0) • 16-bit timer (TM0n) for 3-phase PWM inverter control: 2 channels • Compare registers: 6 registers × 2 channels • 12-bit dead-time timers (DTMn0 to DTMn2): 3 timers × 2 channels •...
Page 197: Functions Added To V850E/Ia2
CHAPTER 9 TIMER/COUNTER FUNCTION 9.1.3 Functions added to V850E/IA2 (1) Addition of BFCMn4 and CM0n4 registers, and BFCMn5 and CM0n5 registers When the TM0CEn bit of the TMC0n register is 1 (counting enabled), transferring data from the BFCMn4 or BFCMn5 register to the CM0n4 or CM0n5 register is enabled or disabled by the BFTEN bit of the TMC0n register (n = 0, 1).
Page 198: Basic Configuration
CHAPTER 9 TIMER/COUNTER FUNCTION 9.1.4 Basic configuration The basic configuration is shown below. Figure 9-1. Block Diagram of Timer 0 (Mode 0: Symmetric Triangular Wave, Mode 1: Asymmetric Triangular Wave) BFCMn3 INTCM0n3 CM0n3 INTTM0n TM0n Output control by external input (ESOn), 1/16 TM0n timer operation 1/32...
Page 199 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-2. Block Diagram of Timer 0 (Mode 2: Sawtooth Wave) BFCMn3 INTCM0n3 CM0n3 Clear Output control by TM0n external input (ESOn), TM0n timer operation 1/16 1/32 ALVTO DTRRn BFCMn0 CM0n0 Underflow DTMn0 TO0n0 (U phase) INTCM010 TO0n1 (U phase)
Page 200 CHAPTER 9 TIMER/COUNTER FUNCTION (1) Timers 00, 01 (TM00, TM01) TM0n operates as a 16-bit up/down timer or up timer. The cycle is controlled by compare register 0n3 (CM0n3) (n = 0, 1). TM0n start/stop is controlled by the TM0CEn bit of timer control register 0n (TMC0n). Division by the prescaler can be selected for the count clock from among f /2, f /4, f...
Page 201 CHAPTER 9 TIMER/COUNTER FUNCTION (2) Dead-time timers 00 to 02, 10 to 12 (DTM00 to DTM02, DTM10 to DTM12) DTMn0 to DTMn2 are dedicated 12-bit down timers that generate dead time, which is effective for inverter control applications. DTMn0 to DTMn2 operate as one-shot timers. Counting by a dead-time timer is enabled or disabled by the TM0CEDn bit of timer control register 0n (TMC0n) and cannot be controlled by software.
Page 202 CHAPTER 9 TIMER/COUNTER FUNCTION (5) Compare registers 004, 005, 014, 015 (CM004, CM005, CM014, CM015) CM0n4 and CM0n5 are 16-bit registers that always compare their value with TM0n. If the value of these registers matches the value of TM0n, the registers generate an interrupt signal (INTCM0n4 or INTCM0n5). CM0n4 and CM0n5 are also provided with a buffer register (BFCMn4 or BFCMn5), the contents of which are transferred to CM0n4 or CM0n5 at the next transfer timing.
Page 203 CHAPTER 9 TIMER/COUNTER FUNCTION Address After reset BFCM00 FFFFF572H FFFFH Address After reset BFCM10 FFFFF5B2H FFFFH Address After reset BFCM01 FFFFF574H FFFFH Address After reset BFCM11 FFFFF5B4H FFFFH Address After reset BFCM02 FFFFF576H FFFFH Address After reset BFCM12 FFFFF5B6H FFFFH Address After reset BFCM04...
Page 204 CHAPTER 9 TIMER/COUNTER FUNCTION (8) Buffer registers CM03, CM13 (BFCM03, BFCM13) BFCMn3 is a 16-bit register that transfers data to the compare register at any timing. Transfer enable or disable is controlled by the BFTE3 bit of the TMC0n register. BFCMn3 can be read/written in 16-bit units.
Page 205: Control Registers
CHAPTER 9 TIMER/COUNTER FUNCTION 9.1.5 Control registers (1) Timer 0 clock selection register (PRM01) The PRM01 register is used to select the base clock (f ) of timer 0 (TM0n). It can be read/written in 8-bit or 1-bit units. Caution Always set this register before using the timer. Address After reset PRM01...
Page 206 CHAPTER 9 TIMER/COUNTER FUNCTION (2) Timer control registers 00, 01 (TMC00, TMC01) TMC0n is a 16-bit register that sets the operation of timer 0 (TM0n). The TMC0n register can be read/written in 16-bit units. If the higher 8 bits of the TMC0n register are used as the TMC0nH register and the lower 8 bits as the TMC0nL register, the register can be read/written in 8-bit or 1-bit units.
Page 207 CHAPTER 9 TIMER/COUNTER FUNCTION (2/4) Bit position Bit name Function 13 to 11 CUL02 to CUL00 Cautions 1. The INTTM0n and INTCM0n3 interrupts can be culled at the same culling ratio (1/1, 1/2, 1/4, 1/8, 1/16). 2. Even when BFTE3 = 1, BFTEN = 1 (settings to transfer data from the BFCMn0 to BFCMn3 registers to the CM0n0 to CM0n3 registers), transfer is not performed at the generation timing of the culled INTTM0n and INTCM0n3 interrupts if MBFTE = 0.
Page 208 CHAPTER 9 TIMER/COUNTER FUNCTION (3/4) Bit position Bit name Function BFTE3 Specifies transfer of data from the BFCMn3 register to the CM0n3 register. 0: Transfer disabled 1: Transfer enabled The transfer timing from the BFCMn3 register to the CM0n3 register is as follows. BFCMn3 →...
Page 209 CHAPTER 9 TIMER/COUNTER FUNCTION (4/4) Bit position Bit name Function 1, 0 MOD01, Specifies the operation mode of TM0n. MOD00 BFCMn3 → Operation mode TM0n Timer clear BFCMn0 to operation source CM0n3 BFCMn2, timing BFCMn4, BFCMn5 → CM0n0 to CM0n2, CM0n4, CM0n5 timing...
Page 210 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-5. Interrupt Culling Processing (a) PWM mode 0 (symmetric triangular wave) CM0n3 TM0n count value 0000H Interrupt request INTTM0n INTTM0n INTTM0n INTTM0n occurrence occurrence occurrence occurrence CUL02 to CUL00 Interrupt culling Interrupt culling 1/1 cycle 1/2 cycle Remark n = 0, 1...
Page 211 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-6. Interrupt Culling Ratio Change Timing (Relationship Between STINTn Bit Setting and CUL Bit Change): PWM Mode 1 (Asymmetric Triangular Wave) TM0CEn bit CM0n3 TM0n count value 0000H INTTM0n INTTM0n INTTM0n INTTM0n INTTM0n INTTM0n INTTM0n INTTM0n STINTn = 1 INTCM0n3 INTCM0n3 INTCM0n3 INTCM0n3...
Page 212 CHAPTER 9 TIMER/COUNTER FUNCTION (3) Timer unit control registers 00, 01 (TUC00, TUC01) TUC0n is an 8-bit register that controls the TO0n0 to TO0n5 outputs. TUC0n can be read/written in 8-bit or 1-bit units. However, bit 0 is read-only. <1> <0>...
Page 213 CHAPTER 9 TIMER/COUNTER FUNCTION (4) Timer output mode registers 0, 1 (TOMR0, TOMR1) The TOMRn register controls timer output from the TO0n0 to TO0n5 pins. To prevent abnormal output from the TO0n0 to TO0n5 pins due to illegal access, data is written to the TOMRn register in the following two sequences.
Page 214 CHAPTER 9 TIMER/COUNTER FUNCTION (2/2) Bit position Bit name Function ALVVB Specifies the output level of the TO0n3 pin. 0: Inverted level of active level set by ALVTO bit 1: Active level set by ALVTO bit When ALVVB = 1, the output level of TO0n3 output is the same as TO0n2. Caution Changing the ALVVB bit during TM0n operation (TM0CEn = 1) is prohibited ALVWB...
Page 215 CHAPTER 9 TIMER/COUNTER FUNCTION Examples of the output waveforms of TO000 and TO001 when the higher 4 bits (ALVTO, ALVUB, ALVVB, and ALVWB) of the TOMRn register are set in PWM mode 0 (asymmetric triangular waves) are shown below. Figure 9-7. Output Waveforms of TO000 and TO001 in PWM Mode 0 (Symmetric Triangular Waves) (Without Dead Time (TM0CED0 Bit = 1)) (a) TOMR0 register value = 80H TM00 = CM000...
Page 216 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-8. Output Waveforms of TO000 and TO001 in PWM Mode 0 (Symmetric Triangular Waves) (With Dead Time (TM0CED0 Bit = 0)) (a) TOMR0 register value = 80H TM00 = CM000 TM00 = CM000 TO000 TO001 Dead time period Dead time period (b) TOMR0 register value = 00H...
Page 217 CHAPTER 9 TIMER/COUNTER FUNCTION Data is set to timer output mode registers 0 and 1 (TOMR0, TOMR1) in the following sequence. <1> Prepare the data to be set to timer output mode registers 0 and 1 (TOMR0, TOMR1) in a general-purpose register.
Page 218 CHAPTER 9 TIMER/COUNTER FUNCTION (5) PWM output enable registers 0, 1 (POER0, POER1) The POERn register is used to make the external pulse output (TO0n0 to TO0n5) status inactive by software. POERn can be read/written in 8-bit or 1-bit units. <5>...
Page 219 CHAPTER 9 TIMER/COUNTER FUNCTION (6) PWM software timing output registers 0, 1 (PSTO0, PSTO1) The PSTOn register is used to perform settings to output the desired waveforms to the external pulse output pins (TO0n0 to TO0n5) by software. PSTOn can be read/written in 8-bit or 1-bit units. Cautions 1.
Page 220 CHAPTER 9 TIMER/COUNTER FUNCTION (1/2) <7> <2> <1> <0> Address After reset PSTO0 TORTO0 UPORT0 VPORT0 WPORT0 FFFFF57EH <7> <2> <1> <0> Address After reset PSTO1 TORTO1 UPORT1 VPORT1 WPORT1 FFFFF5BEH Bit position Bit name Function TORTOn Specifies TO0n0 to TO0n5 output control. 0: Timer output 1: Software output The change of the TO0n0 to TO0n5 signals during software output occurs when the...
Page 221 CHAPTER 9 TIMER/COUNTER FUNCTION (2/2) Bit position Bit name Function WPORTn Specifies the TO0n4 (W phase)/TO0n5 (W phase) pin output value. WPORTn Operation TO0n4 Inverted level of ALVTO bit setting TO0n5 When ALVWB = 0 Level of ALVTO bit setting When ALVWB = 1 Inverted level of ALVTO bit setting TO0n4...
Page 222 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-9. When UPORTn = 1 Is Set Immediately Before TORTOn = 0 (Switched by Active Value) CM0n3 CM0n3 CM0n3 CM0n3 TM0n Count value 0000H Note 1 Note 2 Note 2 Note 1 Note 2 Note 3 Note 4 INTCM0n3 INTTM0n...
Page 223 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-10. When UPORTn = 0 Is Set Immediately Before TORTOn = 0 (Switched by Inactive Value) CM0n3 CM0n3 CM0n3 CM0n3 TM0n Count value 0000H Note 2 Note 3 Note 1 Note 1 Note 2 Note 4 INTCM0n3 INTTM0n TO0n0...
Page 224 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-11. When UPORTn = 0 Is Set Immediately Before TORTOn = 1 CM0n3 CM0n3 CM0n3 CM0n3 TM0n Count value 0000H Note 2 Note 1 Note 1 Note 2 Note 1 Note 3 INTCM0n3 Note 4 INTTM0n TO0n0 TM0CEn...
Page 225 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-12. Software Output Waveforms of TO000 and TO001 (Without Dead Time (TM0CED0 = 1)) (a) TOMR0 register value = 80H UPORT0 ← 1 UPORT0 ← 0 TO000 TO001 (b) TOMR0 register value = 00H UPORT0 ← 1 UPORT0 ←...
Page 226 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-13. Software Output Waveforms of TO000 and TO001 (With Dead Time (TM0CED0 = 0)) (a) TOMR0 register value = 80H UPORT0 ← 1 UPORT0 ← 0 TO000 TO001 Dead-time period Dead-time period (b) TOMR0 register value = 00H UPORT0 ←...
Page 227 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-14. Software Output Waveforms of TO000 and TO001 When “1” Is Written to UPORT0 Bit While TORTO0 = 1 (When TOMR0 Register Value = 80H) (a) Without dead time (TM0CED0 = 1) UPORT0 ← 1 UPORT0 ←...
Page 228 CHAPTER 9 TIMER/COUNTER FUNCTION (7) TOMR write enable registers 0, 1 (SPEC0, SPEC1) The SPECn register enables writing to the TOMRn register. Unless writing to the TOMRn register is performed immediately after writing to the SPECn register (any data can be written), write processing to the TOMRn register is not performed normally.
Page 229: Operation
CHAPTER 9 TIMER/COUNTER FUNCTION 9.1.6 Operation Remarks 1. In the explanation of operations in this section, the bits that affect the TO0n0 to TO0n5 outputs are assumed to be set as follows. ALVTO = 1, ALVUB = 0, ALVVB = 0, ALVWB = 0, TORTOn =0 2.
Page 230 CHAPTER 9 TIMER/COUNTER FUNCTION Table 9-4. Operation Modes of Timer 0 (TM0n) BFCMn3 → TMC0n Register Operation Mode TM0n Timer Clear Interrupt BFCMn0 to BFCMn2, BFCMn4, BFCMn5 → Operation Source Source CM0n3 MOD01 MOD00 Timing CM0n0 to CM0n2, CM0n4, CM0n5 Timing −...
Page 231 CHAPTER 9 TIMER/COUNTER FUNCTION (2) PWM mode 0: Triangular wave modulation (right-left symmetric waveform control) [Setting procedure] (a) Set PWM mode 0 (symmetric triangular wave) using the MOD01 and MOD00 bits of the TMC0n register. Also set the active level of the TO0n0 to TO0n5 pins using the ALVTO bit of the TOMRn register (n = 0, (b) Set the count clock of TM0n using the PRM02 to PRM00 bits of the TMC0n register.
Page 232 CHAPTER 9 TIMER/COUNTER FUNCTION [Operation] In PWM mode 0, TM0n performs up/down count operation. When TM0n = 0000H during down counting, an underflow interrupt (INTTM0n) is generated, and when TM0n = CM0n3 during up counting, a match interrupt (INTCM0n3) is generated (n = 0, 1). Switching from up counting to down counting is performed when TM0n and CM0n3 match (INTCM0n3), and switching from down counting to up counting is performed when a TM0n underflow occurs after TM0n becomes 0000H.
Page 233 CHAPTER 9 TIMER/COUNTER FUNCTION [Output waveform width with respect to set value] • PWM cycle = BFCMn3 × 2 × T TM0n • Dead-time width = (DTRRn + 1)/f • Active width of positive phase (TO0n0, TO0n2, TO0n4 pins) = { (CM0n3 − CM0nX ) + (CM0n3 −...
Page 234 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-15. Operation Timing in PWM Mode 0 (Symmetric Triangular Wave) (1/2) (a) Operation timing of compare registers 0n0 to 0n2 (CM0n0 to CM0n2) CM0n3 (d) CM0n3 (e) TM0n count value 0000H CM0nx CM0nx CM0nx CM0nx match match match...
Page 235 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-15. Operation Timing in PWM Mode 0 (Symmetric Triangular Wave) (2/2) (b) Operation timing of compare registers 0n4 and 0n5 (CM0n4, CM0n5) CM0n3 (d) CM0n3 (e) TM0n count value 0000H CM0nx CM0nx CM0nx CM0nx match match match match...
Page 236 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-16. Overall Operation Image of PWM Mode 0 (Symmetric Triangular Wave) CM0n3 CM0n3 CM0n2 CM0n2 CM0n2 CM0n2 CM0n1 CM0n1 CM0n1 CM0n1 TM0n count value CM0n0 CM0n0 CM0n0 CM0n0 0000H TO0n0 output TO0n1 output TO0n2 output Without dead time TO0n3 output...
Page 237 CHAPTER 9 TIMER/COUNTER FUNCTION Next, an example of the operation timing, which depends on the values set to CM0n0 to CM0n2, CM0n4, and CM0n5 (BFCMn0 to BFCMn2, BFCMn4, BFCMn5) is shown. (a) When CM0nx (BFCMnx) ≥ CM0n3 is set Figure 9-17. Operation Timing in PWM Mode 0 (Symmetric Triangular Wave, BFCMnx ≥ CM0n3) (1/2) (a) Operation timing of compare registers 0n0 to 0n2 (CM0n0 to CM0n2) CM0n3 CM0n3...
Page 238 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-17. Operation Timing in PWM Mode 0 (Symmetric Triangular Wave, BFCMnx ≥ CM0n3) (2/2) (b) Operation timing of compare registers 0n4 and 0n5 (CM0n4, CM0n5) CM0n3 CM0n3 TM0n count value 0000H CM0nx CM0nx CM0nx match match match (BFCMnx = CM0n3)
Page 239 CHAPTER 9 TIMER/COUNTER FUNCTION (b) When CM0nx (BFCMnx) = 0000H is set Figure 9-18. Operation Timing in PWM Mode 0 (Symmetric Triangular Wave, BFCMnx = 0000H) (1/2) (a) Operation timing of compare registers 0n0 to 0n2 (CM0n0 to CM0n2) CM0n3 CM0n3 TM0n count value...
Page 240 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-18. Operation Timing in PWM Mode 0 (Symmetric Triangular Wave, BFCMnx = 0000H) (2/2) (b) Operation timing of compare registers 0n4 and 0n5 (CM0n4, CM0n5) CM0n3 CM0n3 TM0n count value 0000H CM0nx CM0nx CM0nx CM0nx match match match...
Page 241 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-19. Change Timing from 100% Duty State (PWM Mode 0) (1/2) (a) Operation timing of compare registers 0n0 to 0n2 (CM0n0 to CM0n2) CM0n3 CM0n3 CM0n3 CM0n3 TM0n count value CM0nx CM0nx CM0nx CM0nx CM0nx CM0nx match match...
Page 242 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-19. Change Timing from 100% Duty State (PWM Mode 0) (2/2) (b) Operation timing of compare registers 0n4 and 0n5 (CM0n4, CM0n5) CM0n3 CM0n3 CM0n3 CM0n3 TM0n count value CM0nx CM0nx CM0nx CM0nx CM0nx CM0nx match match match...
Page 243 CHAPTER 9 TIMER/COUNTER FUNCTION (3) PWM mode 1: Triangular wave modulation (right-left asymmetric waveform control) [Setting procedure] (a) Set PWM mode 1 (asymmetric triangular wave) using the MOD01 and MOD00 bits of the TMC0n register. Also set the active level of the TO0n0 to TO0n5 pins using the ALVTO bit of the TOMRn register (n = 0, 1).
Page 244 CHAPTER 9 TIMER/COUNTER FUNCTION [Operation] In PWM mode 1, TM0n performs up/down count operation. When TM0n = 0000H during down counting, an underflow interrupt (INTTM0n) is generated, and when TM0n = CM0n3 during up counting, a match interrupt (INTCM0n3) is generated (n = 0, 1). Switching from up counting to down counting is performed when TM0n and CM0n3 match (INTCM0n3), and switching from down counting to up counting is performed by INTTM0n.
Page 245 CHAPTER 9 TIMER/COUNTER FUNCTION [Output waveform width with respect to set value] • PWM cycle = BFCMn3 × 2 × T TM0n • Dead time width = (DTRRn + 1)/f • Active width of positive phase (TO0n0, TO0n2, TO0n4 pins) = { (CM0n3 −...
Page 246 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-20. Operation Timing in PWM Mode 1 (Asymmetric Triangular Wave) (1/2) (a) Operation timing of compare registers 0n0 to 0n2 (CM0n0 to CM0n2) CM0n3 (f) CM0n3 (g) TM0n count value 0000H CM0nx CM0nx CM0nx CM0nx match match match...
Page 247 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-20. Operation Timing in PWM Mode 1 (Asymmetric Triangular Wave) (2/2) (b) Operation timing of compare registers 0n4 and 0n5 (CM0n4, CM0n5)) CM0n3 (f) CM0n3 (g) TM0n count value 0000H CM0nx CM0nx CM0nx CM0nx match match match match...
Page 248 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-21. Overall Operation Image of PWM Mode 1 (Asymmetric Triangular Wave) CM0n3 CM0n3 CM0n2 CM0n2 CM0n2 CM0n2 CM0n1 CM0n1 TM0n CM0n1 CM0n1 CM0n0 count value CM0n0 CM0n0 CM0n0 0000H TO0n0 output TO0n1 output TO0n2 output Without dead time TO0n3 output...
Page 249 CHAPTER 9 TIMER/COUNTER FUNCTION (a) When BFCMnx ≥ CM0n3 is set in software processing started by INTCM0n3 Figure 9-22. Operation Timing in PWM Mode 1 (Asymmetric Triangular Wave, BFCMnx ≥ CM0n3) (1/2) (a) Operation timing of compare registers 0n0 to 0n2 (CM0n0 to CM0n2) CM0n3 CM0n3 TM0n...
Page 250 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-22. Operation Timing in PWM Mode 1 (Asymmetric Triangular Wave, BFCMnx ≥ CM0n3) (2/2) (b) Operation timing of compare registers 0n4 and 0n5 (CM0n4, CM0n5) CM0n3 CM0n3 TM0n count value 0000H CM0nx CM0nx CM0nx match match match (BFCMnx = CM0n3)
Page 251 CHAPTER 9 TIMER/COUNTER FUNCTION (b) When BFCMnx > CM0n3 is set in software processing started by INTTM0n Figure 9-23. Operation Timing in PWM Mode 1 (Asymmetric Triangular Wave, BFCMnx > CM0n3) (1/2) (a) Operation timing of compare registers 0n0 to 0n2 (CM0n0 to CM0n2) CM0n3 CM0n3 TM0n...
Page 252 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-23. Operation Timing in PWM Mode 1 (Asymmetric Triangular Wave, BFCMnx > CM0n3) (2/2) (b) Operation timing of compare registers 0n4 and 0n5 (CM0n4, CM0n5) CM0n3 CM0n3 TM0n count value 0000H CM0nx match BFCMnx CM0nx INTCM0n3 INTTM0n INTCM0n3...
Page 253 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-24. Change Timing from 100% Duty State (PWM Mode 1) (1/2) (a) Operation timing of compare registers 0n0 to 0n2 (CM0n0 to CM0n2) CM0n3 CM0n3 CM0n3 CM0n3 TM0n count value 0000H CM0nx CM0nx CM0nx match match match BFCM0nx...
Page 254 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-24. Change Timing from 100% Duty State (PWM Mode 1) (2/2) (b) Operation timing of compare registers 0n4 and 0n5 (CM0n4, CM0n5) CM0n3 CM0n3 CM0n3 CM0n3 TM0n count value 0000H CM0nx CM0nx CM0nx match match match BFCM0nx CM0nx...
Page 255 CHAPTER 9 TIMER/COUNTER FUNCTION (c) When BFCMnx = 0000H is set in software processing started by INTCM0n3 Figure 9-25. Operation Timing in PWM Mode 1 (Asymmetric Triangular Wave, BFCMnx = 0000H) (1) (1/2) (a) Operation timing of compare registers 0n0 to 0n2 (CM0n0 to CM0n2) CM0n3 CM0n3 TM0n...
Page 256 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-25. Operation Timing in PWM Mode 1 (Asymmetric Triangular Wave, BFCMnx = 0000H) (1) (2/2) (b) Operation timing of compare registers 0n4 and 0n5 (CM0n4, CM0n5) CM0n3 CM0n3 TM0n count value 0000H CM0nx CM0nx CM0nx CM0nx match match...
Page 257 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-26. Change Timing from 100% Duty State (1) (PWM Mode 1) (1/2) (a) Operation timing of compare registers 0n0 to 0n2 (CM0n0 to CM0n2) CM0n3 CM0n3 CM0n3 CM0n3 TM0n count value 0000H CM0nx CM0nx CM0nx CM0nx CM0nx CM0nx...
Page 258 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-26. Change Timing from 100% Duty State (1) (PWM Mode 1) (2/2) (b) Operation timing of compare registers 0n4 and 0n5 (CM0n4, CM0n5) CM0n3 CM0n3 CM0n3 CM0n3 TM0n count value 0000H CM0nx CM0nx CM0nx CM0nx CM0nx CM0nx match...
Page 259 CHAPTER 9 TIMER/COUNTER FUNCTION (d) When BFCMnx = 0000H is set in software processing started by INTTM0n Figure 9-27. Operation Timing in PWM Mode 1 (Asymmetric Triangular Wave, BFCMnx = 0000H) (2) (1/2) (a) Operation timing of compare registers 0n0 to 0n2 (CM0n0 to CM0n2) CM0n3 CM0n3 TM0n...
Page 260 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-27. Operation Timing in PWM Mode 1 (Asymmetric Triangular Wave, BFCMnx = 0000H) (2) (2/2) (b) Operation timing of compare registers 0n4 and 0n5 (CM0n4, CM0n5) CM0n3 CM0n3 TM0n count value 0000H CM0nx CM0nx CM0nx match match match...
Page 261 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-28. Change Timing from 100% Duty State (2) (PWM Mode 1) (1/2) (a) Operation timing of compare registers 0n0 to 0n2 (CM0n0 to CM0n2) CM0n3 CM0n3 CM0n3 CM0n3 TM0n count value 0000H CM0nx CM0nx CM0nx CM0nx CM0nx match...
Page 262 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-28. Change Timing from 100% Duty State (2) (PWM Mode 1) (2/2) (b) Operation timing of compare registers 0n4 and 0n5 (CM0n4, CM0n5) CM0n3 CM0n3 CM0n3 CM0n3 TM0n count value 0000H CM0nx CM0nx CM0nx CM0nx CM0nx match match...
Page 263 CHAPTER 9 TIMER/COUNTER FUNCTION (e) When BFCMnx = CM0n3 is set in software processing started by INTTM0n Figure 9-29. Operation Timing in PWM Mode 1 (Asymmetric Triangular Wave, BFCMnx = CM0n3) (1/2) (a) Operation timing of compare registers 0n0 to 0n2 (CM0n0 to CM0n2) CM0n3 CM0n3 TM0n...
Page 264 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-29. Operation Timing in PWM Mode 1 (Asymmetric Triangular Wave, BFCMnx = CM0n3) (2/2) (b) Operation timing of compare registers 0n4 and 0n5 (CM0n4, CM0n5) CM0n3 CM0n3 TM0n count value 0000H CM0nx CM0nx CM0nx match match match BFCMnx...
Page 265 CHAPTER 9 TIMER/COUNTER FUNCTION (4) PWM mode 2: Sawtooth wave modulation [Setting procedure] (a) Set PWM mode 2 (sawtooth wave) using the MOD01 and MOD00 bits of the TMC0n register. Also set the active level of the TO0n0 to TO0n5 pins using the ALVTO bit of the TOMRn register. (b) Set the count clock of TM0n using the PRM02 to PRM00 bits of the TMC0n register.
Page 266 CHAPTER 9 TIMER/COUNTER FUNCTION [Operation] In PWM mode 2, TM0n performs up count operation, and when it matches the value of CM0n3, match interrupt INTCM0n3 is generated and TM0n is cleared (n = 0, 1). The PWM cycle in this mode is ((BFCMn3 value + 1) × TM0n count clock). Note that the next PWM cycle width is set to BFCMn3.
Page 267 CHAPTER 9 TIMER/COUNTER FUNCTION [Output waveform width with respect to set value] • PWM cycle = (BFCMn3 + 1) × T TM0n • Dead time width = (DTRRn + 1)/f • Active width of positive phase (TO0n0, TO0n2, TO0n4 pins) = (CM0nX + 1) ×...
Page 268 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-30. Operation Timing in PWM Mode 2 (Sawtooth Wave) (1/2) (a) Operation timing of compare registers 0n0 to 0n2 (CM0n0 to CM0n2) CM0n3 (d) CM0n3 (e) TM0n count value 0000H CM0nx CM0nx match match BFCMnx CM0nx BFCMn3 CM0n3...
Page 269 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-30. Operation Timing in PWM Mode 2 (Sawtooth Wave) (2/2) (b) Operation timing of compare registers 0n4 and 0n5 (CM0n4, CM0n5) CM0n3 (d) CM0n3 (e) TM0n count value 0000H CM0nx CM0nx match match BFCMnx CM0nx BFCMn3 CM0n3 Interrupt request...
Page 270 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-31. Overall Operation Image of PWM Mode 2 (Sawtooth Wave) CM0n3 CM0n3 CM0n2 CM0n2 CM0n1 CM0n1 TM0n CM0n0 CM0n0 count value 0000H TO0n0 output TO0n1 output TO0n2 output Without dead time TO0n3 output TO0n4 output TO0n5 output TO0n0 output TO0n1 output...
Page 271 CHAPTER 9 TIMER/COUNTER FUNCTION (a) When BFCMnx > CM0n3 is set Figure 9-32. Operation Timing in PWM Mode 2 (Sawtooth Wave, BFCMnx > CM0n3) (1/2) (a) Operation timing of compare registers 0n0 to 0n2 (CM0n0 to CM0n2) CM0n3 CM0n3 CM0n3 TM0n count value 0000H...
Page 272 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-32. Operation Timing in PWM Mode 2 (Sawtooth Wave, BFCMnx > CM0n3) (2/2) (b) Operation timing of compare registers 0n4 and 0n5 (CM0n4, CM0n5) CM0n3 CM0n3 CM0n3 TM0n count value 0000H CM0nx match BFCMnx CM0nx Interrupt request INTCM0nx INTCM0n3...
Page 273 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-33. Change Timing from 100% Duty State (PWM Mode 2) (1/2) (a) Operation timing of compare registers 0n0 to 0n2 (CM0n0 to CM0n2) CM0n3 CM0n3 CM0n3 CM0n3 TM0n count value 0000H CM0nx CM0nx match match BFCM0nx CM0nx INTCM01x...
Page 274 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-33. Change Timing from 100% Duty State (PWM Mode 2) (2/2) (b) Operation timing of compare registers 0n4 and 0n5 (CM0n4, CM0n5) CM0n3 CM0n3 CM0n3 CM0n3 TM0n count value 0000H CM0nx CM0nx match match BFCM0nx CM0nx INTCM0nx INTCM0n3...
Page 275 CHAPTER 9 TIMER/COUNTER FUNCTION (b) When BFCMnx = CM0n3 is set Figure 9-34. Operation Timing in PWM Mode 2 (Sawtooth Wave, BFCMnx = CM0n3) (1/2) (a) Operation timing of compare registers 0n0 to 0n2 (CM0n0 to CM0n2) CM0n3 CM0n3 CM0n3 TM0n count value 0000H...
Page 276 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-34. Operation Timing in PWM Mode 2 (Sawtooth Wave, BFCMnx = CM0n3) (2/2) (b) Operation timing of compare registers 0n4 and 0n5 (CM0n4, CM0n5) CM0n3 CM0n3 CM0n3 TM0n count value 0000H CM0nx CM0nx CM0nx CM0nx match match match...
Page 277 CHAPTER 9 TIMER/COUNTER FUNCTION (c) When BFCMnx = 0000H is set Figure 9-35. Operation Timing in PWM Mode 2 (Sawtooth Wave, BFCMnx = 0000H) (1/2) (a) Operation timing of compare registers 0n0 to 0n2 (CM0n0 to CM0n2) CM0n3 CM0n3 CM0n3 TM0n count value 0000H...
Page 278 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-35. Operation Timing in PWM Mode 2 (Sawtooth Wave, BFCMnx = 0000H) (2/2) (b) Operation timing of compare registers 0n4 and 0n5 (CM0n4, CM0n5) CM0n3 CM0n3 CM0n3 TM0n count value 0000H CM0nx CM0nx CM0nx CM0nx match match match...
Page 279 CHAPTER 9 TIMER/COUNTER FUNCTION (d) When BFCMnx = 0000H is set while DTMnx = 000H or TM0CEDn bit = 1 A pulse equivalent to one count clock of the timer is output. Figure 9-36. Operation Timing in PWM Mode 2 (Sawtooth Wave, BFCMnx = 0000H) While DTMnx = 000H or TM0CEDn Bit = 1 (1/2) (a) Operation timing of compare registers 0n0 to 0n2 (CM0n0 to CM0n2) CM0n3...
Page 280 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-36. Operation Timing in PWM Mode 2 (Sawtooth Wave, BFCMnx = 0000H While DTMnx = 000H or TM0CEDn Bit = 1) (2/2) (b) Operation timing of compare registers 0n4 and 0n5 (CM0n4, CM0n5) CM0n3 CM0n3 CM0n3 TM0n count value...
Page 281 CHAPTER 9 TIMER/COUNTER FUNCTION (e) When BFCMnx = CM0n3 = a is set Figure 9-37. Operation Timing in PWM Mode 2 (Sawtooth Wave, BFCMnx = CM0n3 = a) (When DTRRn = 0000H, TM0CEDn Bit of TMC0n Register = 1, ALVTO Bit of TOMRn Register = 1 (PWM Driving, Active Level = High) Are Set) (1/2) (a) Operation timing of compare registers 0n0 to 0n2 (CM0n0 to CM0n2) CM0n3...
Page 282 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-37. Operation Timing in PWM Mode 2 (Sawtooth Wave, BFCMnx = CM0n3 = a) (When DTRRn = 0000H, TM0CEDn Bit of TMC0n Register = 1, ALVTO Bit of TOMRn Register = 1 (PWM Driving, Active Level = High) Are Set) (2/2) (b) Operation timing of compare registers 0n4 and 0n5 (CM0n4, CM0n5) CM0n3 CM0n3...
Page 283 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-38. Operation Timing in PWM Mode 2 (Sawtooth Wave, BFCMnx = CM0n3 = a) (When DTRRn = 0000H, TM0CEDn Bit of TMC0n Register = 1, ALVTO Bit of TOMRn Register = 0 (PWM Driving, Active Level = Low) Are Set) (1/2) (a) Operation timing of compare registers 0n0 to 0n2 (CM0n0 to CM0n2) CM0n3 CM0n3...
Page 284 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-38. Operation Timing in PWM Mode 2 (Sawtooth Wave, BFCMnx = CM0n3 = a) (When DTRRn = 0000H, TM0CEDn Bit of TMC0n Register = 1, ALVTO Bit of TOMRn Register = 0 (PWM Driving, Active Level = Low) Are Set) (2/2) (b) Operation timing of compare registers 0n4 and 0n5 (CM0n4, CM0n5) CM0n3 CM0n3...
Page 285: Operation Timing
CHAPTER 9 TIMER/COUNTER FUNCTION 9.1.7 Operation timing (1) TM0CEn bit write and TM0n timer operation timing Figure 9-39 shows the timing from when the TM0CEn bit of the TMC0n register is written until the TM0n timer starts operating. Figure 9-39. TM0CEn Bit Write and TM0n Timer Operation Timing TM0CEn bit write timing Register write timing...
Page 286 CHAPTER 9 TIMER/COUNTER FUNCTION (2) Interrupt generation timing The interrupt generation timing at the TM0n count clock settings (PRM02 to PRM00 bits of the TMC0n register) in the various modes is described below. Figure 9-40. Interrupt Generation Timing in PWM Mode 0 (Symmetric Triangular Wave), PWM Mode 1 (Asymmetric Triangular Wave) (a) When count clock = f 0002H...
Page 287 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-41. Interrupt Generation Timing in PWM Mode 2 (Sawtooth Wave) (a) When count clock = f 0002H CM0nx TM0n 0001H 0002H 0000H 0001H 0002H 0000H 0001H 0002H 0000H 0001H 0002H 0000H 0001H 0002H 0000H 0001H 0002H 0000H 0001H 0002H INTCM0nx (b) When count clock = f 0002H...
Page 288 CHAPTER 9 TIMER/COUNTER FUNCTION (3) Relationship between interrupt generation and STINTn bit of TMC0n register The interrupt generation timing for the setting of the STINTn bit of the TMC0n register and the interrupt culling ratio setting (bits CUL02 to CUL00) in the various modes is described below. If, to realize the INTTM0n and INTCM0n3 interrupt culling function for TM0n, bits CUL02 to CUL00 of the TMC0n register are set for a culling ratio other than 1/1, and count operation is started, the interrupt output order differs according to the setting of the STINTn bit when counting starts.
Page 289 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-43. Interrupt Generation Timing in PWM Mode 0 (Symmetric Triangular Wave), PWM Mode 1 (Asymmetric Triangular Wave): In Case of Interrupt Culling Ratio of 1/2 (a) When STINTn bit = 0 TM0CEn bit 0004H CM0n3 TM0n 0000H 0001H 0002H 0003H 0004H 0003H 0002H 0001H 0000H 0001H 0002H 0003H 0004H 0003H 0002H 0001H 0000H 0001H 0002H 0003H INTCM0n3...
Page 290 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-44. Interrupt Generation Timing in PWM Mode 2 (Sawtooth Wave): In Case of Interrupt Culling Ratio of 1/1 (a) When STINTn bit = 0 TM0CEn bit 0004H CM0n3 TM0n 0000H 0001H 0002H 0003H 0004H 0000H 0001H 0002H 0003H 0004H 0000H 0001H 0002H 0003H 0004H 0000H 0001H 0002H 0003H INTCM0n3 (b) When STINTn bit = 1 TM0CEn bit...
Page 291 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-45. Interrupt Generation Timing in PWM Mode 2 (Sawtooth Wave): In Case of Interrupt Culling Ratio of 1/2 (a) When STINTn bit = 0 TM0CEn bit 0004H CM0n3 TM0n 0000H 0001H 0002H 0003H 0004H 0000H 0001H 0002H 0003H 0004H 0000H 0001H 0002H 0003H 0004H 0000H 0001H 0002H 0003H INTCM0n3 (b) When STINTn bit = 1 TM0CEn bit...
Page 292 CHAPTER 9 TIMER/COUNTER FUNCTION (4) TO0n0 to TO0n5 output timing Figure 9-46. TO0n0 to TO0n5 Output Timing in PWM Mode 0 (Symmetric Triangular Wave), PWM Mode 1 (Asymmetric Triangular Wave) TM0CEn bit 0008H CM0n3 0003H CM0nx TM0n 0000H 0001H 0002H 0003H 0004H 0005H 0006H 0007H 0008H 0007H 0006H 0005H 0004H 0003H 0002H 0001H 0000H 0001H 0002H 0003H 0002H DTRRn...
Page 293 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-47. TO0n0 to TO0n5 Output Timing in PWM Mode 2 (Sawtooth Wave) TM0CEn bit 000AH CM0n3 CM0nx 0005H TM0n 0000H 0001H 0002H 0003H 0004H 0005H 0006H 0007H 0008H 0009H 000AH 0000H 0001H 0002H 0003H 0004H 0005H 0006H 0002H DTRRn DTMnx...
Page 294: Timer 1
CHAPTER 9 TIMER/COUNTER FUNCTION 9.2 Timer 1 9.2.1 Features (timer 1) Timer 10 (TM10) is a 16-bit up/down counter that performs the following operations. • General-purpose timer mode (See 9.2.5 (1) Operation in general-purpose timer mode.) Free-running timer PWM output •...
Page 295 CHAPTER 9 TIMER/COUNTER FUNCTION • PWM output function In the general-purpose timer mode, 16-bit resolution PWM can be output from the TO10 pin. • Timer clear The following timer clear operations are performed according to the mode that is used. (a) General-purpose timer mode: Timer clear operation is possible upon occurrence of match with CM100 set value.
Page 296: Basic Configuration
CHAPTER 9 TIMER/COUNTER FUNCTION 9.2.3 Basic configuration The basic configuration is shown below. Table 9-5. Timer 1 Configuration List Timer Count Clock Register Read/Write Generated Capture Trigger Interrupt Signal − − Timer 1 TM10 Read/write − CM100 Read/write INTCM100 /16, −...
Page 297 CHAPTER 9 TIMER/COUNTER FUNCTION (1) Timer 10 (TM10) TM10 is a general-purpose timer (in general-purpose mode) and 2-phase encoder input up/down counter (in UDC mode). This timer counts up in the general-purpose timer mode and counts up/down in the UDC mode. It can be read/written in 16-bit units.
Page 298 CHAPTER 9 TIMER/COUNTER FUNCTION Table 9-6. Timer 1 (TM10) Clear Conditions Operation Mode TUM0 Register TMC10 Register TM10 Clear MSEL ENMD CLR1 CLR0 × × General-purpose Clearing not performed (free-running timer) timer mode × × Cleared upon match with CM100 set value ×...
Page 299: Control Registers
CHAPTER 9 TIMER/COUNTER FUNCTION 9.2.4 Control registers (1) Timer 1/timer 2 clock selection register (PRM02) The PRM02 register is used to select the base clock (f ) of timer 1 and timer 2. This register can be read/written in 8-bit or 1-bit units. Cautions 1.
Page 300 CHAPTER 9 TIMER/COUNTER FUNCTION (2) Timer unit mode register 0 (TUM0) The TUM0 register is an 8-bit register used to specify the TM10 operation mode or to control the operation of the PWM output pin. TUM0 can be read/written in 8-bit or 1-bit units. Cautions 1.
Page 301 CHAPTER 9 TIMER/COUNTER FUNCTION (3) Timer control register 10 (TMC10) The TMC10 register is used to enable/disable TM10 operation and to set transfer and timer clear operations. TMC10 can be read/written in 8-bit or 1-bit units. Caution Changing the values of the TMC10 register bits other than the TM1CE0 bit during TM10 operation (TM1CE0 = 1) is prohibited.
Page 302 CHAPTER 9 TIMER/COUNTER FUNCTION (2/2) Bit position Bit name Function 1, 0 CLR1, CLR0 Controls TM10 clear operation in UDC mode A. CLR1 CLR0 Specifies TM10 clear source Cleared only by external input (TCLR10) Cleared upon match of TM10 count value and CM100 set value Cleared by TCLR10 input or upon match of TM10 count value and CM100 set value...
Page 303 CHAPTER 9 TIMER/COUNTER FUNCTION (5) Signal edge selection register 10 (SESA10) The SESA10 register is used to specify the valid edge of external interrupt requests from external pins (INTP100, INTP101, TIUD10, TCUD10, TCLR10). The valid edge (rising edge, falling edge, or both edges) can be specified independently for each pin. SESA10 can be read/written in 8-bit or 1-bit units.
Page 304 CHAPTER 9 TIMER/COUNTER FUNCTION (2/2) Bit position Bit name Function 5, 4 CESUD01, Specifies valid edge of TCLR10 pin. CESUD00 CESUD01 CESUD00 Valid edge Falling edge Rising edge Low level High level The set values of bits CESUD01 and CESUD00 and the TM10 operation are related as follows.
Page 305 CHAPTER 9 TIMER/COUNTER FUNCTION (6) Prescaler mode register 10 (PRM10) The PRM10 register is used to perform the following selections. • Selection of count clock in general-purpose timer mode (CMD bit of TUM0 register = 0) • Selection of count operation mode in UDC mode (CMD = 1) PRM10 can be read/written in 8-bit or 1-bit units.
Page 306 CHAPTER 9 TIMER/COUNTER FUNCTION (7) Status register 0 (STATUS0) The STATUS0 register indicates the operating status of TM10. STATUS0 is read-only, in 8-bit or 1-bit units. <2> <1> <0> Address After reset STATUS0 TM1UDF0 TM1OVF0 TM1UBD0 FFFFF5EFH Bit position Bit name Function TM1UDF0 TM10 underflow flag...
Page 307 CHAPTER 9 TIMER/COUNTER FUNCTION (9) Compare register 100 (CM100) CM100 is a 16-bit register that always compares its value with the value of TM10. When the value of a compare register matches the value of TM10, an interrupt signal is generated. The interrupt generation timing in the various modes is described below.
Page 308 CHAPTER 9 TIMER/COUNTER FUNCTION (11) Capture/compare register 100 (CC100) CC100 is a 16-bit register. It can be specified as a capture register or as a compare register using capture/compare control register 0 (CCR0). CC100 can be read/written in 16-bit units. Cautions 1.
Page 309 CHAPTER 9 TIMER/COUNTER FUNCTION (12) Capture/compare register 101 (CC101) CC101 is a 16-bit register. It can be specified as a capture register or as a compare register using capture/compare control register 0 (CCR0). CC101 can be read/written in 16-bit units. Cautions 1.
Page 310: Operation
CHAPTER 9 TIMER/COUNTER FUNCTION 9.2.5 Operation (1) Operation in general-purpose timer mode TM10 can perform the following operations in the general-purpose timer mode. (a) Interval operation (when ENMD bit of TMC10 register = 1) TM10 and CM100 always compare their values and the INTCM100 interrupt is generated upon occurrence of a match.
Page 311 CHAPTER 9 TIMER/COUNTER FUNCTION Table 9-7. Capture Trigger Signal (TM10) to 16-Bit Capture Register Capture Register Capture Trigger Signal CC100 INTP100 CC101 INTP100 or INTP101 Remark CC100 and CC101 are capture/compare registers. Which of these registers is used is specified by capture/compare control register 0 (CCR0). The valid edge of the capture trigger is specified by signal edge selection register 10 (SESA10).
Page 312 CHAPTER 9 TIMER/COUNTER FUNCTION (i) Description of operation The CM100 register is a compare register used to set the PWM output cycle. When the value of this register matches the value of TM10, the INTCM100 interrupt is generated. The compare match is saved by hardware, and TM10 is cleared at the next count clock after the match.
Page 313 CHAPTER 9 TIMER/COUNTER FUNCTION (2) Operation in UDC mode (a) Overview of operation in UDC mode The count clock input to TM10 in the UDC mode (CMD bit of TUM0 register = 1) can only be externally input from the TIUD10 and TCUD10 pins. Up/down count judgment in the UDC mode is determined based on the phase difference of the TIUD10 and TCUD10 pin inputs according to the PRM10 register setting (there is a total of four choices).
Page 314 CHAPTER 9 TIMER/COUNTER FUNCTION (b) Up/down count operation in UDC mode TM10 up/down count judgment in the UDC mode is determined based on the phase difference of the TIUD10 and TCUD10 pin inputs according to the PRM10 register setting. (i) Mode 1 (PRM10 register’s PRM12 bit = 1, PRM11 bit = 0, PRM10 bit = 0) In mode 1, the following count operations are performed based on the level of the TCUD10 pin upon detection of the valid edge of the TIUD10 pin.
Page 315 CHAPTER 9 TIMER/COUNTER FUNCTION (ii) Mode 2 (PRM10 register’s PRM12 bit = 1, PRM11 bit = 0, PRM10 bit = 1) The count conditions in mode 2 are as follows. • TM10 up count upon detection of valid edge of TIUD10 pin •...
Page 316 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-55. Mode 3 (When Rising Edge Is Specified as Valid Edge of TIUD10 Pin): In Case of Simultaneous TIUD10, TCUD10 Pin Edge Timing TIUD10 TCUD10 TM10 0007H 0008H 0009H 000AH 0009H 0008H 0007H Up count Down count (iv) Mode 4 (PRM10 register’s PRM12 = 1, PRM11 = 1, PRM10 = 1) In mode 4, when two signals out of phase are input to the TIUD10 and TCUD10 pins, up/down...
Page 317 CHAPTER 9 TIMER/COUNTER FUNCTION (c) Operation in UDC mode A (i) Interval operation The operations at the count clock following a match of the TM10 count value and the CM100 set value are as follows. • In case of up count operation: TM10 is cleared (0000H) and the INTCM100 interrupt is generated. •...
Page 318 CHAPTER 9 TIMER/COUNTER FUNCTION (d) Operation in UDC mode B (i) Basic operation The operations at the next count clock after the count value of TM10 and the CM100 set value match when TM10 is in UDC mode B are as follows. •...
Page 319: Supplementary Description Of Internal Operation
CHAPTER 9 TIMER/COUNTER FUNCTION 9.2.6 Supplementary description of internal operation (1) Clearing of count value in UDC mode B When TM10 is in UDC mode B, the conditions to clear the count value are as follows. • In case of TM10 up-count operation: TM10 count value is cleared upon match with the CM100 register •...
Page 320 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-60. Clear Operation After Match of CM101 Register Set Value and TM10 Count Value (a) Down count → Down count TM10 cleared Count clock (Rising edge set as valid edge) TM10 00FFH 00FEH 0000H FFFFH CM101 register 00FEH Down count...
Page 321 CHAPTER 9 TIMER/COUNTER FUNCTION (3) Interrupt signal output upon compare match An interrupt signal is output when the count value of TM10 matches the set value of the CM100, CM101, Note Note CC100 , or CC101 register. The interrupt generation timing is as follows. Note When CC100 and CC101 are set to the compare register mode.
Page 322: Timer 2
CHAPTER 9 TIMER/COUNTER FUNCTION 9.3 Timer 2 9.3.1 Features (timer 2) Timers 20 and 21 (TM20, TM21) are 16-bit general-purpose timer units that perform the following operations. • Pulse interval or frequency measurement and programmable pulse output • Interval timer •...
Page 323 CHAPTER 9 TIMER/COUNTER FUNCTION • Interrupt request sources • Compare-match interrupt request: 6 types Perform comparison with subchannel n capture/compare register and generate the INTCC2n interrupt upon compare match. • Timer/counter overflow interrupt request: 2 types The INTTM20 (INTTM21) interrupt is generated when the count value of TM20 (TM21) becomes FFFFH. •...
Page 324: Basic Configuration
CHAPTER 9 TIMER/COUNTER FUNCTION 9.3.3 Basic configuration The basic configuration is shown below. Table 9-9. Timer 2 Configuration List Timer Count Clock Register Read/Write Generated Interrupt Capture Trigger Other Signal Functions − − Timer 2 TM20 INTTM20 Note 1 − −...
Page 325 CHAPTER 9 TIMER/COUNTER FUNCTION The following shows the output level sources during timer output. Table 9-11. Output Level Sources During Timer Output TO2n Toggle Mode 0 Toggle Mode 1 Toggle Mode 2 Toggle Mode 3 (OTMEn1, OTMEn0 = 00) (OTMEn1, OTMEn0 = 01) (OTMEn1, OTMEn0 = 10) (OTMEn1, OTMEn0 = 11) Trigger...
Page 326 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-64 shows the block diagram of timer 2. Figure 9-64. Block Diagram of Timer 2 ECLR 1/2, 1/4, 1/8, CNT = MAX. INTTM20 1/16, 1/32, TCOUNTE0 TM20 1/64, 1/128 edge selection CNT = 0 (16-bit) TCOUNTE1 edge selection INTCC20...
Page 327 CHAPTER 9 TIMER/COUNTER FUNCTION Table 9-12. Meaning of Signals in Block Diagram Signal Name Meaning Note 1 CASC TM21 count signal input in 32-bit mode Count value of timer 2 (CNT = MAX.: Maximum value count signal output of timer 2 (generated when TM2n = FFFFH), CNT = 0: Zero count signal output of timer 2 (generated when TM2n = 0000H)) TM2n count signal input in 16-bit mode...
Page 328 CHAPTER 9 TIMER/COUNTER FUNCTION (1) Timers 20, 21 (TM20, TM21) The features of TM2n are listed below. • Free-running counter that enables counter clearing by compare match of subchannel 0 and subchannel 5 • Can be used as a 32-bit capture timer when TM20 and TM21 are connected in cascade. •...
Page 329 CHAPTER 9 TIMER/COUNTER FUNCTION (4) Timer 2 subchannel n sub capture/compare register (CVSEn0) (n = 1 to 4) The CVSEn0 register is the subchannel n 16-bit sub capture/compare register. In the compare register mode, this register can be used as a buffer. In the capture register mode, this register captures the value of TM20 when the BFEEn bit of the CMSEm0 register = 0 (m = 12, 34).
Page 330: Control Registers
CHAPTER 9 TIMER/COUNTER FUNCTION 9.3.4 Control registers (1) Timer 1/timer 2 clock selection register (PRM02) The PRM02 register is used to select the base clock (f ) of timer 1 and timer 2. This register can be read/written in 8-bit or 1-bit units. Cautions 1.
Page 331 CHAPTER 9 TIMER/COUNTER FUNCTION (3) Timer 2 count clock/control edge selection register 0 (CSE0) The CSE0 register is used to specify the TM2n count clock and the control valid edge (n = 0, 1). This register can be read/written in 16-bit units. When the higher 8 bits of the CSE0 register are used as the CSE0H register, and the lower 8 bits are used as the CSE0L register, they can be read/written in 8-bit or 1-bit units.
Page 332 CHAPTER 9 TIMER/COUNTER FUNCTION (4) Timer 2 subchannel input event edge selection register 0 (SESE0) The SESE0 register specifies the valid edge of the external capture signal input (TINEn) for the subchannel n capture/compare register performing capture (n = 0 to 5). This register can be read/written in 16-bit units.
Page 333 CHAPTER 9 TIMER/COUNTER FUNCTION (5) Timer 2 time base control register 0 (TCRE0) The TCRE0 register controls the operation of TM2n (n = 0, 1). This register can be read/written in 16-bit units. When the higher 8 bits of the TCRE0 register are used as the TCRE0H register, and the lower 8 bits are used as the TCRE0L register, they can be read/written in 8-bit or 1-bit units.
Page 334 CHAPTER 9 TIMER/COUNTER FUNCTION (1/2) <14> <13> <6> <5> Address After reset TCRE0 CASE1 CLRE1 CEE1 ECRE1 ECEE1 OSTE1 UDSE11 UDSE10 CLRE0 CEE0 ECRE0 ECEE0 OSTE0 UDSE01 UDSE00 FFFFF646H 0000H Bit position Bit name Function CASE1 Specifies 32-bit cascade operation mode for TM21 (TM21 counts upon overflow of TM20 (carry count)).
Page 335 CHAPTER 9 TIMER/COUNTER FUNCTION (2/2) Bit position Bit name Function 11, 3 ECEEn Specifies TM2n count operation enable/disable through ECLR signal input. 0: TM2n count operation not enabled 1: TM2n count operation enabled Cautions 1. In the 32-bit cascade operation mode (CASE1 = 1), the TM2n count operation using ECLR signal input is not performed.
Page 336 CHAPTER 9 TIMER/COUNTER FUNCTION (6) Timer 2 output control register 0 (OCTLE0) The OCTLE0 register controls timer output from the TO2n pin (n = 1 to 4). This register can be read/written in 16-bit units. When the higher 8 bits of the OCTLE0 register are used as a OCTLE0H register, and the lower 8 bits are used as a OCTLE0L register, they can be read/written in 8-bit or 1-bit units.
Page 337 CHAPTER 9 TIMER/COUNTER FUNCTION (a) Caution for PWM output change timing If the SWFEn bit is changed from 1 to 0 when the timer is operating while the internal PWM output operation is being performed, then the output level becomes active. After that, PWM output from the TO2n pin is performed upon a compare match at subchannel n.
Page 338 CHAPTER 9 TIMER/COUNTER FUNCTION (7) Timer 2 subchannel 0, 5 capture/compare control register (CMSE050) The CMSE050 register controls the timer 2 subchannel 0 capture/compare register (CVSE00) and the timer 2 subchannel 5 capture/compare register (CVSE50). This register can be read/written in 16-bit units. Address After reset CMSE050...
Page 339 CHAPTER 9 TIMER/COUNTER FUNCTION (8) Timer 2 subchannel 1, 2 capture/compare control register (CMSE120) The CMSE120 register controls the timer 2 subchannel n sub capture/compare register (CVSEn0) and the timer 2 subchannel n main capture/compare register (CVPEn0) (n = 1, 2). This register can be read/written in 16-bit units.
Page 340 CHAPTER 9 TIMER/COUNTER FUNCTION (2/2) Bit position Bit name Function 11, 3 LNKEn Selects capture event signal input from edge selection and specifies transfer operation in compare register mode. 0: ED1 signal input selected in capture register mode. In the compare register mode, the data of the CVSEn0 register is transferred to the CVPEn0 register upon occurrence of a TM2x compare match (TM2x = timer/counter selected by bits TB1En, TB0En).
Page 341 CHAPTER 9 TIMER/COUNTER FUNCTION (9) Timer 2 subchannel 3, 4 capture/compare control register (CMSE340) The CMSE340 register controls the timer 2 subchannel n sub capture/compare register (CVSEn0) and the timer 2 subchannel n main capture/compare register (CVPEn0). This register can be read/written in 16-bit units. (1/2) Address After reset...
Page 342 CHAPTER 9 TIMER/COUNTER FUNCTION (2/2) Bit position Bit name Function 11, 3 LNKEn Selects capture event signal input from edge selection and specifies transfer operation in compare register mode. 0: ED1 signal input selected in capture register mode. In the compare register mode, the data of the CVSEn0 register is transferred to the CVPEn0 register upon occurrence of a TM2x compare match (TM2x = timer/ counter selected with bits TB1En, TB0En).
Page 343 CHAPTER 9 TIMER/COUNTER FUNCTION (10) Timer 2 time base status register 0 (TBSTATE0) The TBSTATE0 register indicates the status of TM2n (n = 0, 1). This register can be read/written in 16-bit units. When the higher 8 bits of the TBSTATE0 register are used as the TBSTATE0H register, and the lower 8 bits are used as the TBSTATE0L register, they can be read/written in 8-bit or 1-bit units.
Page 344 CHAPTER 9 TIMER/COUNTER FUNCTION (11) Timer 2 capture/compare 1 to 4 status register 0 (CCSTATE0) The CCSTATE0 register indicates the status of the timer 2 subchannel sub capture/compare register (CVSEn0) and the timer 2 subchannel main capture/compare register (CVPEn0) (n = 1 to 4). This register can be read/written in 16-bit units.
Page 345 CHAPTER 9 TIMER/COUNTER FUNCTION (12) Timer 2 output delay register 0 (ODELE0) The ODELE0 register sets the output delay operation synchronized with the clock to the TO2n pin’s output delay circuit (n = 1 to 4). This register can be read/written in 16-bit units. When the higher 8 bits of the ODELE0 register are used as the ODELE0H register, and the lower 8 bits are used as the ODELE0L register, they can be read/written in 8-bit or 1-bit units.
Page 346 CHAPTER 9 TIMER/COUNTER FUNCTION (13) Timer 2 software event capture register (CSCE0) The CSCE0 register sets capture operation by software in the capture register mode. This register can be read/written in 16-bit units. Address After reset CSCE0 SEVE5 SEVE4 SEVE3 SEVE2 SEVE1 SEVE0...
Page 347: Operation
CHAPTER 9 TIMER/COUNTER FUNCTION 9.3.5 Operation (1) Edge detection The edge detection timing is shown below. Figure 9-66. Edge Detection Timing Note TINEx, TCLR2, TCOUNTEn MUXTB0 ED1, ED2 ECLR Note The set values of the TESnE1 and TESnE0 bits and the CESE1 and CESE0 bits of the CSE0 register, and the IESEx1 and IESEx0 bits of the SESE0 register are shown.
Page 348 CHAPTER 9 TIMER/COUNTER FUNCTION (2) Basic operation of timer 2 Figures 9-67 to 9-70 show the basic operation of timer 2. Figure 9-67. Timer 2 Up Count Timing (When TCRE0 Register’s UDSEn1, UDSEn0 Bits = 00B, ECEEn Bit = 0, ECREn Bit = 0, CLREn Bit = 0, CASE1 Bit = 0) Note 1 OSTEn bit Note 1...
Page 349 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-68. External Control Timing of Timer 2 (When TCRE0 Register’s UDSEn1, UDSEn0 Bits = 00B, OSTEn Bit = 0, CEEn Bit = 1, CASE1 Bit = 0) Note ECEEn bit Note ECREn bit Note CLREn bit ECLR 1234H 1235H...
Page 350 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-69. Operation in Timer 2 Up/Down Count Mode (When TCRE0 Register’s ECEEn bit = 0, ECREn Bit = 0, CLREn Bit = 0, OSTEn Bit = 0, CEEn Bit = 1, CASE1 Bit = 0) Note 1 UDSEn1, UDSEn0 bits Don't care...
Page 351 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-70. Timing in 32-Bit Cascade Operation Mode (When TCRE0 Register’s UDSEn1, UDSEn0 Bits = 00B, ECEEn Bit = 0, ECREn Bit = 0, CLREn Bit = 0, OSTEn Bit = 0, CEEn Bit = 1, CASE1 Bit = 1) Note CASC [TB1]...
Page 352 CHAPTER 9 TIMER/COUNTER FUNCTION (3) Operation of capture/compare register (subchannels 1 to 4) Subchannels 1 to 4 receive the count value of the timer 2 multiplex count generator. The multiplex count generator is an internal unit of TM2n that supplies the multiplex count value MUXCNT to subchannels 1 to 4.
Page 353 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-72. Multiplex Count Timing CNT (0) FFFEH FFFFH 0000H 0001H 1234H 1235H CNT (1) MUXTB0 MUXTB1 MUXCNT FFFEH 1234H FFFFH 1234H FFFFH 1234H FFFFH 1234H 0000H 1235H 0000H 1235H 0000H 1235H 0001H 1235H 0001H 1235H 0001H Remarks 1.
Page 354 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-73. Capture Operation: 16-Bit Buffer-Less Mode (When Operation Is Delayed Through Setting of LNKEy Bit of CMSEx0 Register, and CMSEx0 Register’s CCSEy Bit = 0, BFEEy Bit = 0, EEVEy Bit = 1, and CSCE0 Register’s SEVEy Bit = 0) MUXTB0 MUXTB1 MUXCNT...
Page 355 CHAPTER 9 TIMER/COUNTER FUNCTION Note 1 Figure 9-74. Capture Operation: Mode with 16-Bit Buffer (When CMSEx0 Register’s TByE1 Bit = 0, TByE0 Bit = 1, CCSEy Bit = 0, LNKEy Bit = 0, BFEEy Bit = 1, EEVEy Bit = 1, and CSCE0 Register’s SEVEy Bit = 0) MUXTB0 MUXTB1...
Page 356 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-75. Capture Operation: 32-Bit Cascade Operation Mode (When CMSEx Register’s TByE1 Bit = 1, TByE0 Bit = 1, CCSEy Bit = 0, LNKEy Bit = 0, BFEEy Bit = Arbitrary, EEVEy Bit = 1, and CSCE0 Register’s SEVEy Bit = 0) TCOUNTE0 = TCOUNTE1 CNT (0)
Page 357 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-76. Capture Operation: Capture Control by Software and Trigger Timing (When CMSEx0 Register’s TByE1 Bit = 0, TByE0 Bit = 1, CCSEy Bit = 0, LNKEy Bit = 0, BFEEy Bit = 1) MUXTB0 MUXTB1 MUXCNT Note 1 EEVEy bit...
Page 358 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-77. Compare Operation: Buffer-Less Mode (When CMSEx0 Register’s CCSEy Bit = 1, LNKEy Bit = Arbitrary, BFEEy Bit = 0) MUXTB0 MUXTB1 MUXCNT Note 1 TB0Ey bit Note 1 TB1Ey bit WRITE_ENABLE_S RELOAD_PRIMARY CVSEm0 register CVPEm0 register RELOAD1 Note 2...
Page 359 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-78. Compare Operation: Mode with Buffer (When Operation Is Delayed Through Setting of LNKEy Bit of CMSEx0 Register, CMSEx0 Register’s CCSEy Bit = 1, BFEEy Bit = 1) MUXTB0 MUXTB1 MUXCNT Note LNKEy bit WRITE_ENABLE_S RELOAD2A RELOAD1 RELOAD_PRIMARY...
Page 360 CHAPTER 9 TIMER/COUNTER FUNCTION (4) Operation of capture/compare register (subchannels 0, 5) Figures 9-79 and 9-80 show the operation of the capture/compare register (subchannels 0, 5). Figure 9-79. Capture Operation: Timer 2 Count Value Read Timing (When CMSE050 Register’s CCSEy Bit = 0, EEVEy Bit = 1, and CSCE0 Register’s SEVEy Bit = 0) Note 1 LNKEy Note 2...
Page 361 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-80. Compare Operation: Timing of Compare Match and Write Operation to Register (When CMSE050 Register’s CCSEy Bit = 1, EEVEy Bit = Arbitrary, and CSCE0 Register’s SEVEy Bit = Arbitrary) CPU write C/C CVSEy0 register MATCH Note 1 Note 2...
Page 362 CHAPTER 9 TIMER/COUNTER FUNCTION (5) Operation of output circuit Figures 9-81 to 9-84 show the output circuit operation. Figure 9-81. Signal Output Operation: Toggle Mode 0 and Toggle Mode 1 (When OCTLE0 Register’s SWFEn Bit = 0, and ODELE0 Register’s ODLEn2 to ODLEn0 Bits = 0) Note 1 OTMEn1, OTMEn0 bits TO2n timer output...
Page 363 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-82. Signal Output Operation: Toggle Mode 2 and Toggle Mode 3 (When OCTLE0 Register’s SWFEn Bit = 0, and ODELE0 Register’s ODLEn2 to ODLEn0 Bits = 0) Note 1 OTMEn1, OTMEn0 bits TO2n timer output Note 2 (ALVEn bit = 0 TO2n timer output...
Page 364 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-84. Signal Output Operation: During Delay Output Operation (When OCTLE0 Register’s OTMEn1, OTMEn0 Bits = 0, ALVEn = 0, SWFEn Bit = 0) Note ODELEn2 to ODELEn0 bits TO2n timer output Note ODELEn2 to ODELEn0 bits of OCTLE0 register Remarks 1.
Page 365: Pwm Output Operation In Timer 2 Compare Mode
CHAPTER 9 TIMER/COUNTER FUNCTION 9.3.6 PWM output operation in timer 2 compare mode (1) Operation during PWM output operation of TO2n pin in toggle mode 1 In toggle mode 1, the output of TO2n (internal) is made inactive at the trigger signal when TM20 = 0, and the output of TO2n (internal) is made active triggered by a compare match signal with subchannel 1 (the CVSEn0 register).
Page 366 CHAPTER 9 TIMER/COUNTER FUNCTION (2) Operations when output of the TO2n pin is controlled by manipulating the OCTLE0.SWFEn bit in toggle mode 1 (a) When compare match signal of subchannel n is output immediately after the SWFEn bit changes from 1 to 0 Figures 9-86 and 9-87 show the waveform of each block at output start/end when the output of the TO2n output pin is controlled by manipulating the SWFEn bit in toggle mode 1.
Page 367 CHAPTER 9 TIMER/COUNTER FUNCTION (b) When the trigger signal of TM20 = 0 is output immediately after the SWFEn bit is changed from 1 to 0 When the trigger signal of TM20 = 0 is output immediately after the SWFEn bit is changed from 1 to 0, the initial active period is from when the SWFEn bit is changed from 1 to 0 until the trigger signal of TM20 is output.
Page 368: Timer 3
CHAPTER 9 TIMER/COUNTER FUNCTION 9.4 Timer 3 9.4.1 Features (timer 3) Timer 3 (TM3) is a 16-bit timer/counter that can perform the following operations. • Interval timer function • PWM output • External signal cycle measurement • TO3 output buffer set to off by INTP4 input 9.4.2 Function overview (timer 3) •...
Page 369: Function Added To V850E/Ia2
CHAPTER 9 TIMER/COUNTER FUNCTION 9.4.3 Function added to V850E/IA2 Timer 3 (TM3) of the V850E/IA2 has an added function to control TO3 output by using the INTP4 pin. This additional function can be used to forcibly stop TO3 output, if any abnormality is detected, by inputting a signal to the INTP4 pin.
Page 370 CHAPTER 9 TIMER/COUNTER FUNCTION (1) Timer 3 (TM3) TM3 functions as a 16-bit free-running timer or as an event counter for an external signal. Besides being mainly used for cycle measurement, TM3 can be used as pulse output. TM3 is read-only, in 16-bit units. Cautions 1.
Page 371 CHAPTER 9 TIMER/COUNTER FUNCTION (2) Capture/compare registers 30 and 31 (CC30 and CC31) These capture/compare registers 30 and 31 are 16-bit registers. They can be used as capture registers or compare registers according to the CMS1 and CMS0 bit specifications of timer control register 31 (TMC31). These registers can be read/written in 16-bit units (however, write operations can only be performed in compare mode).
Page 372 CHAPTER 9 TIMER/COUNTER FUNCTION (b) Setting these registers to compare registers (CMS1 and CMS0 of TMC31 = 1) When these registers are set to compare registers, the TM3 and register values are compared for each count clock, and an interrupt is generated by a match. If the CCLR bit of timer control register 31 (TMC31) is set (1), the TM3 value is cleared (0) at the same time as a match with the CC30 register (it is not cleared (0) by a match with the CC31 register).
Page 373: Control Registers
CHAPTER 9 TIMER/COUNTER FUNCTION 9.4.5 Control registers (1) Timer 3 clock selection register (PRM03) The PRM03 register is used to select the base clock (f ) of timer 3 (TM3). This register can be read/written in 8-bit or 1-bit units. Cautions 1.
Page 374 CHAPTER 9 TIMER/COUNTER FUNCTION (2) Timer control register 30 (TMC30) The TMC30 register controls the operation of TM3. This register can be read/written in 8-bit or 1-bit units. Cautions 1. The TM3CAE bit and other bits cannot be set at the same time. Be sure to set the TM3CAE bit and then set the other bits and the other registers of TM3.
Page 375 CHAPTER 9 TIMER/COUNTER FUNCTION (2/2) Bit position Bit name Function 6 to 4 CS2 to CS0 Selects the internal count clock for TM3. Count clock /128 /256 Caution Do not change the CS2 to CS0 bits during timer operation. If they are to be changed, they must be changed after setting the TM3CE bit to 0.
Page 376 CHAPTER 9 TIMER/COUNTER FUNCTION (3) Timer control register 31 (TMC31) The TMC31 register controls the operation of TM3. This register can be read/written in 8-bit or 1-bit units. Cautions 1. Do not change the bits of the TMC31 register during timer operation. If they are to be changed, they must be changed after setting the TM3CE bit of the TMC30 register to 0.
Page 377 CHAPTER 9 TIMER/COUNTER FUNCTION Address After reset TMC31 ENT1 CCLR ECLR CMS1 CMS0 FFFFF688H Bit position Bit name Function Sets the operation when TM3 overflows. 0: Count operation continues after overflow (free-running mode) 1: After overflow, timer holds 0000H and stops count operation (overflow stop mode).
Page 378 CHAPTER 9 TIMER/COUNTER FUNCTION (4) Valid edge selection register (SESC) This register specifies the valid edge of external interrupt requests (TI3, TCLR3, INTP30, INTP31) from an external pin. The rising edge, the falling edge, or both rising and falling edges can be specified as the valid edge independently for each pin.
Page 379 CHAPTER 9 TIMER/COUNTER FUNCTION (5) Timer 3 output control register (TO3C) TO3C is a register that controls output of the TO3 pin. This register can be read/written in 8-bit or 1-bit units. Caution The TO3 output stop status can be canceled by writing 0 to the TO3SP bit of this register. <0>...
Page 380: Operation
CHAPTER 9 TIMER/COUNTER FUNCTION 9.4.6 Operation (1) Count operation Timer 3 can function as a 16-bit free-running timer or as an external signal event counter. The setting for the type of operation is specified by timer control register 3n (TMC3n) (n = 0, 1). When it operates as a free-running timer, if the CC30 or CC31 register and the TM3 count value match, an interrupt signal is generated and the timer output signal (TO3) can be set or reset.
Page 381 CHAPTER 9 TIMER/COUNTER FUNCTION (2) Overflow When the TM3 register has counted the count clock from FFFFH to 0000H, the TM3OVF bit of the TMC30 register is set (1), and an overflow interrupt (INTTM3) is generated at the same time. However, if the CC30 register is set to compare mode (CMS0 bit = 1) and to the value FFFFH when match clearing is enabled (CCLR bit = 1), then the TM3 register is considered to be cleared and the TM3OVF bit is not set (1) when the TM3 register changes from FFFFH to 0000H.
Page 382 CHAPTER 9 TIMER/COUNTER FUNCTION (3) Capture operation The TM3 register has two capture/compare registers. These are the CC30 register and the CC31 register. A capture operation or a compare operation is performed according to the settings of both the CMS1 and CMS0 bits of the TMC31 register.
Page 383 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-92. TM3 Capture Operation Example (When Both Edges Are Specified) (TM3 count values) ∆ ∆ Count start Overflow TM3CE ← 1 TM3OVF ← 1 Interrupt request (INTP31) Capture register (CC31) Remark D0 to D2: TM3 count values User’s Manual U15195EJ5V0UD...
Page 384 CHAPTER 9 TIMER/COUNTER FUNCTION (4) Compare operation The TM3 register has two capture/compare registers. These are the CC30 register and the CC31 register. A capture operation or a compare operation is performed according to the settings of both the CMS1 and CMS0 bits of the TMC31 register.
Page 385 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-93. Compare Operation Example (2/2) (b) If CCLR bit = 1 and CC30 register is 0000H Count up FFFFH 0000H 0000H 0001H Compare register 0000H (CC30) INTTM3 (output) Match detection (INTCC30) Remark The match is detected immediately after the count up, and the match detection signal is generated.
Page 386 CHAPTER 9 TIMER/COUNTER FUNCTION (5) External pulse output Timer 3 has one timer output pin (TO3). An external pulse output (TO3) is generated when a match of the two compare registers (CC30 and CC31) and the TM3 register is detected. If a match is detected when the TM3 count value and the CC30 value are compared, the output level of the TO3 pin is set.
Page 387 CHAPTER 9 TIMER/COUNTER FUNCTION (6) TO3 output control function by INTP4 pin Output of the TO3 pin can be forcibly stopped by inputting a signal to the INTP4 pin if an abnormality is detected in the power system of a motor. If the TO3 output mode is set (PMC27 = 1 and PFC27 = 1) and if the specified valid edge is generated on the INTP4 pin after the TO3SP bit of the timer 3 output control register (TO3C) has been set to 1, the output buffer of the TO3 pin can be turned off (the TO3 pin goes into a high-impedance state).
Page 388: Application Examples
CHAPTER 9 TIMER/COUNTER FUNCTION 9.4.7 Application examples (1) Interval timer By setting the TMC30 and TMC31 registers as shown in Figure 9-96, timer 3 operates as an interval timer that repeatedly generates interrupt requests with the value that was set in advance in the CC30 register as the interval.
Page 389 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-97. Interval Timer Operation Timing Example Count clock 0000H 0001H 0000H 0001H 0000H 0001H register Count start Clear Clear CC30 register INTCC30 interrupt Interval time Interval time Interval time Remark p: Setting value of CC30 register (0000H to FFFFH) Count clock cycle Interval time = (p + 1) ×...
Page 390 CHAPTER 9 TIMER/COUNTER FUNCTION (2) PWM output By setting the TMC30 and TMC31 registers as shown in Figure 9-98, timer 3 can output a PWM of the frequency determined by the setting of the CS2 to CS0 bits of the TMC30 register with the values that were set in advance in the CC30 and CC31 registers as the intervals.
Page 391 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-99. PWM Output Operation Timing Example Count clock TM3 register 0000H 0001H FFFFH 0000H 0001H Count start Clear CC30 register CC31 register INTCC30 interrupt INTCC31 interrupt (output) Remarks 1. p: Setting value of CC30 register (0000H to FFFFH) q: Setting value of CC31 register (0000H to FFFFH) p ≠...
Page 392 CHAPTER 9 TIMER/COUNTER FUNCTION (3) Cycle measurement By setting the TMC30 and TMC31 registers as shown in Figure 9-100, timer 3 can measure the cycle of signals input to the INTP30 pin or INTP31 pin. The valid edge of the INTP30 pin is selected according to the IES301 and IES300 bits of the SESC register, and the valid edge of the INTP31 pin is selected according to the IES311 and IES310 bits of the SESC register.
Page 393 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-101. Cycle Measurement Operation Timing Example Count clock 0000H 0001H FFFFH 0000H 0001H register Count start Clear INTP30 (input) CC30 register INTCC30 interrupt INTTM3 interrupt (D1 − D0) × t {(10000H − D1) + D2} × t Note (D3 −...
Page 394: Cautions
CHAPTER 9 TIMER/COUNTER FUNCTION 9.4.8 Cautions Various cautions concerning timer 3 are shown below. (1) If a conflict occurs between the reading of the CC30 register and a capture operation when the CC30 register is used in capture mode, an external trigger (INTP30) valid edge is detected and an external interrupt request signal (INTCC30) is generated, but the timer value is not stored in the CC30 register.
Page 395: Timer 4
CHAPTER 9 TIMER/COUNTER FUNCTION 9.5 Timer 4 9.5.1 Features (timer 4) Timer 4 (TM4) functions as a 16-bit interval timer. 9.5.2 Function overview (timer 4) • 16-bit interval timer: 1 channel • Compare register: 1 • Count clock selected from divisions of internal system clock (set the frequency of the count clock to 16 MHz or less) •...
Page 396: Basic Configuration
CHAPTER 9 TIMER/COUNTER FUNCTION 9.5.3 Basic configuration Table 9-16. Timer 4 Configuration List Timer Count Clock Register Read/Write Generated Capture Timer Other Interrupt Trigger Output S/R Functions Signal − − − − Timer 4 /4, f /8, f /16, f /32, Read /64, f...
Page 397 CHAPTER 9 TIMER/COUNTER FUNCTION (1) Timer 4 (TM4) TM4 is a 16-bit timer. It is mainly used as an interval timer for software. Starting and stopping TM4 is controlled by the TM4CE0 bit of timer control register 4 (TMC4). Division by the prescaler can be selected for the count clock from among f /4, f /8, f /16, f...
Page 398 CHAPTER 9 TIMER/COUNTER FUNCTION (2) Compare register 4 (CM4) CM4 and the TM4 register count value are compared, and an interrupt request signal (INTCM4) is generated when a match occurs. TM4 is cleared, synchronized with this match. If the TM4CAE0 bit of the TMC4 register is set to 0, a reset is performed asynchronously, and the registers are initialized.
Page 399 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-103. Example of Timing During TM4 Operation (a) When TM4 < CM4 TM4CAE0 TM4CE0 INTCM4 Remark M = TM4 value when overwritten N = CM4 value after overwrite M < N (b) When TM4 > CM4 FFFFH TM4CAE0 TM4CE0...
Page 400: Control Register
CHAPTER 9 TIMER/COUNTER FUNCTION 9.5.4 Control register (1) Timer control register 4 (TMC4) The TMC4 register controls the operation of timer 4. This register can be read/written in 8-bit or 1-bit units. Caution The TM4CAE0 bit and other bits cannot be set at the same time. Be sure to set the TM4CAE0 bit and then set the other bits and the other registers of TM4.
Page 401: Operation
CHAPTER 9 TIMER/COUNTER FUNCTION 9.5.5 Operation (1) Compare operation TM4 can be used for a compare operation in which the value that was set in the compare register (CM4) is compared with the TM4 count value. If a match is detected by the compare operation, an interrupt (INTCM4) is generated. The generation of the interrupt causes TM4 to be cleared (0) at the next count timing.
Page 402 CHAPTER 9 TIMER/COUNTER FUNCTION Figure 9-104. TM4 Compare Operation Example (2/2) (b) When CM4 is set to 0 Count clock Count up TM4 clear Clear FFFFH Match detection (INTCM4) Overflow Interval time = (FFFFH + 2) × Count clock cycle Remark User’s Manual U15195EJ5V0UD...
Page 403: Application Example
CHAPTER 9 TIMER/COUNTER FUNCTION 9.5.6 Application example (1) Interval timer This section explains an example in which timer 4 is used as an interval timer with 16-bit precision. Interrupt requests (INTCM4) are output at equal intervals (refer to Figure 9-104 TM4 Compare Operation Example).
Page 404: Timer Connection Function
CHAPTER 9 TIMER/COUNTER FUNCTION 9.6 Timer Connection Function 9.6.1 Overview The V850E/IA2 provides a function to connect timer 1 and timer 2. Figure 9-105. Block Diagram of Timer Connection Function Timer connection selector Timer 2 Capture 0 CVSE10/ CVPE10 Capture 1 CVSE20/ CVPE20 Timer 1...
Page 405: Control Register
CHAPTER 9 TIMER/COUNTER FUNCTION 9.6.2 Control register (1) Timer connection selection register 0 (TMIC0) The TMIC0 register enables/disables input of the INTCM100 and INTCM101 signals to the CVSEn0/CVPEn0 registers (n = 1, 2). This register can be read/written in 8-bit or 1-bit units. Address After reset TMIC0...
Page 406: Chapter 10 Serial Interface Function
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.1 Features The serial interface function provides two types of serial interfaces combining a total of four transmit/receive channels. Three of these channels can be used simultaneously. The two interface formats are as follows. (1) Asynchronous serial interfaces (UART0, UART1): 2 channels (2) Clocked serial interfaces (CSI0, CSI1): 2 channels UART0, UART1, in which one byte of serial data is transmitted/received following a start bit, support full-duplex communication.
Page 407: Selecting Uart1 Or Csi1 Mode
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.1.1 Selecting UART1 or CSI1 mode UART1 and CSI1 of the V850E/IA2 share pins, and therefore these interfaces cannot be used at the same time. Select UART1 or CSI1 in advance by using the port 3 mode control register (PMC3) and port 3 function control register (PFC3) (refer to 12.3.4 Port 3).
Page 408: Asynchronous Serial Interface 0 (Uart0)
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.2 Asynchronous Serial Interface 0 (UART0) 10.2.1 Features • Transfer rate: 300 bps to 1,250 kbps (using a dedicated baud rate generator and an internal system clock of 40 MHz) • Full-duplex communications On-chip receive buffer register 0 (RXB0) On-chip transmit buffer register 0 (TXB0) •...
Page 409: Configuration
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.2.2 Configuration UART0 is controlled by asynchronous serial interface mode register 0 (ASIM0), asynchronous serial interface status register 0 (ASIS0), and asynchronous serial interface transmission status register 0 (ASIF0). Receive data is maintained in receive buffer register 0 (RXB0), and transmit data is written to transmit buffer register 0 (TXB0). Figure 10-2 shows the configuration of asynchronous serial interface 0 (UART0).
Page 410 CHAPTER 10 SERIAL INTERFACE FUNCTION (8) Transmit buffer register 0 (TXB0) TXB0 is an 8-bit buffer for transmit data. A transmit operation is started by writing transmit data to TXB0. (9) Addition of transmission control parity A transmit operation is controlled by adding a start bit, parity bit, or stop bit to the data that is written to the TXB0 register, according to the contents that were set in the ASIM0 register.
Page 411: Control Registers
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.2.3 Control registers (1) Asynchronous serial interface mode register 0 (ASIM0) The ASIM0 register is an 8-bit register that controls the UART0 transfer operation. This register can be read/written in 8-bit or 1-bit units. Cautions 1. When using UART0, be sure to set the external pins related to UART0 functions to the control made before setting clock select register 0 (CKSR0) and the baud rate generator control register (BRGC0), and then set the UARTCAE0 bit to 1.
Page 412 CHAPTER 10 SERIAL INTERFACE FUNCTION (2/3) Bit position Bit name Function RXE0 Enables/disables reception. Note 0: Disables reception 1: Enables reception Cautions 1. Set the RXE0 bit to 1 after setting the UARTCAE0 bit to 1 at startup. Set the UARTCAE0 bit to 0 after setting the RXE0 bit to 0 to stop.
Page 413 CHAPTER 10 SERIAL INTERFACE FUNCTION (3/3) Bit position Bit name Function • 0 parity 4, 3 PS1, PS0 During transmission, the parity bit is cleared (0) regardless of the transmit data. During reception, no parity error is generated because no parity bit is checked. •...
Page 414 CHAPTER 10 SERIAL INTERFACE FUNCTION (2) Asynchronous serial interface status register 0 (ASIS0) The ASIS0 register, which consists of 3-bit error flags (PE, FE and OVE), indicates the error status when UART0 reception is complete. The ASIS0 register is cleared to 00H by a read operation. When a reception error occurs, receive buffer register 0 (RXB0) should be read and the error flag should be cleared after the ASIS0 register is read.
Page 415 CHAPTER 10 SERIAL INTERFACE FUNCTION (3) Asynchronous serial interface transmission status register 0 (ASIF0) The ASIF0 register, which consists of 2-bit status flags, indicates the status during transmission. By writing the next data to the TXB0 register after data is transferred from the TXB0 register to the transmit shift register, transmit operations can be performed continuously without suspension even during an interrupt interval.
Page 416 CHAPTER 10 SERIAL INTERFACE FUNCTION (4) Receive buffer register (RXB0) The RXB0 register is an 8-bit buffer register for storing parallel data that had been converted by the receive shift register. When reception is enabled (RXE0 bit = 1 in the ASIM0 register), receive data is transferred from the receive shift register to the RXB0 register, synchronized with the completion of the shift-in processing of one frame.
Page 417 CHAPTER 10 SERIAL INTERFACE FUNCTION (5) Transmit buffer register 0 (TXB0) The TXB0 register is an 8-bit buffer register for setting transmit data. When transmission is enabled (TXE0 bit = 1 in the ASIM0 register), the transmit operation is started by writing data to TXB0 register.
Page 418: Interrupt Requests
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.2.4 Interrupt requests The following three types of interrupt requests are generated from UART0. • Reception completion interrupt (INTSR0) • Transmission completion interrupt (INTST0) • Reception error interrupt (INTSER0) The default priorities among these three types of interrupt requests is, from high to low, reception completion interrupt, transmission completion interrupt, and reception error interrupt.
Page 419: Operation
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.2.5 Operation (1) Data format Full-duplex serial data transmission and reception can be performed. The transmit/receive data format consists of one data frame containing a start bit, character bits, a parity bit, and stop bits as shown in Figure 10-3. The character bit length within one data frame, the type of parity, and the stop bit length are specified according to asynchronous serial interface mode register 0 (ASIM0).
Page 420 CHAPTER 10 SERIAL INTERFACE FUNCTION (2) Transmit operation When the UARTCAE0 bit is set to 1 in the ASIM0 register, a high level is output from the TXD0 pin. Then, when the TXE0 bit is set to 1 in the ASIM0 register, transmission is enabled, and the transmit operation is started by writing transmit data to transmit buffer register 0 (TXB0).
Page 421 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-4. Asynchronous Serial Interface Transmission Completion Interrupt Timing (a) Stop bit length: 1 Start TXD0 (output) Parity Stop INTST0 (output) (b) Stop bit length: 2 Stop Parity TXD0 (output) Start INTST0 (output) User’s Manual U15195EJ5V0UD...
Page 422 CHAPTER 10 SERIAL INTERFACE FUNCTION (3) Continuous transmission operation UART0 can write the next transmit data to the TXB0 register at the timing that the transmit shift register starts the shift operation. This enables an efficient transmission rate to be realized by continuously transmitting data even during the servicing of the transmission completion interrupt (INTST0) after the transmission of one data frame.
Page 423 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-5. Continuous Transmission Processing Flow Set registers Write the first byte of the transmit data to TXB0 register When reading ASIF0 register, TXBF0 = 0? Write the second byte of the transmit data to the Interrupt occurrence TXB0 register.
Page 424 CHAPTER 10 SERIAL INTERFACE FUNCTION (a) Starting procedure The procedure to start continuous transmission is shown below. Figure 10-6. Continuous Transmission Starting Procedure Start Start Stop Stop TXD0 (output) Data (1) Data (2) <1> <2> <3> <4> <5> INTST0 (output) TXB0 register Data (1) Data (2)
Page 425 CHAPTER 10 SERIAL INTERFACE FUNCTION (b) Ending procedure The procedure for ending continuous transmission is shown below. Figure 10-7. Continuous Transmission End Procedure Start Start Stop Stop TXD0 (output) Data (m − 1) Data (m) <6> <7> <8> <9> <10> <11>...
Page 426 CHAPTER 10 SERIAL INTERFACE FUNCTION (4) Receive operation The awaiting reception state is set by setting the UARTCAE0 bit to 1 in the ASIM0 register and then setting the RXE0 bit to 1 in the ASIM0 register. To start reception, start sampling at the falling edge of the RXD0 pin upon detection of the falling edge.
Page 427 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-8. Asynchronous Serial Interface Reception Completion Interrupt Timing Start RXD0 (input) Parity Stop INTSR0 (output) RXB0 register Cautions 1. Be sure to read receive buffer register 0 (RXB0) even when a reception error occurs. If the RXB0 register is not read, an overrun error will occur at the next data reception and the reception error status will continue infinitely.
Page 428 CHAPTER 10 SERIAL INTERFACE FUNCTION (a) Separation of reception error interrupt A reception error interrupt can be separated from the INTSR0 signal and generated as the INTSER0 signal by clearing the ISRM bit of the ASIM0 register to 0. Figure 10-9. When Reception Error Interrupt Is Separated from INTSR0 Signal (ISRM Bit = 0) (a) No error occurs during reception (b) An error occurs during reception INTSR0 signal (output)
Page 429 CHAPTER 10 SERIAL INTERFACE FUNCTION (6) Parity types and corresponding operation A parity bit is used to detect a bit error in communication data. Normally, the same type of parity bit is used on the transmission and reception sides. (a) Even parity (i) During transmission The parity bit is controlled so that the number of bits with the value “1”...
Page 430 CHAPTER 10 SERIAL INTERFACE FUNCTION (7) Receive data noise filter The RXD0 signal is sampled at the rising edge of the prescaler output base clock (f ). If the same sampling value is obtained twice, the match detector output changes, and this output is sampled as input data. Therefore, data not exceeding one clock width is judged to be noise and is not delivered to the internal circuit (see Figure 10-12).
Page 431: Dedicated Baud Rate Generator 0 (Brg0)
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.2.6 Dedicated baud rate generator 0 (BRG0) A dedicated baud rate generator, which consists of a source clock selector and an 8-bit programmable counter, generates serial clocks during transmission/reception by UART0. The dedicated baud rate generator output can be selected as the serial clock for each channel.
Page 432 CHAPTER 10 SERIAL INTERFACE FUNCTION (2) Serial clock generation A serial clock can be generated according to the settings of the CKSR0 and BRGC0 registers. The base clock to the 8-bit counter is selected by the TPS3 to TPS0 bits of the CKSR0 register. The 8-bit counter divisor value can be set by the MDL7 to MDL0 bits of the BRGC0 register.
Page 433 CHAPTER 10 SERIAL INTERFACE FUNCTION (b) Baud rate generator control register 0 (BRGC0) The BRGC0 register is an 8-bit register that controls the baud rate (serial transfer speed) of UART0. This register can be read or written in 8-bit units. Caution If the MDL7 to MDL0 bits are to be overwritten, the TXE0 and RXE0 bits should be set to 0 in the ASIM0 register first.
Page 434 CHAPTER 10 SERIAL INTERFACE FUNCTION (c) Baud rate The baud rate is the value obtained by the following formula. Baud rate = [bps] 2 × k = Frequency [Hz] of base clock selected by TPS3 to TPS0 bits of CKSR0 register. k = Value set by MDL7 to MDL0 bits of BRGC0 register (k = 8, 9, 10, ..., 255) (d) Baud rate error The baud rate error is obtained by the following formula.
Page 435 CHAPTER 10 SERIAL INTERFACE FUNCTION (3) Baud rate setting example Table 10-3. Baud Rate Generator Setting Data = 40 MHz = 33 MHz = 10 MHz Baud Rate (bps) 0.16 –0.07 0.16 0.16 –0.07 0.16 1200 0.16 –0.07 0.16 2400 0.16 –0.07 0.16...
Page 436 CHAPTER 10 SERIAL INTERFACE FUNCTION (4) Allowable baud rate range during reception The degree to which a discrepancy from the transmission destination’s baud rate is allowed during reception is shown below. Caution The equations described below should be used to set the baud rate error during reception so that it always is within the allowable error range.
Page 437 CHAPTER 10 SERIAL INTERFACE FUNCTION Therefore, the transfer destination’s maximum receivable baud rate (BRmax) is as follows. − BRmax = (FLmin/11) Brate 21k + 2 Similarly, the maximum allowable transfer rate (FLmax) can be obtained as follows. − × × −...
Page 438: Cautions
CHAPTER 10 SERIAL INTERFACE FUNCTION (5) Transfer rate during continuous transmission During continuous transmission, the transfer rate from a stop bit to the next start bit is extended two clocks of the base clock longer than normal. However, on the reception side, the transfer result is not affected since the timing is initialized by the detection of the start bit.
Page 439: Asynchronous Serial Interface 1 (Uart1)
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.3 Asynchronous Serial Interface 1 (UART1) 10.3.1 Features • Clocked (synchronous) mode/asynchronous mode can be selected • Operation clock Synchronous mode: Baud rate generator/external clock selectable Asynchronous mode: Baud rate generator • Transfer rate 300 bps to 153,600 bps (in asynchronous mode, f = 40 MHz) 4800 bps to 1000000 bps (in synchronous mode) •...
Page 440: Configuration
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.3.2 Configuration UART1 is controlled by asynchronous serial interface mode register 10 and 11 (ASIM10 and ASIM11) and asynchronous serial interface status register 1 (ASIS1). Receive data is held in the receive buffer registers (RXB1 and RXBL1), and transmit data is held in the transmit shift registers (TXS1 and TXSL1).
Page 441 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-16. Block Diagram of Asynchronous Serial Interface 1 Internal bus PE1 FE1 OVE1 Asynchronous Asynchronous Reception buffers 1, L1 serial interface mode serial interface status (RXB1, RXBL1) registers 10, 11 registers 1 (ASIM10, ASIM11) (ASIS1) Transmit Receive...
Page 442: Control Registers
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.3.3 Control registers Because UART1 shares its pins with CSI1, the UART1 mode must be preset by using the PMC3 and RFC3 registers (refer to 10.1.1 Selecting UART1 or CSI1 mode). (1) Asynchronous serial interface mode register 10 (ASIM10) The ASIM10 register is an 8-bit register that controls the UART1 transfer operation.
Page 443 CHAPTER 10 SERIAL INTERFACE FUNCTION <6> Address After reset ASIM10 RXE1 SCLS FFFFFA28H Bit position Bit name Function RXE1 Enables/disables reception. 0: Disables reception 1: Enables reception 5, 4 PS1, PS0 Specify parity bit length Operation No parity, extension bit operation 0 parity Transmit side →...
Page 444 CHAPTER 10 SERIAL INTERFACE FUNCTION (2) Asynchronous serial interface mode register 11 (ASIM11) The ASIM11 register is an 8-bit register that controls the UART1 transfer mode. This register can be read/written in 8-bit or 1-bit units Address After reset ASIM11 UMST UMSR FFFFFA2AH...
Page 445 CHAPTER 10 SERIAL INTERFACE FUNCTION (3) Asynchronous serial interface status register 1 (ASIS1) The ASIS1 register is a register that is configured of a UART1 transmission status flag (SOT1), reception status flag (SIR1), a bit (RB8) indicating the 9th bit when extension bit addition is enabled, and 3-bit error flags (PE1, FE1, OVE1) that indicate the error status at reception end.
Page 446 CHAPTER 10 SERIAL INTERFACE FUNCTION <7> <6> <2> <1> <0> Address After reset ASIS1 SOT1 SIR1 OVE1 FFFFFA2CH Bit position Bit name Function Status flag indicating transmission status. SOT1 0: Transmission end timing (when INTST1 is generated) Note 1: Indicates transmission status Note The transmission status is the status until the specified number of stop bits has been transmitted following write operation to the transmit register.
Page 447 CHAPTER 10 SERIAL INTERFACE FUNCTION (4) 2-frame continuous reception buffer register 1 (RXB1)/receive buffer register L1 (RXBL1) The RXB1 register is a 16-bit buffer register that holds receive data (during 2-frame continuous reception (UMSR bit of ASIM11 register = 1), during 9-bit extended data reception (EBS bit of ASIM11 register = 1)). During 7 or 8 bit character reception, 0 is stored in the MSB.
Page 448 CHAPTER 10 SERIAL INTERFACE FUNCTION (a) When 2-frame continuous reception is set RXB1 RXB15 RXB14 RXB13 RXB12 RXB11 RXB10 RXB9 RXB8 RXB7 RXB6 RXB5 RXB4 RXB3 RXB2 RXB1 RXB0 7-/8-bit data of 1st frame 7-/8-bit data of 2nd frame (b) When 9-bit extension reception is set RXB1 RXB15 RXB14...
Page 449 CHAPTER 10 SERIAL INTERFACE FUNCTION (c) Cautions <1> Operation upon occurrence of overrun error during 2-frame continuous reception • During normal operation Reception completion interrupt (INTSR1) generated at end of reception of 2nd frame, no error RXD1 Frame 1 Frame 2 •...
Page 450 CHAPTER 10 SERIAL INTERFACE FUNCTION (5) 2-frame continuous transmission shift register 1 (TXS1)/transmit shift register L1 (TXSL1) The TXS1 register is a 9-bit/2-frame continuous transmission processing shift register. Transmission is started by writing data to this register. A transmission completion interrupt request (INTST1) is generated in synchronization with the end of transmission of 1 frame or 2 frames including the TXS1 data.
Page 451: Interrupt Requests
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.3.4 Interrupt requests The following two types of interrupt request are generated from UART1. • Reception completion interrupt (INTSR1) • Transmission completion interrupt (INTST1) The reception completion interrupt has higher default priority than the transmission completion interrupt. Table 10-5.
Page 452: Operation
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.3.5 Operation (1) Data format Full-duplex serial data is transmitted and received. Figure 10-17 shows the format of transmit/receive data. One data frame consists of a start bit, character bits, a parity bit, and a stop bit(s). When 2 data frame transfer is set, both frames have the above-described format.
Page 453 CHAPTER 10 SERIAL INTERFACE FUNCTION Table 10-6. ASIM10, ASIM11 Register Settings and Data Format ASIM10, ASIM11 Register Settings Data Format CL Bit PS1 Bit PS0 Bit SL Bit EBS Bit D0 to D6    DATA Stop bit  ...
Page 454 CHAPTER 10 SERIAL INTERFACE FUNCTION (2) Transmission operation The transmission operation is started by writing data to 2-frame continuous transmission shift register 1 (TXS1)/transmit shift register L1 (TXSL1). Following data write, the start bit is transmitted from the next shift timing. Since the UART1 does not have a CTS (transmission enable signal) input pin, use a port when the other party confirms the reception enabled status.
Page 455 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-18. Asynchronous Serial Interface Transmission Completion Interrupt Timing (a) When stop bit length = 1 bit TXD1 (output) Start Parity Stop INTST1 interrupt Flag in transmission (SOT1) (b) When stop bit length = 2 bits TXD1 (output) Start Parity...
Page 456 CHAPTER 10 SERIAL INTERFACE FUNCTION (3) Continuous transmission of 3 or more frames In addition to the 1-frame/2-frame transmission function, UART1 also enables continuous transmission of 3 or more frames, using the method shown below. (a) How to continuously transmit 3 or more frames (when the stop bit is 1 bit (SL bit = 0)) Three frames can be continuously transmitted by writing transmit data to the TXS1/TXSL1 register in the period between the generation of the transmission completion interrupt request (INTST1) and 4 ×...
Page 457 CHAPTER 10 SERIAL INTERFACE FUNCTION (4) Reception operation The reception wait status is entered by setting the RXE1 bit of the ASIM10 register to 1. To start the reception operation, first perform start bit detection. Start bit detection is done by performing sampling of the RXD1 pin.
Page 458 CHAPTER 10 SERIAL INTERFACE FUNCTION (c) Reception completion interrupt request When reception of one frame of data has been completed (stop bit detection) when the RXE1 bit of the ASIM10 register = 1, the receive data in the shift register is transferred to RXB1/RXBL1 and a reception completion interrupt request (INTSR1) is generated after 1 frame or 2 frames of data have been transferred to RXB1/RXBL1.
Page 459 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-20. Asynchronous Serial Interface Reception Completion Interrupt Timing (a) When stop bit length = 1 bit 8 serial clocks 8 serial clocks Parity RXD1 (input) Start Stop INTSR1 interrupt Flag in reception (SIR1) (b) When stop bit length = 2 bits 8 serial clocks 8 serial clocks RXD1 (input)
Page 460 CHAPTER 10 SERIAL INTERFACE FUNCTION (5) Reception errors The flags for the three types of errors: parity errors, framing errors, and overrun errors, are affected in synchronization with reception operation. As a result of data reception, the PE1, FE1, and OVE1 flags of the ASIS1 register are set (1) and a reception completion interrupt request (INTSR1) is generated at the same time.
Page 461 CHAPTER 10 SERIAL INTERFACE FUNCTION (b) Odd parity <1> During transmission In contrast to even parity, the parity bit is controlled so that the number of bits with the value “1” within the transmit data including the parity bit is odd. The parity bit value is as follows. •...
Page 462: Synchronous Mode
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.3.6 Synchronous mode The synchronous mode can be set with the ASCK1 pin, which is the serial clock I/O pin. The synchronous mode is set with the MOD bit of the ASIM11 register, and the serial clock to be used for synchronization is selected with the SCLS bit of the ASIM10 register.
Page 463 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-22. Transmission/Reception Timing Chart for Synchronous Mode (1/3) (a) In 1-frame transmission/reception mode Serial clock Transmit data Stop bit Transmission register write signal Flag in transmission (SOT1) Transmission completion interrupt (INTST1) Flag in reception (SIR1) Reception completion interrupt...
Page 464 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-22. Transmission/Reception Timing Chart for Synchronous Mode (2/3) (b) In 2-frame continuous transmission/reception mode Serial clock Transmit data Stop bit Stop bit Transmission register write signal Flag in transmission (SOT1) Transmission completion interrupt (INTST1) Flag in reception (SIR1) Reception...
Page 465 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-22. Transmission/Reception Timing Chart for Synchronous Mode (3/3) (c) Transmission/reception timing and transmit data timing during serial clock output Serial clock (output) System clock Transmit data Transmission timing Reception timing Note Note The transmit data is delayed by 1 system clock in relation to the serial clock. (d) Transmission/reception timing and transmit data timing using external serial clock External serial clock System clock...
Page 466 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-23. Reception Completion Interrupt and Error Interrupt Generation Timing During Synchronous Mode Reception (a) During normal operation (in 1-frame reception mode) Receive data START STOP Flag in reception (SIR1) Reception completion interrupt (INTSR1) Error interrupt (b) In 2-frame continuous reception mode Receive data START...
Page 467: Dedicated Baud Rate Generator 1 (Brg1)
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.3.7 Dedicated baud rate generator 1 (BRG1) (1) Configuration of baud rate generator 1 (BRG1) For UART1, the serial clock can be selected from the dedicated baud rate generator output or internal system clock (f ) for each channel.
Page 468 CHAPTER 10 SERIAL INTERFACE FUNCTION (2) Dedicated baud rate generator 1 (BRG1) BRG1 is configured of an 8-bit timer counter for baud rate signal generation, a prescaler mode register that controls the generation of the baud rate signal (PRSM1), a prescaler compare register that sets the value of the 8-bit timer counter (PRSCM1), and a prescaler.
Page 469 CHAPTER 10 SERIAL INTERFACE FUNCTION (c) Prescaler compare register 1 (PRSCM1) PRSCM1 is an 8-bit compare register that sets the value of the 8-bit timer counter. This register can be read/written in 8-bit units. Cautions 1. The internal timer counter is cleared by writing to the PRSCM1 register. Therefore, do not overwrite the PRSCM1 register during a transmission operation.
Page 470 CHAPTER 10 SERIAL INTERFACE FUNCTION (f) Baud rate setting value The formulas for calculating the baud rate in the asynchronous mode and the synchronous mode and the formula for calculating the error are as follows. <1> Formula for calculating baud rate in asynchronous mode Baud rate = [bps] 2 ×...
Page 471 CHAPTER 10 SERIAL INTERFACE FUNCTION <4> Baud rate setting example In an actual system, the output of a prescaler module, etc. is connected to the input clock. Table 10- 8 shows the baud rate generator setting data at this time. Table 10-8.
Page 472 CHAPTER 10 SERIAL INTERFACE FUNCTION (3) Allowable baud rate range during reception The degree to which a discrepancy from the transmission destination’s baud rate is allowed during reception is shown below. Caution The equations described below should be used to set the baud rate error during reception so that it always is within the allowable error range.
Page 473 CHAPTER 10 SERIAL INTERFACE FUNCTION Therefore, the transfer destination’s maximum receivable baud rate (BRmax) is as follows. − BRmax = (FLmin/11) Brate 21k + 2 Similarly, the maximum allowable transfer rate (FLmax) can be obtained as follows. − × × −...
Page 474: Clocked Serial Interfaces 0, 1 (Csi0, Csi1)
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.4 Clocked Serial Interfaces 0, 1 (CSI0, CSI1) 10.4.1 Features • High-speed transfer: Maximum 5 Mbps • Half-duplex communications • Master mode or slave mode can be selected • Transmission data length: 8 bits or 16 bits can be set •...
Page 475: Configuration
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.4.2 Configuration CSIn is controlled via the clocked serial interface mode register (CSIMn) (n = 0, 1). Transmission/reception of data is performed by reading/writing the SIOn register (n = 0, 1). (1) Clocked serial interface mode registers 0, 1 (CSIM0, CSIM1) The CSIMn register is an 8-bit register that specifies the operation of CSIn.
Page 476 CHAPTER 10 SERIAL INTERFACE FUNCTION (12) Clocked serial interface initial transmit buffer register L (SOTBFL0, SOTBFL1) The SOTBFLn register is an 8-bit buffer register that stores initial transmit data in the repeat transfer mode. (13) Selector The selector selects the serial clock to be used. (14) Serial clock controller Controls the serial clock supply to the shift register.
Page 477 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-26. Block Diagram of Clocked Serial Interface Serial clock controller SCKn Clock start/stop control Selector & clock phase control Interrupt INTCSIn controller BRG3 SCKn Transmission control Transmission data control Control signal Initial transmit SO selection buffer register (SOTBFn/SOTBFLn) Transmit...
Page 478: Control Registers
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.4.3 Control registers Because CSI1 shares its pins with UART1, the CSI1 mode must be preset by using the PMC3 and RFC3 registers (refer to 10.1.1 Selecting mode of UART1 or CSI1). (1) Clocked serial interface mode registers 0, 1 (CSIM0, CSIM1) The CSIMn register controls the CSIn operation (n = 0, 1).
Page 479 CHAPTER 10 SERIAL INTERFACE FUNCTION <7> <6> <4> <0> Address After reset CSIM0 CSICAE0 TRMD0 DIR0 CSIT AUTO CSOT0 FFFFF900H <7> <6> <4> <0> Address After reset CSICAE1 TRMD1 DIR1 CSIT AUTO CSOT1 CSIM1 FFFFF910H Bit position Bit name Function Enables/disables CSIn operation.
Page 480 CHAPTER 10 SERIAL INTERFACE FUNCTION (2) Clocked serial interface clock selection registers 0, 1 (CSIC0, CSIC1) The CSICn register is an 8-bit register that controls the CSIn transfer operation (n = 0, 1). These registers can be read/written in 8-bit or 1-bit units. Caution The CSICn register can be overwritten only when the CSICAEn bit of the CSIMn register = 0.
Page 481 CHAPTER 10 SERIAL INTERFACE FUNCTION Address After reset CSIC0 CKS2 CKS1 CKS0 FFFFF901H Address After reset CSIC1 CKS2 CKS1 CKS0 FFFFF911H Bit position Bit name Function 4, 3 CKP, DAP Specifies operation mode. Operation mode SCKn (I/O) SOn (output) DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 SIn (input) SCKn (I/O) SOn (output)
Page 482 CHAPTER 10 SERIAL INTERFACE FUNCTION (3) Clocked serial interface receive buffer registers 0, 1 (SIRB0, SIRB1) The SIRBn register is a 16-bit buffer register that stores receive data (n = 0, 1). When the receive-only mode is set (TRMDn bit of CSIMn register = 0), the reception operation is started by reading data from the SIRBn register.
Page 483 CHAPTER 10 SERIAL INTERFACE FUNCTION (4) Clocked serial interface receive buffer registers L0, L1 (SIRBL0, SIRBL1) The SIRBLn register is an 8-bit buffer register that stores receive data (n = 0, 1). When the receive-only mode is set (TRMDn bit of CSIMn register = 0), the reception operation is started by reading data from the SIRBLn register.
Page 484 CHAPTER 10 SERIAL INTERFACE FUNCTION (5) Clocked serial interface read-only receive buffer registers 0, 1 (SIRBE0, SIRBE1) The SIRBEn register is a 16-bit buffer register that stores receive data (n = 0, 1). These registers are read-only, in 16-bit units. In addition to reset input, this register can also be initialized by clearing (0) the CSICAEn bit of the CSIMn register.
Page 485 CHAPTER 10 SERIAL INTERFACE FUNCTION (6) Clocked serial interface read-only receive buffer registers L0, L1 (SIRBEL0, SIRBEL1) The SIRBELn register is an 8-bit buffer register that stores receive data (n = 0, 1). These registers are read-only, in 8-bit or 1-bit units. In addition to reset input, this register can also be initialized by clearing (0) the CSICAEn bit of the CSIMn register.
Page 486 CHAPTER 10 SERIAL INTERFACE FUNCTION (7) Clocked serial interface transmit buffer registers 0, 1 (SOTB0, SOTB1) The SOTBn register is a 16-bit buffer register that stores transmit data (n = 0, 1). When the transmission/reception mode is set (TRMDn bit of CSIMn register = 1), the transmission operation is started by writing data to the SOTBn register.
Page 487 CHAPTER 10 SERIAL INTERFACE FUNCTION (8) Clocked serial interface transmit buffer registers L0, L1 (SOTBL0, SOTBL1) The SOTBLn register is an 8-bit buffer register that stores transmit data (n = 0, 1). When the transmission/reception mode is set (TRMDn bit of CSIMn register = 1), the transmission operation is started by writing data to the SOTBLn register.
Page 488 CHAPTER 10 SERIAL INTERFACE FUNCTION (9) Clocked serial interface initial transmit buffer registers 0, 1 (SOTBF0, SOTBF1) The SOTBFn register is a 16-bit buffer register that stores initial transmission data in the repeat transfer mode (n = 0, 1). The transmission operation is not started even if data is written to the SOTBFn register. These registers can be read/written in 16-bit units.
Page 489 CHAPTER 10 SERIAL INTERFACE FUNCTION (10) Clocked serial interface initial transmit buffer registers L0, L1 (SOTBFL0, SOTBFL1) The SOTBFLn register is an 8-bit buffer register that stores initial transmission data in the repeat transfer mode (n = 0, 1). The transmission operation is not started even if data is written to the SOTBFLn register. These registers can be read/written in 8-bit or 1-bit units.
Page 490 CHAPTER 10 SERIAL INTERFACE FUNCTION (11) Serial I/O shift registers 0, 1 (SIO0, SIO1) The SIOn register is a 16-bit shift register that converts parallel data into serial data (n = 0, 1). The transfer operation is not started even if the SIOn register is read. These registers are read-only, in 16-bit units.
Page 491 CHAPTER 10 SERIAL INTERFACE FUNCTION (12) Serial I/O shift registers L0, L1 (SIOL0, SIOL1) The SIOLn register is an 8-bit shift register that converts parallel data into serial data (n = 0, 1). The transfer operation is not started even if the SIOLn register is read. These registers are read-only, in 8-bit or 1-bit units.
Page 492: Operation
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.4.4 Operation (1) Single transfer mode (a) Usage Note 1 In the receive-only mode (TRMDn bit of CSIMn register = 0), transfer is started by reading the receive data buffer register (SIRBn/SIRBLn) (n = 0, 1). Note 2 In the transmission/reception mode (TRMDn bit of CSIMn register = 1), transfer is started by writing to the transmit data buffer register (SOTBn/SOTBLn).
Page 493 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-27. Timing Chart in Single Transfer Mode (1/2) (a) In transmission/reception mode, data length: 8 bits, transfer direction: MSB first, no interrupt delay, single transfer mode, operation mode: CKP bit = 0, DAP bit = 0 SCKn (I/O) (55H)
Page 494 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-27. Timing Chart in Single Transfer Mode (2/2) (b) In transmission/reception mode, data length: 8 bits, transfer direction: MSB first, no interrupt delay, single transfer mode, operation mode: CKP bit = 0, DAP bit = 1 SCKn (I/O) (55H)
Page 495 CHAPTER 10 SERIAL INTERFACE FUNCTION (b) Clock phase selection The following shows the timing when changing the conditions for clock phase selection (CKP bit of CSICn register) and data phase selection (DAP bit of CSICn register) under the following conditions. •...
Page 496 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-28. Timing Chart According to Clock Phase Selection (2/2) (c) When CKP bit = 0, DAP bit = 1 SCKn (I/O) SIn (input) SOn (output) DO6 DO5 DO4 DO3 DO2 DO1 Reg_R/W INTCSIn interrupt CSOTn bit (d) When CKP bit = 1, DAP bit = 1 SCKn (I/O)
Page 497 CHAPTER 10 SERIAL INTERFACE FUNCTION (c) Transmission/reception completion interrupt request signals (INTCSI0, INTCSI1) INTCSIn is set (1) upon completion of data transmission/reception. Caution The delay mode (CSIT bit = 1) is valid only in the master mode (bits CKS2 to CKS0 of the CSICn register are not 111B).
Page 498 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-29. Timing Chart of Interrupt Request Signal Output in Delay Mode (2/2) (b) When CKP bit = 1, DAP bit = 1 Input clock SCKn (I/O) SIn (input) SOn (output) Reg_R/W INTCSIn interrupt CSOTn bit Delay Remarks 1.
Page 499 CHAPTER 10 SERIAL INTERFACE FUNCTION (2) Repeat transfer mode (a) Usage (receive-only) <1> Set the repeat transfer mode (AUTO bit of CSIMn register = 1) and the receive-only mode (TRMDn bit of CSIMn register = 0). <2> Read the SIRBn register (start transfer with dummy read). <3>...
Page 500 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-30. Repeat Transfer (Receive-Only) Timing Chart SCKn (I/O) SIn (input) din-1 din-2 din-3 din-4 din-5 SIOLn din-5 register SIRBLn din-1 din-2 din-3 din-4 register SIRBEn (d4) Reg_RD SIRBn (dummy) SIRBn (d1) SIRBn (d2) SIRBn (d3) SIOn (d5) CSOTn bit INTCSIn...
Page 501 CHAPTER 10 SERIAL INTERFACE FUNCTION (b) Usage (transmission/reception) <1> Set the repeat transfer mode (AUTO bit of CSIMn register = 1) and the transmission/reception mode (TRMDn bit of CSIMn register = 1) <2> Write the first data to the SOTBFn register. <3>...
Page 502 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-31. Repeat Transfer (Transmission/Reception) Timing Chart SCKn (I/O) SOn (output) dout-1 dout-2 dout-3 dout-4 dout-5 din-1 din-2 din-3 din-4 din-5 SIn (input) SOTBFLn dout-1 register SOTBLn dout-2 dout-3 dout-4 dout-5 register SIOLn din-5 register SIRBLn din-1 din-2...
Page 503 CHAPTER 10 SERIAL INTERFACE FUNCTION (c) Next transfer reservation period In the repeat transfer mode, the next transfer must be prepared with the period shown in Figure 10-32. Figure 10-32. Timing Chart of Next Transfer Reservation Period (1/2) (a) When data length: 8 bits, operation mode: CKP bit = 0, DAP bit = 0 SCKn (I/O) INTCSIn...
Page 504 CHAPTER 10 SERIAL INTERFACE FUNCTION Figure 10-32. Timing Chart of Next Transfer Reservation Period (2/2) (c) When data length: 8 bits, operation mode: CKP bit = 0, DAP bit = 1 SCKn (I/O) INTCSIn interrupt Reservation period: 6.5 SCKn cycles (d) When data length: 16 bits, operation mode: CKP bit = 0, DAP bit = 1 SCKn (I/O)
Page 505 CHAPTER 10 SERIAL INTERFACE FUNCTION (d) Cautions To continue repeat transfers, it is necessary to either read the SIRBn register or write to the SOTBn register during the transfer reservation period. If access is performed to the SIRBn register or the SOTBn register when the transfer reservation period is over, the following occurs.
Page 506 CHAPTER 10 SERIAL INTERFACE FUNCTION (ii) In case of conflict between interrupt request and register access Since continuous transfer has stopped once, executed as a new repeat transfer. In the slave mode, a bit phase error transfer error results (refer to Figure 10-34). In the transmission/reception mode, the value of the SOTBFn register is retransmitted, and illegal data is sent.
Page 507: Output Pins
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.4.5 Output pins (1) SCKn pin When the CSIn operation is disabled (CSICAEn bit of CSIMn register = 0), the SCKn pin output status is as follows (n = 0, 1). Table 10-9. SCKn Pin Output Status CKS2 CKS1 CKS0...
Page 508: Dedicated Baud Rate Generator 3 (Brg3)
CHAPTER 10 SERIAL INTERFACE FUNCTION 10.4.6 Dedicated baud rate generator 3 (BRG3) (1) Configuration of baud rate generator 3 (BRG3) Dedicated baud rate generator output or the internal system clock (f ) can be selected for the CSI0 and CSI1 serial clocks.
Page 509 CHAPTER 10 SERIAL INTERFACE FUNCTION (2) Dedicated baud rate generator 3 (BRG3) BRG3 is configured by an 8-bit timer counter that generates the baud rate signal, prescaler mode register 3 (PRSM3), which controls baud rate signal generation, prescaler compare register 3 (PRSCM3), which sets the value of the 8-bit timer counter, and a prescaler.
Page 510 CHAPTER 10 SERIAL INTERFACE FUNCTION (c) Prescaler compare register 3 (PRSCM3) PRSCM3 is an 8-bit compare register that sets the value of the 8-bit timer counter. This register can be read/written in 8-bit units. Cautions 1. The internal timer counter is cleared by writing to the PRSM3 register. Therefore, do not write to the PRSCM3 register during transmission.
Page 511 CHAPTER 10 SERIAL INTERFACE FUNCTION (e) Baud rate setting value Table 10-11. Baud Rate Generator Setting Data (a) When f = 32 MHz BGCS1 BGCS0 PRSCM Register Value Clock (Hz) 4,000,000 2,000,000 1,000,000 500,000 250,000 100,000 50,000 25,000 10,000 5,000 (b) When f = 40 MHz BGCS1...
Page 512: Chapter 11 A/D Converter
CHAPTER 11 A/D CONVERTER 11.1 Features • Two 10-bit resolution on-chip A/D converters (A/D converter 0 and 1) Simultaneous sampling by two circuits is possible. • Analog input: Total of 14 channels for two circuits A/D converter 0: 6 channels A/D converter 1: 8 channels •...
Page 513 CHAPTER 11 A/D CONVERTER (4) D/A converter The D/A converter is used to generate the voltage that matches the analog input. The output voltage of the D/A converter is controlled by the successive approximation register (SAR). (5) Successive approximation register (SAR) The SAR is a 10-bit register that controls the output value of the D/A converter for comparing with the analog input voltage value.
Page 514 CHAPTER 11 A/D CONVERTER Figure 11-1. Block Diagram of A/D Converter 0 or 1 ANIn0 ANIn1 ANIn2 ANIn3 Comparator Sample and and D/A ANIn4 hold circuit converter ANIn5 ANI16 ANI17 SAR (10) INTADn ADCRn0 ITRG0 Controller ADCRn1 ADCRn2 ADTRGn INTDETn ADCRn3 Trigger source switching ADCRn4...
Page 515 CHAPTER 11 A/D CONVERTER Figure 11-2. Block Diagram of Trigger Source Switching Circuit in Timer Trigger Made ADTRG0 Trigger A/D converter 0 INTCM003 Trigger INTCM013 ITRG10 ITRG13 ITRG12 ITRG11 ADTRG1 Trigger A/D converter 1 Trigger INTTM00 INTTM01 INTCM004 INTCM005 INTCM014 INTCM015 ITRG1 ITRG41 ITRG40...
Page 516: Functions Added To V850E/Ia2
CHAPTER 11 A/D CONVERTER 11.3 Functions Added to V850E/IA2 (1) Addition of INTCM004, INTCM005, INTCM014, INTCM015 as timer trigger sources The timer trigger source (INTTM0n, INTCM0n3 to INTCM0n5) is selected using A/D internal trigger selection registers 0 and 1 (ITRG0 and ITRG1) when the timer trigger mode is set by A/D scan mode registers 00 and 10 (ADSCM00 and ADSCM10).
Page 517: Control Registers
CHAPTER 11 A/D CONVERTER 11.4 Control Registers (1) A/D scan mode registers 00 and 10 (ADSCM00, ADSCM10) The ADSCMn0 registers are 16-bit registers that select analog input pins, specify operation modes, and control conversion operations. They can be read or written in 16-bit units. When the higher 8 bits of the ADSCMn0 register are used as the ADSCMn0H register and the lower 8 bits are used as the ADSCMn0L register, they can be read/written in 8-bit or 1-bit units.
Page 518 CHAPTER 11 A/D CONVERTER (2/2) Bit position Bit name Function 7 to 4 SANI3 to Specifies conversion start analog input pin in scan mode. SANI0 These bits are ignored in select mode. SANI3 SANI2 SANI1 SANI0 Scan start analog input pin ANIn0 ANIn1 ANIn2...
Page 519 CHAPTER 11 A/D CONVERTER (2) A/D scan mode registers 01 and 11 (ADSCM01, ADSCM11) The ADSCMn1 registers are 16-bit registers that set the conversion time of the A/D converter. They can be read or written in 16-bit units. When the higher 8 bits of the ADSCMn1 register are used as the ADSCMn1H register, and the lower 8 bits are used as the ADSCMn1L register, the ADSCMn1H register can be read/written in 8-bit units, and the ADSCMn1L register is read-only, in 8-bit units.
Page 520 CHAPTER 11 A/D CONVERTER (3) A/D voltage detection mode registers 0 and 1 (ADETM0, ADETM1) The ADETMn registers are 16-bit registers that set the voltage detection mode. In the voltage detection mode, the analog input pin for which voltage detection is being performed and a reference voltage value are compared and an interrupt is set in response to the comparison result.
Page 521 CHAPTER 11 A/D CONVERTER (4) A/D conversion result registers 00 to 05 and 10 to 17 (ADCR00 to ADCR05, ADCR10 to ADCR17) The ADCR0m and ADCR1n registers are 10-bit registers that hold the results of A/D conversions (m = 0 to 5, n = 0 to 7).
Page 522 CHAPTER 11 A/D CONVERTER The correspondence between the analog input pins and the ADCR0m and ADCR1n registers is shown below. Table 11-3. Correspondence Between Analog Input Pins and ADCR0m and ADCR1n Registers A/D Converter Analog Input Pin A/D Conversion Result Register A/D converter 0 ANI00 ADCR00...
Page 523 CHAPTER 11 A/D CONVERTER The relationship between the analog voltage input to an analog input pin (ANI0m or ANI1n) and the value of the A/D conversion result register (ADCR0m or ADCR1n) is as follows (m = 0 to 5, n = 0 to 7): ADCR = INT ( ×1,024 + 0.5) (ADCR −...
Page 524 CHAPTER 11 A/D CONVERTER (5) A/D internal trigger selection registers 0, 1 (ITRG0, ITRG1) The ITRGn register switches the trigger source in timer trigger mode. The timer trigger source of A/D converters 0 and 1 can be set using the ITRGn register. This register can be read or written in 8-bit or 1-bit units.
Page 525 CHAPTER 11 A/D CONVERTER Table 11-4. Timer Trigger Source Selection of A/D Converters 0 and 1 (1/3) ITRGm3 ITRGm2 ITRGm1 ITRG41 ITRG40 ITRG31 ITRG30 ITRG20 ITRG10 Trigger Source of A/D Converter n × × × × × Selects INTCM003 × ×...
Page 526 CHAPTER 11 A/D CONVERTER Table 11-4. Timer Trigger Source Selection of A/D Converters 0 and 1 (2/3) ITRGm3 ITRGm2 ITRGm1 ITRG41 ITRG40 ITRG31 ITRG30 ITRG20 ITRG10 Trigger Source of A/D Converter n × × Selects INTCM013, INTTM01, INTCM004, INTCM005, INTCM014 ×...
Page 527 CHAPTER 11 A/D CONVERTER Table 11-4. Timer Trigger Source Selection of A/D Converters 0 and 1 (3/3) ITRGm3 ITRGm2 ITRGm1 ITRG41 ITRG40 ITRG31 ITRG30 ITRG20 ITRG10 Trigger Source of A/D Converter n × × Selects INTCM013, INTTM01, INTCM005, INTCM014, INTCM015 ×...
Page 528: Interrupt Requests
CHAPTER 11 A/D CONVERTER 11.5 Interrupt Requests A/D converters 0 and 1 generate two kinds of interrupts. • A/D conversion end interrupts (INTAD0, INTAD1) • Voltage detection interrupts (INTDET0, INTDET1) (1) A/D conversion end interrupts (INTAD0, INTAD1) In the A/D conversion enabled status, an A/D conversion end interrupt is generated when a specified number of A/D conversions have been completed.
Page 529: A/D Converter Operation
CHAPTER 11 A/D CONVERTER 11.6 A/D Converter Operation 11.6.1 A/D converter basic operation A/D conversion is performed using the following procedure. (1) Set the analog input selection and the operation mode and trigger mode specifications using the ADSCM00 Note 1 or ADSCM10 register .
Page 530: Operation Modes And Trigger Modes
CHAPTER 11 A/D CONVERTER 11.6.2 Operation modes and trigger modes Diverse conversion operations can be specified for A/D converters 0 and 1 by specifying the operation mode and trigger mode. The operation mode and trigger mode are set using the ADSCM00 or ADSCM10 register. The relationship between the operation mode and the trigger mode is shown below.
Page 531 CHAPTER 11 A/D CONVERTER (2) Operation modes The two operation modes, which are the modes that set the ANI00 to ANI05 and ANI10 to ANI17 pins, are select mode and scan mode. These modes are set using the ADSCM00 and ADSCM10 registers. (a) Select mode In select mode, one analog input specified by the ADSCM00 or ADSCM10 register is A/D converted.
Page 532 CHAPTER 11 A/D CONVERTER (b) Scan mode In scan mode, pins from the A/D conversion start analog input pin to the A/D conversion termination analog input pin specified by the ADSCM00 or ADSCM10 register are sequentially selected and A/D converted. The A/D conversion result is stored in the ADCR0m or ADCR1n register corresponding to the analog input (m = 0 to 5, n = 0 to 7).
Page 533: Operation In A/D Trigger Mode
CHAPTER 11 A/D CONVERTER 11.7 Operation in A/D Trigger Mode Setting the ADCE0 or ADCE1 bit of the ADSCM00 or ADSCM10 register to 1 starts A/D conversion. 11.7.1 Operation in select mode One analog input specified by the ADSCM00 or ADSCM10 register is A/D converted at a time and the result is stored in the ADCR0m or ADCR1n register.
Page 534: Operation In Scan Mode
CHAPTER 11 A/D CONVERTER 11.7.2 Operation in scan mode Pins from the conversion start analog input pin to the conversion termination analog input pin specified by ADSCM00 or ADSCM10 register are sequentially selected and A/D converted. An A/D conversion result is stored in the ADCR0m or ADCR1n register corresponding to the analog input (m = 0 to 5, n = 0 to 7).
Page 535: Operation In A/D Trigger Polling Mode
CHAPTER 11 A/D CONVERTER 11.8 Operation in A/D Trigger Polling Mode Setting the ADCE0 or ADCE1 bit of the ADSCM00 or ADSCM10 register to 1 starts A/D conversion. Both select mode and scan mode are available in A/D trigger polling mode. Since the ADCS0 or ADCS1 bit of the ADSCM00 or ADSCM10 register remains 1 after the INTAD0 or INTAD1 interrupt in this mode, it is not necessary to write 1 in the ADCE0 or ADCE1 bit as an A/D conversion restart operation.
Page 536: Operation In Scan Mode
CHAPTER 11 A/D CONVERTER 11.8.2 Operation in scan mode Pins from the conversion start analog input pin to the conversion termination analog input pin specified by the ADSCM00 or ADSCM10 register are sequentially selected and A/D converted. The A/D conversion result is stored in the ADCR0m or ADCR1n register corresponding to the analog input (m = 0 to 5, n = 0 to 7).
Page 537: Operation In Timer Trigger Mode
CHAPTER 11 A/D CONVERTER 11.9 Operation in Timer Trigger Mode A/D converters 0 and 1 have a total of 14 channels of analog inputs (ANI00 to ANI05 and ANI10 to ANI17). For these channels, an interrupt signal specified by A/D internal trigger selection registers 0 and 1 (ITRG0, INTRG1) can be set as a conversion trigger.
Page 538: Operation In Scan Mode
CHAPTER 11 A/D CONVERTER 11.9.2 Operation in scan mode Using the interrupt signal specified by A/D internal trigger selection registers 0 and 1 (ITRG0, ITRG1) as a trigger, pins from the conversion start analog input pin to the conversion termination analog input pin specified by the ADSCM00 or ADSCM10 register are sequentially selected and A/D converted.
Page 539: Operation In External Trigger Mode
CHAPTER 11 A/D CONVERTER 11.10 Operation in External Trigger Mode In external trigger mode, an analog input (ANI00 to ANI05, ANI10 to ANI17) is A/D converted at the ADTRG0 or ADTRG1 pin input timing. The valid edge of an external input signal in external trigger mode can be specified as the rising edge, falling edge, or both rising and falling edges using the ES21 or ES20 bit of the INTM1 register for A/D converter 0 and the ES31 or ES30 bit of the INTM1 register for A/D converter 1.
Page 540 CHAPTER 11 A/D CONVERTER 11.10.2 Operation in scan mode Using the ADTRG0 or ADTRG1 signal as a trigger, pins from the conversion start analog input pin to the conversion termination analog input pin specified by the ADSCM00 or ADSCM10 register are sequentially selected and A/D converted.
Page 541 CHAPTER 11 A/D CONVERTER 11.11 Operation Cautions 11.11.1 Stopping A/D conversion operation If 0 is written in the ADCE0 or ADCE1 bit of the ADSCM00 or ADSCM10 register during A/D conversion, it stops the A/D conversion operation and an A/D conversion result is not stored in the ADCR0m or ADCR1n register (m = 0 to 5, n = 0 to 7).
Page 542 CHAPTER 11 A/D CONVERTER 11.11.6 Timing that makes the A/D conversion result undefined If the timing of the end of A/D conversion and the timing of the stop of operation of the A/D converter conflict, the A/D conversion value may be undefined. Because of this, be sure to read the A/D conversion result while the A/D converter is in operation.
Page 543 CHAPTER 11 A/D CONVERTER 11.12 How to Read A/D Converter Characteristics Table Here, special terms unique to the A/D converter are explained. (1) Resolution This is the minimum analog input voltage that can be identified. That is, the percentage of the analog input voltage per bit of digital output is called 1LSB (Least Significant Bit).
Page 544 CHAPTER 11 A/D CONVERTER (3) Quantization error When analog values are converted to digital values, a ±1/2LSB error naturally occurs. In an A/D converter, an analog input voltage in a range of ±1/2LSB is converted to the same digital code, so a quantization error cannot be avoided.
Page 545 CHAPTER 11 A/D CONVERTER (5) Full-scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value (3/2LSB) when the digital output changes from 1……110 to 1……111. Figure 11-19. Full-Scale Error Full-scale error (n = 0, 1) –3 –2...
Page 546 CHAPTER 11 A/D CONVERTER (7) Integral linearity error This shows the degree to which the conversion characteristics deviate from the ideal linear relationship. It expresses the maximum value of the difference between the actual measurement value and the ideal straight line when the zero-scale error and full-scale error are 0.
Page 547 CHAPTER 12 PORT FUNCTIONS 12.1 Features • Input-only ports: I/O ports: • Ports function alternately as I/O pins of other peripheral functions • Input or output can be specified in bit units 12.2 Basic Configuration of Ports The V850E/IA2 has a total of 53 on-chip I/O ports (ports 0 to 4, DH, DL, CT, CM), of which 6 are input-only ports. The port configuration is shown below.
Page 548 CHAPTER 12 PORT FUNCTIONS Port Name Pin Name Port Function Function in Control Mode Block Type Port 0 P00 to P05 6-bit input NMI input Timer/counter output stop signal input External interrupt input A/D converter (ADC) external trigger input Timer 3 output stop signal input Port 1 P10 to P12 3-bit I/O...
Page 549 CHAPTER 12 PORT FUNCTIONS (2) Functions of each port pin after reset and registers that set port or control mode Port Name Pin Name Pin Function After Reset Mode-Setting Register Single-Chip Mode ROMless Mode − Port 0 P00/NMI P00 (input mode) P01/ESO0/INTP0 P01 (input mode) P02/ESO1/INTP1...
Page 550 CHAPTER 12 PORT FUNCTIONS (3) Port block diagrams Figure 12-1. Type A Block Diagram PMCmn PMmn Output signal in PORT control mode Address Remark m: Port number n: Bit number User’s Manual U15195EJ5V0UD...
Page 551 CHAPTER 12 PORT FUNCTIONS Figure 12-2. Type B Block Diagram PMCmn PMmn PORT Address Noise elimination Input signal in Edge detection control mode Remark m: Port number n: Bit number User’s Manual U15195EJ5V0UD...
Page 552 CHAPTER 12 PORT FUNCTIONS Figure 12-3. Type C Block Diagram PMCmn PMmn PORT Address Input signal in control mode Remark m: Port number n: Bit number User’s Manual U15195EJ5V0UD...
Page 553 CHAPTER 12 PORT FUNCTIONS Figure 12-4. Type D Block Diagram Set/reset control of PMC PMCCM0 PMCM0 PORT PCM0 PCM0 Address Input signal in control mode User’s Manual U15195EJ5V0UD...
Page 554 CHAPTER 12 PORT FUNCTIONS Figure 12-5. Type E Block Diagram Noise elimination Address Input signal in Edge detection control mode Remark m: Port number n: Bit number Figure 12-6. Type F Block Diagram PFC33 PMC33 PM33 Output signal in control mode PORT Address User’s Manual U15195EJ5V0UD...
Page 555 CHAPTER 12 PORT FUNCTIONS Figure 12-7. Type G Block Diagram PFC32 PMC32 PM32 PORT Address Input signal in Note control mode Note The signal level of the input signal is as follows in control mode. PMC32 bit PFC32 bit Input signal in control mode (PMC3 register) (PFC3 register) RXD1...
Page 556 CHAPTER 12 PORT FUNCTIONS Figure 12-8. Type H Block Diagram ASCK1 output SCK1 output enable signal enable signal PFC34 Selector PMC34 PM34 Output signal 1 in control mode Output signal 2 in control mode PORT Address Input signal in Note control mode Note The signal level of the input signal is as follows in control mode.
Page 557 CHAPTER 12 PORT FUNCTIONS Figure 12-9. Type I Block Diagram Set/reset control of PMC PMCmn PMmn Output signal in control mode PORT Address Remark m: Port number n: Bit number User’s Manual U15195EJ5V0UD...
Page 558 CHAPTER 12 PORT FUNCTIONS Figure 12-10. Type J Block Diagram SCK0 output enable signal PMC42 PM42 Output signal in control mode PORT Address Input signal in control mode User’s Manual U15195EJ5V0UD...
Page 559 CHAPTER 12 PORT FUNCTIONS Figure 12-11. Type K Block Diagram PFCmn PMCmn PMmn Output signal in PORT control mode Address Input signal in Noise elimination control mode Edge detection Remark m: Port number n: Bit number User’s Manual U15195EJ5V0UD...
Page 560 CHAPTER 12 PORT FUNCTIONS Figure 12-12. Type L Block Diagram PFC27 PMC27 TO3SP PM27 Note INTP4 Output signal in control mode PORT Address Input signal in Noise elimination control mode Edge detection Note Output signal after an edge on the INTP4 pin has been detected. User’s Manual U15195EJ5V0UD...
Page 561 CHAPTER 12 PORT FUNCTIONS Figure 12-13. Type M Block Diagram Set/reset control of PMC PSTPOFF BOENx PMCmn PMmn Output signal in control mode PORT Address BOENx Input signal in control mode BOENx Remarks 1. m: Port number n: Bit number 2.
Page 562 CHAPTER 12 PORT FUNCTIONS Figure 12-14. Type N Block Diagram Set/reset control of PMC PSTPOFF PMCmn PMmn Output signal in control mode PORT Address Remarks 1. m: Port number n: Bit number 2. PSTPOFF: Signal in IDLE/software STOP mode User’s Manual U15195EJ5V0UD...
Page 563 CHAPTER 12 PORT FUNCTIONS 12.3 Pin Functions of Each Port 12.3.1 Port 0 Port 0 is a 6-bit input-only port in which all pins are fixed to input. Address After reset − − FFFFF400H Undefined Besides functioning as an input port, in control mode, it can also operate as the timer/counter output stop signal input, external interrupt request input, A/D converter (ADC) external trigger input, and timer 3 output stop signal input.
Page 564 CHAPTER 12 PORT FUNCTIONS 12.3.2 Port 1 Port 1 is a 3-bit I/O port in which input or output can be specified in 1-bit units. Address After reset − − − − − FFFFF402H Undefined Bit position Bit name Function 2 to 0 I/O port (n = 2 to 0)
Page 565 CHAPTER 12 PORT FUNCTIONS (b) Port 1 mode control register (PMC1) This register can be read or written in 8-bit or 1-bit units. Write 0 in bits 3 to 7. Caution The PMC11 and PMC12 bits are also used as external interrupts (INTP100 and INTP101). When not using them as external interrupts, mask interrupt requests (refer to 7.3.4 Interrupt control registers (xxICn)).
Page 566 CHAPTER 12 PORT FUNCTIONS 12.3.3 Port 2 Port 2 is an 8-bit I/O port in which input or output can be specified in 1-bit units. Address After reset FFFFF404H Undefined Bit position Bit name Function 7 to 0 I/O port (n = 7 to 0) Besides functioning as a port, in control mode, it also can operate as the timer/counter I/O and external interrupt request input.
Page 567 CHAPTER 12 PORT FUNCTIONS (b) Port 2 mode control register (PMC2) This register can be read or written in 8-bit or 1-bit units. Caution The PMC20, PMC25, and PMC26 bits also serve as external interrupts (INTP20, INTP25, and INTP30). When not using them as external interrupts, mask interrupt requests (refer to 7.3.4 Interrupt control registers (xxICn)).
Page 568 CHAPTER 12 PORT FUNCTIONS 12.3.4 Port 3 Port 3 is a 5-bit I/O port in which input or output can be specified in 1-bit units Address After reset − − − FFFFF406H Undefined Bit position Bit name Function 4 to 0 I/O port (n = 4 to 0) Besides functioning as a port, in control mode, it also can operate as the serial interface (UART0, UART1/CSI1)
Page 569 CHAPTER 12 PORT FUNCTIONS (b) Port 3 mode control register (PMC3) This register can be read or written in 8-bit or 1-bit units. Address After reset PMC3 PMC34 PMC33 PMC32 PMC31 PMC30 FFFFF446H Bit position Bit name Function PMC34 Specifies operation mode of P34 pin 0: I/O port mode 1: ASCK1/SCK1 I/O mode PMC33...
Page 570 CHAPTER 12 PORT FUNCTIONS 12.3.5 Port 4 Port 4 is a 3-bit I/O port in which input or output can be specified in 1-bit units. Address After reset − − − − − FFFFF408H Undefined Bit position Bit name Function 2 to 0 I/O port (n = 2 to 0)
Page 571 CHAPTER 12 PORT FUNCTIONS (2) Setting of I/O mode and control mode The port 4 mode register (PM4) is used to set the I/O mode of port 4 and the port 4 mode control register (PMC4) is used to set the operation in control mode. (a) Port 4 mode register (PM4) This register can be read or written in 8-bit or 1-bit units.
Page 572 CHAPTER 12 PORT FUNCTIONS 12.3.6 Port DH Port DH is a 6-bit I/O port in which input or output can be specified in 1-bit units. Address After reset − − PDH5 PDH4 PDH3 PDH2 PDH1 PDH0 FFFFF006H Undefined Bit position Bit name Function 5 to 0...
Page 573 CHAPTER 12 PORT FUNCTIONS (2) Setting of I/O mode and control mode The port DH mode register (PMDH) is used to set the I/O mode of port DH and the port DH mode control register (PMCDH) is used to set the operation in control mode. (a) Port DH mode register (PMDH) This register can be read or written in 8-bit or 1-bit units.
Page 574 CHAPTER 12 PORT FUNCTIONS 12.3.7 Port DL Port DL is a 16-bit I/O port in which input or output can be specified in 1-bit units. When using the higher 8 bits of PDL as PDLH and the lower 8 bits as PDLL, it can be used as an 8-bit I/O port that can specify input/output in 1-bit units.
Page 575 CHAPTER 12 PORT FUNCTIONS (2) Setting of I/O mode and control mode The port DL mode register (PMDL) is used to set the I/O mode of port DL and the port DL mode control register (PMCDL) is used to set the operation in control mode. (a) Port DL mode register (PMDL) The PMDL register can be read or written in 16-bit units.
Page 576 CHAPTER 12 PORT FUNCTIONS 12.3.8 Port CT Port CT is a 4-bit I/O port in which input or output can be specified in 1-bit units. Address After reset − − − − PCT6 PCT4 PCT1 PCT0 FFFFF00AH Undefined Bit position Bit name Function 6, 4, 1, 0...
Page 577 CHAPTER 12 PORT FUNCTIONS (2) Setting of I/O mode and control mode The port CT mode register (PMCT) is used to set the I/O mode of port CT and the port CT mode control register (PMCCT) is used to set the operation in control mode. (a) Port CT mode register (PMCT) This register can be read or written in 8-bit or 1-bit units.
Page 578 CHAPTER 12 PORT FUNCTIONS 12.3.9 Port CM Port CM is a 2-bit I/O port in which input or output can be specified in 1-bit units. Address After reset − − − − − − PCM1 PCM0 FFFFF00CH Undefined Bit position Bit name Function 1, 0...
Page 579 CHAPTER 12 PORT FUNCTIONS (2) Setting of I/O mode and control mode The port CM mode register (PMCM) is used to set the I/O mode of port CM and the CM mode control register (PMCCM) is used to set the operation in control mode. (a) Port CM mode register (PMCM) This register can be read or written in 8-bit or 1-bit units.
Page 580 CHAPTER 12 PORT FUNCTIONS 12.4 Operation of Port Function The operation of a port differs depending on whether it is set in the input or output mode, as follows. 12.4.1 Writing to I/O port (1) In output mode A value can be written to the output latch (Pn) by writing it to the port n register (Pn). The contents of the output latch are output from the pin.
Page 581 CHAPTER 12 PORT FUNCTIONS 12.5 Noise Eliminator 12.5.1 Interrupt pins A timing controller to guarantee the noise elimination time shown below is added to the pins that operate as NMI and valid edge inputs in port control mode. A signal input that changes in less than this elimination time is not accepted internally.
Page 582 CHAPTER 12 PORT FUNCTIONS Figure 12-15. Example of Noise Elimination Timing Noise elimination clock Input signal 2 clocks 2 clocks 3 clocks 3 clocks 4 clocks 4 clocks 5 clocks 5 clocks Internal signal Timers 1, 2, 3 rising edge detection Timers 1, 2, 3 falling edge detection Caution If there are three or less noise elimination clocks while the timer 1 or 3 input signal is high...
Page 583 CHAPTER 12 PORT FUNCTIONS (1) Timer 10 noise elimination time selection register (NRC10) The NRC10 register is used to set the clock source of timer 10 input pin noise elimination time. It can be read or written in 8-bit or 1-bit units. Caution The noise elimination function starts operating by setting the TM1CE0 bit of the TMC10 register to 1 (enabling count operations).
Page 584 CHAPTER 12 PORT FUNCTIONS (2) Timer 3 noise elimination time selection register (NRC3) The NRC3 register is used to set the clock source of the timer 3 input pin noise elimination time. It can be read or written in 8-bit or 1-bit units. Caution The noise elimination function starts operating by setting the TM3CE0 bit of the TMC30 register to 1 (enabling count operations).
Page 585 CHAPTER 12 PORT FUNCTIONS 12.5.3 Timer 2 input pins A noise eliminator using analog filtering and digital filtering using clock sampling are added to the timer 2 input pins. A signal input that changes in less than this elimination time is not accepted internally. Analog Filter Noise Digital Filter Elimination Time...
Page 586 CHAPTER 12 PORT FUNCTIONS (1) Timer 2 input filter mode registers 0 to 5 (FEM0 to FEM5) The FEMn registers are used to specify timer 2 input pin filtering and to set the clock source of noise elimination time and the input valid edge. It can be read or written in 8-bit or 1-bit units.
Page 587 CHAPTER 12 PORT FUNCTIONS (2/2) Bit position Bit name Function 3, 2 EDGE01n, Specifies the INTP2n pin valid edge. EDGE00n EDGE01n EGE00n Operation Note Interrupt due to INTCC2n Rising edge Falling edge Both rising and falling edges Note Specify when selecting INTCC2n according to a match of TM20, TM21 and the subchannel compare registers (TMS01n, TMS00n bit settings) (n = 0 to 5).
Page 588 CHAPTER 12 PORT FUNCTIONS 12.6 Cautions 12.6.1 Hysteresis characteristics The following ports do not have hysteresis characteristics in the port mode. P10 to P12 P20, P21, P25 to P27 P30, P32, P34 P40, P42 User’s Manual U15195EJ5V0UD...
Page 589 CHAPTER 13 RESET FUNCTION When a low level is input to the RESET pin, the system is reset and each hardware item of the V850E/IA2 is initialized to its initial status. When the RESET pin changes from low level to high level, the reset status is released and the CPU starts program execution.
Page 590 CHAPTER 13 RESET FUNCTION (1) Reset signal acknowledgment RESET Analog Analog Analog delay delay delay Elimination as noise Internal system Note reset signal Reset acknowledgment Reset release Note The internal system reset signal remains active for a period of at least 4 system clocks after the timing of a reset release by the RESET pin.
Page 591 CHAPTER 13 RESET FUNCTION <2> Reset timing (5 V) REGIN (3.3 V) RESET (input) Active low Internal REGRES5 (5 V) Undefined Active low Internal RES5 (5 V) Active high Undefined Internal RES3 (3.3 V) Undefined Active high Analog delay Note Regulator Oscillation output...
Page 592 CHAPTER 13 RESET FUNCTION (a) Pins to be controlled TO000 to TO005, TO010 to TO015, P10/TO10/TIUD10, P11/INTP100/TCUD10, P12/INTP101/TCLR10, P20/INTP20/TI2, P21/INTP21/TO21, P22/INTP22/TO22, P23/INTP23/TO23, P24/INTP24/TO24, P25/INTP25/TCLR2, P26/TCLR3/INTP30/TI3, P27/INTP31/TO3 (b) Circuit of above pins I/O control 5 V system reset (RES5) signal of pin 1: Reset Output buffer enable signal 0: Output buffer off...
Page 593 CHAPTER 13 RESET FUNCTION (ii) Reset during normal operation (5 V system) REGIN (3.3 V system) RESET (input) Internal RES5 (5 V system) Internal RES3 (3.3 V system) Note 1 Note 1 Note 1 Note 2 Pin to be controlled Operates High impedance Operates...
Page 594 CHAPTER 13 RESET FUNCTION 13.3 Initialization Initialize the contents of each register as needed within the program. Table 13-2 shows the initial values of the CPU, internal RAM, and on-chip peripheral I/O after reset. Table 13-2. Initial Values of CPU, Internal RAM, and On-Chip Peripheral I/O After Reset (1/5) On-Chip Hardware Register Name Initial Value After Reset...
Page 595 CHAPTER 13 RESET FUNCTION Table 13-2. Initial Values of CPU, Internal RAM, and On-Chip Peripheral I/O After Reset (2/5) On-Chip Hardware Register Name Initial Value After Reset On-chip Interrupt/ Valid edge selection register (SESC) peripheral exception Timer 2 input filter mode register n (FEMn) (n = 0 to 5) control function Interrupt control registers (P0IC0 to P0IC4, DETIC0, DETIC1, TM0IC0, TM0IC1, TM2IC0, TM2IC1, TM3IC0, CC10IC0, CC10IC1, CC2IC0 to...
Page 596 CHAPTER 13 RESET FUNCTION Table 13-2. Initial Values of CPU, Internal RAM, and On-Chip Peripheral I/O After Reset (3/5) On-Chip Hardware Register Name Initial Value After Reset On-chip Timer 2 Timer 2 clock stop register 0 (STOPTE0) 0000H peripheral Timer 2 clock stop register 0L (STOPTE0L) Timer 2 clock stop register 0H (STOPTE0H) Timer 2 count clock/control edge selection register 0 (CSE0) 0000H...
Page 597 CHAPTER 13 RESET FUNCTION Table 13-2. Initial Values of CPU, Internal RAM, and On-Chip Peripheral I/O After Reset (4/5) On-Chip Hardware Register Name Initial Value After Reset On-chip Timer 3 Valid edge selection register (SESC) peripheral Timer 3 clock selection register (PRM03) Timer 3 noise elimination time selection register (NRC3) Timer 3 output control register (TOC3) Timer 4...
Page 598 Flash memory Flash programming mode control register (FLPMC) 08H/0CH/00H µ Note PD703114: µ PD70F3114: 08H or 0CH (For details, refer to 15.7.12 Flash programming mode control register (FLPMC).) Caution In the table above, “Undefined” means either undefined at the time of a power-on reset or undefined due to data destruction when RESET ↓...
Page 599 CHAPTER 14 REGULATOR 14.1 Features • Two power supplies, one for the internal CPU and one for the peripheral interface, are not necessary. • A 5 V single power supply system can be configured by connecting an N-ch transistor (2SD1950 (VL standard product, surface mount type) or 2SD1581 (independent type) is recommended).
Page 600 CHAPTER 14 REGULATOR 14.3 Connection Example (1) When using an on-chip regulator An on-chip regulator is used connected to an N-ch transistor. An example of connection when using an N-ch transistor and the mount pad dimensions when mounted on the 2SD1950 (VL standard product) (when using a glass epoxy board) are shown below.
Page 601 CHAPTER 14 REGULATOR Figure 14-2. Mount Pad Dimensions When Mounted on 2SD1950 (VL Standard Product) (Glass Epoxy Board) (Unit: mm) 45° 45° (2) When using an external regulator When an on-chip regulator is not used, an external regulator can be used. An example of connection when using an external regulator application is shown below.
Page 602 CHAPTER 14 REGULATOR 14.4 Control Register (1) Regulator control register (REGC) The REGC register controls the operation of the regulator. This register can be read/written in 8-bit or 1-bit units. Cautions 1. Change the value of the REGC register only once after the system has been reset for system stabilization.
Page 603 µ CHAPTER 15 FLASH MEMORY ( PD70F3114) µ PD70F3114 is the flash memory version of the V850E/IA2 and has an on-chip 128 KB flash memory. Caution There are differences in noise immunity and noise radiation between the flash memory and mask ROM versions.
Page 604 µ CHAPTER 15 FLASH MEMORY ( PD70F3114) When the flash writing adapter (FA-100GC-8EU) and dual-power-supply adapter (FA-TVC) are used for µ writing to the PD70F3114GC, connect the pins as follows. Table 15-1. Connection of V850E/IA2 Flash Writing Adapter (FA-100GC-8EU) Name Marked V850E/IA2 on FA-100GC- When UART0 Used...
Page 605 µ CHAPTER 15 FLASH MEMORY ( PD70F3114) When the flash writing adapter (FA-100GF-3BA) and dual-power-supply adapter (FA-TVC) are used for µ writing to the PD70F3114GF, connect the pins as follows. Table 15-2. Connection of V850E/IA2 Flash Writing Adapter (FA-100GF-3BA) Name Marked V850E/IA2 on FA-100GF- When UART0 Used...
Page 606 µ CHAPTER 15 FLASH MEMORY ( PD70F3114) 15.3 Programming Environment The following shows the environment required for writing programs to the flash memory of the V850E/IA2. Figure 15-1. Environment for Writing a Program to Flash Memory REGIN FA-TVC RS-232-C Axxxx Bxxxxx Cxxxxxx STATVE...
Page 607 µ CHAPTER 15 FLASH MEMORY ( PD70F3114) (2) CSI0 Transfer rate: up to 2 MHz (MSB first) Figure 15-3. Communication with Dedicated Flash Programmer (CSI0) REGIN FA-TVC Axxxx Bxxxxx Cxxxxxx STATVE PG-FP4 RESET RESET V850E/IA2 Dedicated flash programmer SCK0 Caution The operating clock amplitude of the V850E/IA2 is 3.3 V. The dedicated flash programmer outputs transfer clocks and the V850E/IA2 operates as a slave.
Page 608 µ CHAPTER 15 FLASH MEMORY ( PD70F3114) 15.5 Pin Connection When performing on-board writing, install a connector on the target system to connect to the dedicated flash programmer. Also, install a function on-board to switch from the normal operation mode (single-chip mode or ROMless mode) to the flash memory programming mode.
Page 609 µ CHAPTER 15 FLASH MEMORY ( PD70F3114) Figure 15-6. Conflict of Signals (Serial Interface Input Pin) V850E/IA2 Conflict of signals Dedicated flash programmer connection pin Input pin Other device Output pin In the flash memory programming mode, the signal that the dedicated flash programmer sends out conflicts with signals the other device outputs.
Page 610 µ CHAPTER 15 FLASH MEMORY ( PD70F3114) 15.5.3 RESET pin When connecting the reset signals of the dedicated flash programmer to the RESET pin, which is connected, to the reset signal generator on-board, a conflict of signals occurs. To avoid the conflict of signals, isolate the connection to the reset signal generator.
Page 611 µ CHAPTER 15 FLASH MEMORY ( PD70F3114) 15.6 Programming Method 15.6.1 Flash memory control The following shows the procedure for manipulating the flash memory. Figure 15-9. Flash Memory Manipulating Procedure Start Supply RESET pulse Switch to flash memory programming mode Select communication mode Manipulate flash memory End?
Page 612 µ CHAPTER 15 FLASH MEMORY ( PD70F3114) 15.6.2 Flash memory programming mode When rewriting the contents of flash memory using the dedicated flash programmer, set the V850E/IA1 in the flash memory programming mode. To switch to this mode, set the MODE0 and MODE1/V pins before canceling reset.
Page 613 µ CHAPTER 15 FLASH MEMORY ( PD70F3114) 15.6.4 Communication commands The V850E/IA2 communicates with the dedicated flash programmer by means of commands. A command sent from the dedicated flash programmer to the V850E/IA2 is called a “command”. The response signal sent from the V850E/IA2 to the dedicated flash programmer is called the “response command”.
Page 614 µ CHAPTER 15 FLASH MEMORY ( PD70F3114) The V850E/IA2 sends back response commands for the commands issued from the dedicated flash programmer. The following shows the response commands the V850E/IA2 sends out. Table 15-5. Response Commands Response Command Name Function ACK (acknowledge) Acknowledges command/data, etc.
Page 615 µ CHAPTER 15 FLASH MEMORY ( PD70F3114) 15.7.2 Self-programming function µ PD70F3114 provides self-programming functions, as shown in Table 15-7. By combining these functions, erasing/writing flash memory becomes possible. Table 15-7. Function List Type Function Name Function Erase Area erase Erases the specified area.
Page 616 µ CHAPTER 15 FLASH MEMORY ( PD70F3114) The self-programming interface is outlined below. Figure 15-13. Outline of Self-Programming Interface Application program RAM parameter Entry program Self-programming interface Device internal processing Flash-memory manipulation Flash memory 15.7.4 Hardware environment To write or erase the flash memory, a high voltage must be applied to the V pin.
Page 617 µ CHAPTER 15 FLASH MEMORY ( PD70F3114) The voltage applied to the V pin must satisfy the following conditions: • Hold the voltage applied to the V pin at 0 V in the normal operation mode and hold the V voltage only while the flash memory is being manipulated.
Page 618 µ CHAPTER 15 FLASH MEMORY ( PD70F3114) 15.7.5 Software environment The following conditions must be satisfied before using the entry program to call the device internal processing. Table 15-8. Software Environmental Conditions Item Description Location of entry Execute the entry program in memory other than the block 0 space and flash memory area. program The device internal processing cannot be directly called by the program that is executed on the flash memory.
Page 619 µ CHAPTER 15 FLASH MEMORY ( PD70F3114) 15.7.6 Self-programming function number To identify a self-programming function, the following numbers are assigned to the respective functions. These function numbers are used as parameters when the device internal processing is called. Table 15-9. Self-Programming Function Number Function No.
Page 620 µ CHAPTER 15 FLASH MEMORY ( PD70F3114) 15.7.7 Calling parameters The arguments used to call the self-programming function are shown in the table below. In addition to these arguments, parameters such as the write time and erase time are set to the RAM parameters indicated by ep (r30). Table 15-10.
Page 621 µ CHAPTER 15 FLASH MEMORY ( PD70F3114) 15.7.8 Contents of RAM parameters Reserve the following 48-byte area in the internal RAM or external RAM for the RAM parameters, and set the parameters to be input. Set the base addresses of these parameters to ep (r30). Table 15-11.
Page 622 µ CHAPTER 15 FLASH MEMORY ( PD70F3114) 15.7.9 Errors during self-programming The following errors related to manipulation of the flash memory may occur during self-programming. An error occurs if the return value (r10) of each function is not 0. Table 15-12. Errors During Self-Programming Error Function Description...
Page 623 µ CHAPTER 15 FLASH MEMORY ( PD70F3114) 15.7.11 Area number µ The area numbers and memory map of the PD70F3114 are shown below. Figure 15-16. Area Configuration 0 x 1 F F F F (End address of area 1) Area 1 (64 KB) 0 x 1 0 0 0 0 (Start address of area 1) 0 x 0 F F F F (End address of area 0)
Page 624 Note 08H: When writing voltage is not applied to the V 0CH: When writing voltage is applied to the V µ 00H: Product not provided with flash memory ( PD703114) Bit position Bit name Function Enables/disables writing/erasing on-chip flash memory. When this bit is 1,...
Page 625 µ CHAPTER 15 FLASH MEMORY ( PD70F3114) Setting data to the flash programming mode control register (FLPMC) is performed in the following sequence. <1> Disable interrupts (set the NP bit and ID bit of the PSW to 1). <2> Prepare the data to be set in the specific register in a general-purpose register. <3>...
Page 626 µ CHAPTER 15 FLASH MEMORY ( PD70F3114) 15.7.13 Calling device internal processing This section explains the procedure to call the device internal processing from the entry program. Before calling the device internal processing, make sure that all the conditions of the hardware and software environments are satisfied and that the necessary arguments and RAM parameters have been set.
Page 627 µ CHAPTER 15 FLASH MEMORY ( PD70F3114) (4) Program example An example of a program in which the entry program is executed as a subroutine is shown below. In this example, the return address is saved to the stack and then the device internal processing is called. This program must be located in memory other than the block 0 space and flash memory area.
Page 628 µ CHAPTER 15 FLASH MEMORY ( PD70F3114) (5) Internal manipulation setup parameter µ If the self-programming mode is switched to the normal operation mode, the PD70F3114 must wait for 100 µ s before it accesses the flash memory. In the program example in (4) above, the elapse of this wait time is ensured by setting ISETUP to “104”...
Page 629 µ CHAPTER 15 FLASH MEMORY ( PD70F3114) 15.7.14 Erasing flash memory flow The procedure to erase the flash memory is illustrated below. The processing of each function number must be executed in accordance with the specified calling procedure. Figure 15-17. Erasing Flash Memory Flow Erase Set RAM parameter.
Page 630 µ CHAPTER 15 FLASH MEMORY ( PD70F3114) 15.7.15 Continuous writing flow The procedure to write data all at once to the flash memory by using the function to continuously write data in word units is illustrated below. The processing of each function number must be executed in accordance with the specified calling procedure.
Page 631 µ CHAPTER 15 FLASH MEMORY ( PD70F3114) 15.7.16 Internal verify flow The procedure of internal verification is illustrated below. The processing of each function number must be executed in accordance with the specified calling procedure. Figure 15-19. Internal Verify Flow Internal verify Set RAM parameter.
Page 632 µ CHAPTER 15 FLASH MEMORY ( PD70F3114) 15.7.17 Acquiring flash information flow The procedure to acquire the flash information is illustrated below. The processing of each function number must be executed in accordance with the specified calling procedure. Figure 15-20. Acquiring Flash Information Flow Acquiring flash information Set RAM parameter.
Page 633 µ CHAPTER 15 FLASH MEMORY ( PD70F3114) 15.7.18 Self-programming library V850 Series Flash Memory Self-Programming User’s Manual is available for reference when executing self- programming. In this manual, the library uses the self-programming interface of the V850 Series and can be used in C as a utility and as part of the application program.
Page 634 µ CHAPTER 15 FLASH MEMORY ( PD70F3114) The configuration of the self-programming library is outlined below. Figure 15-22. Outline of Self-Programming Library Configuration Application program C interface Self-programming library Entry program RAM parameter Self-programming interface Device internal processing Flash memory manipulation Flash memory User’s Manual U15195EJ5V0UD...
Page 635 µ It is possible to distinguish a flash memory version ( PD70F3114) and a mask ROM version ( PD703114) by means of software, using the methods shown below. <1> Disable interrupts (set the NP bit of PSW to 1). <2> Write data to the peripheral command register (PHCMD).
Page 636 CHAPTER 16 ELECTRICAL SPECIFICATIONS 16.1 Normal Operation Mode Absolute Maximum Ratings (T = 25°C) Parameter Symbol Conditions Ratings Unit Power supply voltage REGIN REGIN pin –0.5 to +4.6 –0.5 to +7.0 –0.5 to +7.0 –0.5 to +0.5 Note 1 , AV pins –0.5 to V + 0.5...
Page 637 CHAPTER 16 ELECTRICAL SPECIFICATIONS Notes 1. Be sure not to exceed the absolute maximum ratings (MAX. value) of each power supply voltage. Make sure that the following conditions of the V voltage application timing are satisfied when the flash memory is written. •...
Page 638 CHAPTER 16 ELECTRICAL SPECIFICATIONS Clock Oscillator Characteristics = 5.0 V ±0.5 V, V = –40 to +85°C, REGIN = 3.0 to 3.6 V, V = RV = CV = 0 V) (a) Ceramic resonator or crystal resonator connection Parameter Symbol Conditions MIN.
Page 639 CHAPTER 16 ELECTRICAL SPECIFICATIONS Recommended Oscillator Constant (a) Ceramic resonator (i) Murata Manufacturing Co., Ltd. (T = –40 to +85°C) Type Product Name Oscillation Recommended Circuit Constant Recommended Voltage Frequency Range (MHz) C1 (pF) C2 (pF) (Ω) MIN. (V) MAX. (V) Surface mount CSTCR4M00G55-R0 On-chip...
Page 640 µ ±10 Analog pin input leakage ANI00 to ANI05, ANI10 to ANI17 pins LIAN current µ Power supply During REGIN Note 5, PD703114 1.8f + 15 3.0f + 30 Note 4 current normal µ Note 5, PD70F3114 2.0f + 15 3.2f...
Page 641 STOP mode, REGIN = V DDDR DDDR STOP mode, DDDR = RV = HV DDDR µ µ Data retention current REGIN = V PD703114 DDDR DDDR µ µ PD70F3114 µ = RV = HV , Note 1 DDDR DDDR µ...
Page 642 CHAPTER 16 ELECTRICAL SPECIFICATIONS = 5.0 V ±0.5 V, V AC Characteristics (T = –40 to +85°C, REGIN = 3.0 to 3.6 V, V = RV = CV = 0 V, output pin load capacitance: C = 50 pF) AC test input test points (a) Other than (b), (c), and (d) below 0.8 V 0.8 V...
Page 643 CHAPTER 16 ELECTRICAL SPECIFICATIONS Load condition (Device under test) = 50 pF Caution In cases where the load capacitance is greater than 50 pF due to the circuit configuration, insert a buffer or other element to reduce the device’s load capacitance to 50 pF or lower. User’s Manual U15195EJ5V0UD...
Page 644 CHAPTER 16 ELECTRICAL SPECIFICATIONS (1) Clock timing = 5.0 V ±0.5 V, V = –40 to +85°C, REGIN = 3.0 to 3.6 V, V = RV = CV = 0 V, output pin load capacitance: C = 50 pF) Parameter Symbol Conditions MIN.
Page 645 CHAPTER 16 ELECTRICAL SPECIFICATIONS (2) Output waveform (except for CLKOUT) = 5.0 V ±0.5 V, V = –40 to +85°C, REGIN = 3.0 to 3.6 V, V = RV = CV = 0 V, output pin load capacitance: C = 50 pF) Parameter Symbol Conditions...
Page 646 CHAPTER 16 ELECTRICAL SPECIFICATIONS (4) Reset timing = 5.0 V ±0.5 V, V = –40 to +85°C, REGIN = 3.0 to 3.6 V, V = RV = CV = 0 V, C = 50 pF) Parameter Symbol Conditions MIN. MAX. Unit RESET pin high-level width <15>...
Page 647 CHAPTER 16 ELECTRICAL SPECIFICATIONS (5) Multiplexed bus timing = 5.0 V ±0.5 V, (a) CLKOUT asynchronous (T = –40 to +85°C, REGIN = 3.0 to 3.6 V, V = RV = CV = 0 V, output pin load capacitance: C = 50 pF) Parameter Symbol...
Page 648 CHAPTER 16 ELECTRICAL SPECIFICATIONS = 5.0 V ±0.5 V, (b) CLKOUT synchronous (T = –40 to +85°C, REGIN = 3.0 to 3.6 V, V = RV = CV = 0 V, output pin load capacitance: C = 50 pF) Parameter Symbol Conditions MIN.
Page 649 CHAPTER 16 ELECTRICAL SPECIFICATIONS (c) Read cycle (CLKOUT synchronous/asynchronous, 1 wait) CLKOUT (output) <40> A16 to A21 (output) <20> <44> <45> <41> Hi-Z AD0 to AD15 (I/O) Address Data <42> <42> <17> <18> <23> ASTB (output) <28> <43> <25> <19> <43>...
Page 650 CHAPTER 16 ELECTRICAL SPECIFICATIONS (d) Write cycle (CLKOUT synchronous/asynchronous, 1 wait) CLKOUT (output) <40> A16 to A21 (output) <46> AD0 to AD15 (I/O) Address Data <42> <42> <17> <18> ASTB (output) <43> <28> <25> <29> <43> <22> <30> <31> LWR (output) UWR (output) <27>...
Page 651 CHAPTER 16 ELECTRICAL SPECIFICATIONS (6) Interrupt timing = 5.0 V ±0.5 V, V = –40 to +85°C, REGIN = 3.0 to 3.6 V, V = RV = CV = 0 V, C = 50 pF) Parameter Symbol Conditions MIN. MAX. Unit NMI high-level width <49>...
Page 652 CHAPTER 16 ELECTRICAL SPECIFICATIONS (7) Timer input timing = 5.0 V ±0.5 V, V = –40 to +85°C, REGIN = 3.0 to 3.6 V, V = RV = CV = 0 V, C = 50 pF) Parameter Symbol Conditions MIN. MAX.
Page 653 CHAPTER 16 ELECTRICAL SPECIFICATIONS (8) Timer operating frequency = 5.0 V ±0.5 V, V = –40 to +85°C, REGIN = 3.0 to 3.6 V, V = RV = CV = 0 V, output pin load capacitance: C = 50 pF) Parameter Symbol Conditions...
Page 654 CHAPTER 16 ELECTRICAL SPECIFICATIONS (9) CSI timing (2/2) <57> <59> <58> SCKn (I/O) <61> <60> (input) Input data <62> <63> (output) Output data Remarks 1. The broken lines indicate high impedance. 2. n = 0, 1 (10) UART0 timing = 5.0 V ±0.5 V, V = –40 to +85°C, REGIN = 3.0 to 3.6 V, V = RV = CV...
Page 655 CHAPTER 16 ELECTRICAL SPECIFICATIONS (11) UART1 timing (1/2) (a) Clocked master mode = 5.0 V ±0.5 V, V = –40 to +85°C, REGIN = 3.0 to 3.6 V, V = RV = CV = 0 V, output pin load capacitance: C = 50 pF) Parameter Symbol...
Page 656 CHAPTER 16 ELECTRICAL SPECIFICATIONS (11) UART1 timing (2/2) <64> <66> <65> ASCK1 (I/O) <68> <67> RXD1 (input) Input data <69> <70> TXD1 (output) Output data User’s Manual U15195EJ5V0UD...
Page 657 CHAPTER 16 ELECTRICAL SPECIFICATIONS = 5 .0 V ±0.5 V, A/D Converter Characteristics (T = –40 to +85°C, REGIN = 3.0 to 3.6 V, AV = RV = CV = 0 V, C = 50 pF) Parameter Symbol Conditions MIN. TYP.
Page 658 CHAPTER 16 ELECTRICAL SPECIFICATIONS 16.2 Flash Memory Programming Mode Basic Characteristics (T =10 to 40°C (during rewrite), T = –40 to +85°C (except during rewrite), = 5.0 V ±0.5 V, V REGIN = 3.0 to 3.6 V, V = RV = CV = 0 V) Parameter...
Page 659 CHAPTER 16 ELECTRICAL SPECIFICATIONS Serial Write Operation Characteristics = 5.0 V ±0.5 V, V = 10 to +40°C, REGIN = 3.0 to 3.6 V, V = RV = CV = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit ↑ to V ↑...
Page 660 CHAPTER 17 PACKAGE DRAWINGS 100-PIN PLASTIC LQFP (FINE PITCH) (14x14) detail of lead end NOTE ITEM MILLIMETERS Each lead centerline is located within 0.08 mm of 16.00±0.20 its true position (T.P.) at maximum material condition. 14.00±0.20 14.00±0.20 16.00±0.20 1.00 1.00 0.22 +0.05 −0.04 0.08...
Page 661 CHAPTER 17 PACKAGE DRAWINGS 100-PIN PLASTIC QFP (14x20) detail of lead end NOTE ITEM MILLIMETERS Each lead centerline is located within 0.15 mm of 23.6±0.4 its true position (T.P.) at maximum material condition. 20.0±0.2 14.0±0.2 17.6±0.4 0.30±0.10 0.15 0.65 (T.P.) 1.8±0.2 0.8±0.2 0.15 +0.10...
Page 662 CHAPTER 18 RECOMMENDED SOLDERING CONDITIONS µ PD703114 and 70F3114 should be soldered and mounted under the following recommended conditions. For technical information, see the following website. Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html) Table 18-1. Surface Mounting Type Soldering Conditions µ 100-pin plastic LQFP (fine pitch) (14 × 14) PD703114GC-×××-8EU:...
Page 663 Caution Do not use different soldering methods together (except for partial heating). Remarks 1. Products with -A at the end of the part number are lead-free products. 2. For soldering methods and conditions other than those recommended above, consult an NEC Electronics sales representative.
Page 664 APPENDIX A NOTES ON TARGET SYSTEM DESIGN The following shows a diagram of the connection conditions between the in-circuit emulator option board and conversion connector. Design your system making allowances for conditions such as the form of parts mounted on the target system as shown below.
Page 665 APPENDIX A NOTES ON TARGET SYSTEM DESIGN Figure A-2. 100-Pin Plastic QFP (14 × 20) Side view In-circuit emulator IE-V850E-MC In-circuit emulator option board IE-703114-MC-EM1 Conversion connector 231.26 mm Note NEXB-2R100SD/RB YQGUIDE YQPACK100RB NQPACK100RB Target system Note YQSOCKET100SDN (sold separately) can be inserted here to adjust the height (height: 3.2 mm). Top view IE-V850E-MC Target system...
Page 666 APPENDIX B REGISTER INDEX (1/9) Symbol Register Name Unit Page ADCR00 A/D conversion result register 00 ADCR01 A/D conversion result register 01 ADCR02 A/D conversion result register 02 ADCR03 A/D conversion result register 03 ADCR04 A/D conversion result register 04 ADCR05 A/D conversion result register 05 ADCR10...
Page 667 APPENDIX B REGISTER INDEX (2/9) Symbol Register Name Unit Page ASIS0 Asynchronous serial interface status register 0 UART0 ASIS1 Asynchronous serial interface status register 1 UART1 Address wait control register Bus cycle control register BCT0 Bus cycle type configuration register 0 BCT1 Bus cycle type configuration register 1 BFCM00...
Page 668 APPENDIX B REGISTER INDEX (3/9) Symbol Register Name Unit Page CM001 Compare register 001 TM00 CM002 Compare register 002 TM00 CM003 Compare register 003 TM00 CM004 Compare register 004 TM00 CM005 Compare register 005 TM00 CM00IC1 Interrupt control register INTC CM010 Compare register 010 TM01...
Page 669 APPENDIX B REGISTER INDEX (4/9) Symbol Register Name Unit Page CSL10 CC101 capture input selection register TM10 CVPE10 Timer 2 subchannel 1 main capture/compare register CVPE20 Timer 2 subchannel 2 main capture/compare register CVPE30 Timer 2 subchannel 3 main capture/compare register CVPE40 Timer 2 subchannel 4 main capture/compare register CVSE00...
Page 670 APPENDIX B REGISTER INDEX (5/9) Symbol Register Name Unit Page DSA1H DMA source address register 1H DMAC DSA1L DMA source address register 1L DMAC DSA2H DMA source address register 2H DMAC DSA2L DMA source address register 2L DMAC DSA3H DMA source address register 3H DMAC DSA3L DMA source address register 3L...
Page 671 APPENDIX B REGISTER INDEX (6/9) Symbol Register Name Unit Page INTM2 External interrupt mode register 2 INTC ISPR In-service priority register INTC ITRG0 A/D internal trigger selection register 0 ITRG1 A/D internal trigger selection register 1 LOCKR Lock register NRC10 Timer 10 noise elimination time selection register TM10 NRC3...
Page 672 APPENDIX B REGISTER INDEX (7/9) Symbol Register Name Unit Page PMC4 Port 4 mode control register Port PMCCM Port CM mode control register Port PMCCT Port CT mode control register Port PMCDH Port DH mode control register Port PMCDL Port DL mode control register Port PMCDLH Port DL mode control register H...
Page 673 APPENDIX B REGISTER INDEX (8/9) Symbol Register Name Unit Page SIOL1 Serial I/O shift register L1 CSI1 SIRB0 Clocked serial interface receive buffer register 0 CSI0 SIRB1 Clocked serial interface receive buffer register 1 CSI1 SIRBE0 Clocked serial interface read-only receive buffer register 0 CSI0 SIRBE1 Clocked serial interface read-only receive buffer register 1...
Page 674 APPENDIX B REGISTER INDEX (9/9) Symbol Register Name Unit Page TM2IC1 Interrupt control register INTC Timer 3 TM3IC0 Interrupt control register INTC Timer 4 TMC00 Timer control register 00 TM00 TMC00H Timer control register 00H TM00 TMC00L Timer control register 00L TM00 TMC01 Timer control register 01...
Page 675 APPENDIX C INSTRUCTION SET LIST C.1 Conventions (1) Symbols used in operand descriptions Symbol Explanation reg1 General-purpose register (Used as source register) reg2 General-purpose register (Usually used as destination register. Used as source register in some instructions.) reg3 General-purpose register (Usually stores remainder of division result or higher 32 bits of multiplication result.) bit#3 3-bit data for bit number specification...
Page 676 APPENDIX C INSTRUCTION SET LIST (3) Symbols used in operations Symbol Explanation ← Assignment GR [ ] General-purpose register SR [ ] System register zero-extend (n) Zero-extend n to word length. sign-extend (n) Sign-extend n to word length. load-memory (a, b) Read data of size “b”...
Page 677 APPENDIX C INSTRUCTION SET LIST (5) Symbols used in flag operations Symbol Explanation (Blank) No change Clear to 0. × Set or cleared according to result. Previously saved value is restored. (6) Condition codes Condition Name Condition Code Condition Expression Explanation (cond) (CCCC)
Page 678 APPENDIX C INSTRUCTION SET LIST C.2 Instruction Set (Alphabetical Order) (1/5) Mnemonic Operands Opcode Operation Execution Clock Flags × × × × r r r r r 0 0 1 1 1 0 R R R R R GR[reg2] ← GR[reg2] + GR[reg1] reg1, reg2 ×...
Page 679 APPENDIX C INSTRUCTION SET LIST (2/5) Mnemonic Operands Opcode Operation Execution Clock Flags sp ← sp + zero-extend (imm5 logically shift left by 2) DISPOSE imm5, list12 0 0 0 0 0 1 1 0 0 1 i i i i i L GR[reg in list12] ←...
Page 680 APPENDIX C INSTRUCTION SET LIST (3/5) Mnemonic Operands Opcode Operation Execution Clock Flags adr ← GR[reg1] + sign-extend (disp16) LD.W disp16[reg1], r r r r r 1 1 1 0 0 1 R R R R R Note 11 GR[reg2] ← Load-memory (adr, Word) reg2 d d d d d d d d d d d d d d d 1 Note 8...
Page 681 APPENDIX C INSTRUCTION SET LIST (4/5) Mnemonic Operands Opcode Operation Execution Clock Flags RETI if PSW.EP = 1 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 ← EIPC then PC 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 PSW ←...
Page 682 APPENDIX C INSTRUCTION SET LIST (5/5) Mnemonic Operands Opcode Operation Execution Clock Flags r r r r r 0 0 0 0 1 1 1 d d d d adr ← ep + zero-extend (disp5) SLD.HU disp5[ep], Note 9 GR[reg2] ← zero-extend (Load-memory (adr, reg2 Notes 18, 20 Halfword)
Page 683 APPENDIX C INSTRUCTION SET LIST Notes 1. dddddddd is the higher 8 bits of disp9. 4 if there is an instruction to overwrite the contents of the PSW immediately before. If there is no wait state (3 + number of read access wait states) n is the total number of load registers in list12 (According to the number of wait states.
Page 684 APPENDIX D REVISION HISTORY D.1 Major Revisions in This Edition (1/2) Page Description • Addition of the following lead-free products Throughout µ PD703114GC-xxx-8EU-A, 703114GC(A)-xxx-8EU-A,  7 03114GF-xxx-3BA-A, 70F3114GC-8EU-A, 70F3114GC(A)-8EU-A, 70F3114GF-3BA-A • Addition of FLPMC register p. 18 Addition of Note to Table 1-1 Differences Between V850E/IA1 and V850E/IA2 p.
Page 685 APPENDIX D REVISION HISTORY (2/2) Page Description p. 337 Addition of 9.3.4 (6) (a) Caution for PWM output change timing p. 410 Addition of Remark to Figure 10-2 Asynchronous Serial Interface 0 Block Diagram p. 414 Deletion of a part of description and addition of Caution to 10.2.3 (2) Asynchronous serial interface status register 0 (ASIS0) p.
Page 686 APPENDIX D REVISION HISTORY D.2 Revision History up to Previous Edition The following table shows the revision history up to the previous edition. The “Applied to:” column indicates the chapters of each edition in which the revision was applied. (1/7) Edition Major Revision up to Previous Edition Applied to:...
Page 687 APPENDIX D REVISION HISTORY (2/7) Edition Major Revision up to Previous Edition Applied to: Addition of generating source of CC10IC1 register in Table 7-1 Interrupt/Exception Source CHAPTER 7 List INTERRUPT/ EXCEPTION Change of description in Figure 7-2 Acknowledging Non-Maskable Interrupt Request PROCESSING Addition of Caution and change of description in 7.3.8 (2) Signal edge selection register 10 FUNCTION...
Page 688 APPENDIX D REVISION HISTORY (3/7) Edition Major Revision up to Previous Edition Applied to: Modification of description in 9.3.4 (1) Timer 1/timer 2 clock selection register (PRM02) CHAPTER 9 TIMER/COUNTER Modification of description in 9.3.4 (2) Timer 2 clock stop register 0 (STOPTE0) FUNCTION (REAL- Addition of Caution and modification in 9.3.4 (5) Timer 2 time base control register 0 (TCRE0) TIME PULSE UNIT)
Page 689 APPENDIX D REVISION HISTORY (4/7) Edition Major Revision up to Previous Edition Applied to: Addition of Caution in 11.4 (1) A/D scan mode registers 00 and 10 (ADSCM00, ASDSCM10) CHAPTER 11 A/D CONVERTER Change of description on bits that can be manipulated and change of explanation of FR2 to FR0 bits in 11.4 (2) A/D scan mode registers 01 and 11 (ADSCM01, ADSCM11) Addition of 11.11.6 Timing that makes the A/D conversion result undefined Addition of 11.12 How to Read A/D Converter Characteristics Table...
Page 690 APPENDIX D REVISION HISTORY (5/7) Edition Major Revision up to Previous Edition Applied to: Addition of description and Caution to 6.3.4 DMA addressing control registers 0 to 3 CHAPTER 6 DMA (DADC0 to DADC3) FUNCTIONS (DMA CONTROLLER) Addition of description and Caution to and modification of bit description in 6.3.5 DMA channel control registers 0 to 3 (DCHC0 to DCHC3) Addition of description to 6.3.6 DMA disable status register (DDIS) Addition of description to 6.3.7 DMA restart register (DRST)
Page 691 APPENDIX D REVISION HISTORY (6/7) Edition Major Revision up to Previous Edition Applied to: • Addition of the following products Throughout µ PD703114GC(A)-×××-8EU, 70F3114GC(A)-8EU Addition of Note 2 to 1.5 Pin Configuration (Top View) CHAPTER 1 INTRODUCTION Addition of description to 6.3.1 DMA source address registers 0 to 3 (DSA0 to DSA3) CHAPTER 6 DMA FUNCTIONS (DMA Addition of Caution 2 to 6.3.1 DMA source address registers 0H to 3H (DSA0H to DSA3H)
Page 692 APPENDIX D REVISION HISTORY (7/7) Edition Major Revision up to Previous Edition Applied to: Addition of Caution to 12.3.2 (1) Operation in control mode CHAPTER 12 PORT FUNCTIONS Addition of Caution to 12.3.3 (1) Operation in control mode Addition of Caution to 12.3.4 (1) Operation in control mode Modification of description of bits 7 to 5 in 12.3.4 (2) (a) Port 3 mode register (PM3) Addition of Caution to 12.3.5 (1) Operation in control mode Addition of Note to 12.3.9 (1) Operation in control mode...

This manual is also suitable for:

Pd703114a Pd70f3114 Pd70f3114a V850 series V850e/ia1 V850e/ia2

NEC PD703114 User Manual

Chapter 1 Introduction

Chapter 2 Pin Functions

Chapter 3 Cpu Function

Chapter 4 Bus Control Function

Chapter 5 Memory Access Control Function

Chapter 6 Dma Functions (Dma Controller)

Chapter 7 Interrupt/Exception Processing Function

Chapter 8 Clock Generation Function

Chapter 9 Timer/Counter Function

Chapter 10 Serial Interface Function

Chapter 11 A/D Converter

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Summary of Contents for NEC PD703114