Page 1 Preliminary User’s Manual µ µ µ µ PD789467 Subseries 8-Bit Single-Chip Microcontrollers µ µ µ µ PD789462 µ µ µ µ PD789464 µ µ µ µ PD789466 µ µ µ µ PD789467 µ µ µ µ PD78F9468 Document No. U15552EJ1V0UD00 (1st edition) Date Published December 2001 N CP(K) ©...
Page 2 [MEMO] Preliminary User’s Manual U15552EJ1V0UD...
Page 3: Notes For Cmos Devices
Reset operation must be executed immediately after power-on for devices having reset function. FIP and EEPROM are trademarks of NEC Corporation. Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries.
Page 4 The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products may be prohibited without governmental license. To export or re-export some or all of these products from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
Page 5: Regional Information
Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: •...
Page 6 INTRODUCTION Target Readers This manual is intended for users who wish to understand the functions of the µ PD789467 Subseries and to design and develop application systems and programs using these microcontrollers. Target products: • µ PD789467 Subseries: µ PD789462, 789464, 789466, 789467, 78F9468 Purpose This manual is intended to give users an understanding of the functions described in the organization below.
Page 7 Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents Related to Devices Document Name Document No. µ PD789467 Subseries User’s Manual This manual 78K/0S Series User’s Manual Instructions U11047E Documents Related to Development Tools (Software) (User’s Manuals) Document Name...
Page 8 Document No. SEMICONDUCTOR SELECTION GUIDE Products & Packages (CD-ROM) X13769E Semiconductor Device Mounting Technology Manual C10535E Quality Grades on NEC Semiconductor Devices C11531E NEC Semiconductor Device Reliability/Quality Control System C10983E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E Caution The related documents listed above are subject to change without notice.
Page 9: Table Of Contents
CONTENTS CHAPTER 1 GENERAL........................... 20 Features ............................20 Applications..........................20 Ordering Information ......................... 21 Pin Configuration (Top View)....................22 78K/0S Series Lineup......................... 24 Block Diagram ..........................27 Overview of Functions ......................28 CHAPTER 2 PIN FUNCTIONS ....................... 30 List of Pin Functions ......................... 30 Description of Pin Functions ....................
Page 10 3.3.2 Immediate addressing........................56 3.3.3 Table indirect addressing......................57 3.3.4 Register addressing ........................57 Operand Address Addressing ....................58 3.4.1 Direct addressing .......................... 58 3.4.2 Short direct addressing ......................... 59 3.4.3 Special function register (SFR) addressing .................. 60 3.4.4 Register addressing ........................61 3.4.5 Register indirect addressing ......................
Page 11 Operation of 8-Bit Timers 30 and 40 ..................96 6.4.1 Operation as 8-bit timer counter ....................96 6.4.2 Operation as 16-bit timer counter ....................103 6.4.3 Operation as carrier generator....................107 6.4.4 Operation as PWM output (timer 40 only)................... 111 Notes on Using 8-Bit Timers 30 and 40 .................
Page 12 CHAPTER 11 POWER-ON-CLEAR CIRCUIT..................151 11.1 Functions of Power-on-Clear Circuit..................151 11.2 Configuration of Power-on-Clear Circuit ................151 11.3 Power-on-Clear Circuit Operation ..................152 CHAPTER 12 INTERRUPT FUNCTION ....................153 12.1 Interrupt Types .........................153 12.2 Interrupt Sources and Configuration ..................153 12.3 Registers Controlling Interrupt Function................156 12.4 Interrupt Servicing Operation ....................160 12.4.1 Non-maskable interrupt request acknowledgment operation............
Page 13 CHAPTER 19 PACKAGE DRAWING....................208 CHAPTER 20 RECOMMENDED SOLDERING CONDITIONS ............209 APPENDIX A DEVELOPMENT TOOLS....................210 Software Package ........................212 Language Processing Software ..................... 212 Control Software ........................213 Flash Memory Writing Tools ....................214 Debugging Tools (Hardware)....................214 Debugging Tools (Software) ....................
Page 14 LIST OF FIGURES (1/4) Figure No. Title Page I/O Circuit Types............................35 Memory Map ( µ PD789462) ...........................37 Memory Map ( µ PD789464) ...........................38 Memory Map ( µ PD789466) ...........................39 Memory Map ( µ PD789467) ...........................40 Memory Map ( µ PD78F9468) .........................41 Data Memory Addressing ( µ...
Page 15 LIST OF FIGURES (2/4) Figure No. Title Page Block Diagram of Timer 30 ..........................88 Block Diagram of Timer 40 ..........................89 Block Diagram of Output Controller (Timer 40) ..................... 90 Format of 8-Bit Timer Mode Control Register 30................... 93 Format of 8-Bit Timer Mode Control Register 40...................
Page 16 LIST OF FIGURES (3/4) Figure No. Title Page How to Reduce Current Consumption in Standby Mode ................133 Conversion Result Readout Timing (When Conversion Result Is Undefined Value) ........134 Conversion Result Readout Timing (When Conversion Result Is Normal Value) ........134 9-10 Analog Input Pin Treatment .........................135 9-11 A/D Conversion End Interrupt Request Generation Timing.................136...
Page 17 LIST OF FIGURES (4/4) Figure No. Title Page 13-2 Releasing HALT Mode by Interrupt ......................169 13-3 Releasing HALT Mode by RESET Input...................... 170 13-4 Releasing STOP Mode by Interrupt......................172 13-5 Releasing STOP Mode by RESET Input ..................... 173 14-1 Block Diagram of Reset Function ........................
Page 18: List Of Tables
LIST OF TABLES (1/2) Table No. Title Page Types of Pin I/O Circuits and Recommended Connection of Unused Pins ...........35 Internal ROM Capacity ..........................42 Vector Table ..............................42 Special Function Registers..........................54 Port Functions ...............................64 Configuration of Port............................65 Port Mode Registers and Output Latch Settings When Using Alternate Functions........72 Configuration of Clock Generator ........................75 Maximum Time Required for Switching CPU Clock..................84 Operation Modes ............................86...
Page 19 LIST OF TABLES (2/2) Table No. Title Page 10-7 Output Voltages of V to V Pins ......................150 12-1 Interrupt Source List ............................ 154 12-2 Flags Corresponding to Interrupt Request Signal Name................156 12-3 Time from Generation of Maskable Interrupt Request to Servicing............. 162 13-1 Operation Statuses in HALT Mode......................
Page 20: Chapter 1 General
CHAPTER 1 GENERAL 1.1 Features • ROM and RAM capacities Item Program Memory Data Memory (ROM) Internal High-Speed LCD Display RAM Part Number µ PD789462 23 × 4 bits Mask ROM 4 KB 256 bytes µ PD789464 8 KB µ PD789466 Note 16 KB 512 bytes...
Page 21: Ordering Information
CHAPTER 1 GENERAL 1.3 Ordering Information Part Number Package Internal ROM µ PD789462GB-×××-8ET 52-pin plastic LQFP (10 × 10) Mask ROM µ PD789464GB-×××-8ET 52-pin plastic LQFP (10 × 10) Mask ROM µ PD789466GB-×××-8ET Note 52-pin plastic LQFP (10 × 10) Mask ROM µ...
Page 22: Pin Configuration (Top View)
CHAPTER 1 GENERAL 1.4 Pin Configuration (Top View) 52-pin plastic LQFP (10 × × × × 10) µ PD789462GB-×××-8ET µ PD789464GB-×××-8ET µ PD789466GB-×××-8ET Note µ PD789467GB-×××-8ET µ PD78F9468GB-8ET Note Note Under development 52 51 50 49 48 47 46 45 44 43 42 41 40 RESET P81/S21...
Page 23 CHAPTER 1 GENERAL ANI0: Analog input RESET: Reset CAPH, CAPL: LCD power supply capacitance S0 to S22: Segment output control TO40: Timer output COM0 to COM3: Common output Power supply IC0: Internally connected to V Power supply for LCD INTP0: Interrupt from peripherals Programming power supply KR00 to KR03:...
Page 24: 0S Series Lineup
CHAPTER 1 GENERAL 1.5 78K/0S Series Lineup The products in the 78K/0S Series are listed below. The names enclosed in boxes are subseries names. Products in mass production Products under development Y Subseries products support SMB. Small-scale package, general-purpose applications µ...
Page 25 CHAPTER 1 GENERAL The major functional differences among the subseries are listed below. Subseries for general-purpose applications and LCD drive Timer Function 8-Bit 10-Bit Serial Capacity Remark MIN. Interface 8-Bit 16-Bit Watch WDT (Byte) Subseries Name Value − − − µ...
Page 26 CHAPTER 1 GENERAL Subseries of ASSP Function Timer 8-Bit 10-Bit Serial Capacity Remark MIN. Interface 8-Bit 16-Bit Watch WDT (Byte) Subseries Name Value µ PD789803 8 K to 16 K − − − − − 2 ch 1 ch 2 ch 3.6 V (USB: 1 ch) µ...
Page 27: Block Diagram
CHAPTER 1 GENERAL 1.6 Block Diagram P00 to P03 Port 0 8-bit Cascaded timer 30 16-bit 8-bit timer TO40/P60 timer 40 Port 1 P10, P11 Port 4 P40 to P43 Watch timer 78K/0S (Flash CPU core Port 6 P60, P61 memory) Watchdog timer P80 to P85...
Page 28: Overview Of Functions
CHAPTER 1 GENERAL 1.7 Overview of Functions µ PD789462 µ PD789464 µ PD789466 µ PD789467 µ PD78F9468 Note 1 Note 1 Part Number Item Internal memory Mask ROM Flash memory 4 KB 8 KB 16 KB 24 KB 32 KB High-speed RAM 256 bytes 512 bytes...
Page 29 CHAPTER 1 GENERAL An outline of the timer is shown below. 8-Bit Timer 30 8-Bit Timer 40 Watch Timer Watchdog Timer Note 1 Note 2 Operation Interval timer 1 channel 1 channel 1 channel 1 channel mode External event counter –...
Page 30: Chapter 2 Pin Functions
CHAPTER 2 PIN FUNCTIONS 2.1 List of Pin Functions Port pins Pin Name Function After Reset Alternate Function − P00 to P03 Port 0. Input This is a 4-bit I/O port. Input/output can be specified in 1-bit units. When used as an input port, the use of on-chip pull-up resistors can be specified in port units using pull-up resistor option register 0 (PU0).
Page 31: Non-Port Pins
CHAPTER 2 PIN FUNCTIONS Non-port pins Pin Name Function After Reset Alternate Function INTP0 Input External interrupt input for which the valid edge (rising edge, Input P61/ANI0 falling edge, or both rising and falling edges) can be specified. KR00 to KR03 Input Key return signal detection Input...
Page 32: Description Of Pin Functions
CHAPTER 2 PIN FUNCTIONS 2.2 Description of Pin Functions 2.2.1 P00 to P03 (Port 0) These pins constitute a 4-bit I/O port and can be set in the input or output port mode in 1-bit units using port mode register 0 (PM0). When used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 0 (PU0) in port units.
Page 33: P80 To P85 (Port 8)
CHAPTER 2 PIN FUNCTIONS 2.2.5 P80 to P85 (Port 8) These pins constitute a 6-bit input port. In addition, they also function as LCD controller/driver segment signal outputs. Port 8 can be specified in the following operation modes in 1-bit units by port function register 8 (PF8). Port mode In this mode, port 8 functions as a 6-bit input port.
Page 34: Vpp
CHAPTER 2 PIN FUNCTIONS ( µ µ µ µ PD78F9468 only) 2.2.15 V A high voltage should be applied to this pin when the flash memory programming mode is set and when the program is written or verified. Perform either of the following. •...
Page 35: Pin I/O Circuits And Recommended Connection Of Unused Pins
CHAPTER 2 PIN FUNCTIONS 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins The I/O circuit type of each pin and recommended connection of unused pins are shown in Table 2-1. For the I/O circuit configuration of each type, see Figure 2-1. Table 2-1.
Page 36 CHAPTER 2 PIN FUNCTIONS Figure 2-1. I/O Circuit Types (2/2) Type 5-A Type 8-A Pull-up Pull-up P-ch P-ch enable enable Data P-ch Data P-ch IN/OUT IN/OUT Output N-ch Output disable N-ch disable Input enable Type 17-D Type 17-O IN/OUT Input enable P-ch P-ch...
Page 37: Chapter 3 Cpu Architecture
CHAPTER 3 CPU ARCHITECTURE 3.1 Memory Space The µ PD78467 Subseries can access 64 KB of memory space. Figures 3-1 through 3-5 show the memory maps. Figure 3-1. Memory Map ( µ µ µ µ PD789462) FFFFH Special function registers 256 ×...
Page 38 CHAPTER 3 CPU ARCHITECTURE Figure 3-2. Memory Map ( µ µ µ µ PD789464) FFFFH Special function registers 256 × 8 bits FF00H FEFFH Internal high-speed RAM 256 × 8 bits FE00H FDFFH Reserved FA17H FA16H LCD display RAM 23 × 4 bits Data FA00H memory space...
Page 39 CHAPTER 3 CPU ARCHITECTURE Figure 3-3. Memory Map ( µ µ µ µ PD789466) FFFFH Special function registers 256 × 8 bits FF00H FEFFH Internal high-speed RAM 512 × 8 bits FD00H FCFFH Reserved FA17H FA16H LCD display RAM 23 × 4 bits Data FA00H memory space...
Page 40 CHAPTER 3 CPU ARCHITECTURE Figure 3-4. Memory Map ( µ µ µ µ PD789467) FFFFH Special function registers 256 × 8 bits FF00H FEFFH Internal high-speed RAM 512 × 8 bits FD00H FCFFH Reserved FA17H FA16H LCD display RAM 23 × 4 bits Data FA00H memory space...
Page 41 CHAPTER 3 CPU ARCHITECTURE Figure 3-5. Memory Map ( µ µ µ µ PD78F9468) FFFFH Special function registers 256 × 8 bits FF00H FEFFH Internal high-speed RAM 512 × 8 bits FD00H FCFFH Reserved FA17H FA16H LCD display RAM 23 × 4 bits Data FA00H memory space...
Page 42: Internal Program Memory Space
CHAPTER 3 CPU ARCHITECTURE 3.1.1 Internal program memory space The internal program memory space stores programs and table data. This space is usually addressed by the program counter (PC). The µ PD789467 Subseries provides internal ROM (or flash memory) with the following capacity for each product. Table 3-1.
Page 43: Internal Data Memory (Internal High-Speed Ram) Space
CHAPTER 3 CPU ARCHITECTURE 3.1.2 Internal data memory (internal high-speed RAM) space µ PD789467 Subseries products incorporate the following RAM. Internal high-speed RAM Internal high-speed RAM is incorporated in the area between FE00H and FEFFH in the µ PD789462 and 789464, and in the area between FD00H and FEFFH in the µ...
Page 44: Data Memory Addressing
CHAPTER 3 CPU ARCHITECTURE 3.1.4 Data memory addressing The µ PD789467 Subseries is provided with a variety of addressing modes to make memory manipulation as efficient as possible. At the addresses corresponding to data memory area especially, specific addressing modes that correspond to the particular function an area, such as the special function registers, are available.
Page 45 CHAPTER 3 CPU ARCHITECTURE Figure 3-7. Data Memory Addressing ( µ µ µ µ PD789464) FFFFH Special function registers (SFRs) SFR addressing 256 × 8 bits FF20H FF1FH FF00H FEFFH Short direct Internal high-speed RAM addressing 256 × 8 bits FE20H FE1FH Direct addressing...
Page 46 CHAPTER 3 CPU ARCHITECTURE Figure 3-8. Data Memory Addressing ( µ µ µ µ PD789466) FFFFH Special function registers (SFRs) SFR addressing 256 × 8 bits FF20H FF1FH FF00H FEFFH Short direct Internal high-speed RAM addressing 512 × 8 bits FE20H Direct addressing FE1FH...
Page 47 CHAPTER 3 CPU ARCHITECTURE Figure 3-9. Data Memory Addressing ( µ µ µ µ PD789467) FFFFH Special function registers (SFRs) SFR addressing 256 × 8 bits FF20H FF1FH FF00H FEFFH Short direct Internal high-speed RAM addressing 512 × 8 bits FE20H Direct addressing FE1FH...
Page 48 CHAPTER 3 CPU ARCHITECTURE Figure 3-10. Data Memory Addressing ( µ µ µ µ PD78F9468) FFFFH Special function registers (SFRs) SFR addressing 256 × 8 bits FF20H FF1FH FF00H FEFFH Short direct Internal high-speed RAM addressing 512 × 8 bits FE20H Direct addressing FE1FH...
Page 49: Processor Registers
CHAPTER 3 CPU ARCHITECTURE 3.2 Processor Registers The µ PD789467 Subseries provides the following on-chip processor registers. 3.2.1 Control registers The control registers contain special functions to control the program sequence statuses and stack memory. The program counter, program status word, and stack pointer are control registers. Program counter (PC) The program counter is a 16-bit register that holds the address information of the next program to be executed.
Page 50 CHAPTER 3 CPU ARCHITECTURE Interrupt enable flag (IE) This flag controls interrupt request acknowledgement operations of the CPU. When 0, IE is set to the interrupt disabled status (DI), and interrupt requests other than non-maskable interrupt are all disabled. When 1, IE is set to the interrupt enabled status (EI). Interrupt request acknowledgement enable is controlled with an interrupt mask flag corresponding to various interrupt sources.
Page 51 CHAPTER 3 CPU ARCHITECTURE Stack pointer (SP) This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed RAM area can be set as the stack area. Figure 3-13. Stack Pointer Configuration SP15 SP14 SP13 SP12 SP11 SP10...
Page 52: General-Purpose Registers
CHAPTER 3 CPU ARCHITECTURE 3.2.2 General-purpose registers The general-purpose registers consist of eight 8-bit registers (X, A, C, B, E, D, L, and H). Each register can be used as an 8-bit register, or two 8-bit registers in pairs can be used as a 16-bit register (AX, BC, DE, and HL).
Page 53: Special Function Registers (Sfrs)
CHAPTER 3 CPU ARCHITECTURE 3.2.3 Special function registers (SFRs) Unlike a general-purpose register, each special function register has a special function. The special function registers are allocated in the 256-byte area of FF00H to FFFFH. Special function registers can be manipulated, like general-purpose registers, by operation, transfer, and bit manipulation instructions.
Page 54 CHAPTER 3 CPU ARCHITECTURE Table 3-3. Special Function Registers Address Special Function Register (SFR) Name Symbol Bit Unit for Manipulation After Reset 1 Bit 8 Bits 16 Bits √ √ − FF00H Port 0 √ √ − FF01H Port 1 √...
Page 55: Instruction Address Addressing
CHAPTER 3 CPU ARCHITECTURE 3.3 Instruction Address Addressing An instruction address is determined by the program counter (PC) contents. The PC contents are normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed.
Page 56: Immediate Addressing
CHAPTER 3 CPU ARCHITECTURE 3.3.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16 or BR !addr16 instruction is executed. CALL !addr16 and BR !addr16 instructions can be branched to any location in the memory space. [Illustration] In case of CALL !addr16 and BR !addr16 instructions CALL or BR...
Page 57: Register Addressing
CHAPTER 3 CPU ARCHITECTURE 3.3.3 Table indirect addressing [Function] Table contents (branch destination address) of the particular location to be addressed by the lower 5-bit immediate data of an instruction code from bit 1 to bit 5 are transferred to the program counter (PC) and branched.
Page 58: Operand Address Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4 Operand Address Addressing The following methods are available to specify the register and memory (addressing) to undergo manipulation during instruction execution. 3.4.1 Direct addressing [Function] The memory indicated with immediate data in an instruction word is directly addressed. [Operand format] Identifier Description...
Page 59: Short Direct Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.2 Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. The fixed space is the 256-byte space FE20H to FF1FH where the addressing is applied. Internal high-speed RAM and special function registers (SFRs) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively.
Page 60: Special Function Register (Sfr) Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.3 Special function register (SFR) addressing [Function] The memory-mapped special function registers (SFRs) are addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 256-byte space FF00H to FFFFH. However, the SFRs mapped at FF00H to FF1FH can also be accessed with short direct addressing.
Page 61: Register Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.4 Register addressing [Function] In the register addressing mode, general-purpose registers are accessed as operands. The general-purpose register to be accessed is specified by a register specification code or functional name in the instruction code. Register addressing is carried out when an instruction with the following operand format is executed. When an 8-bit register is specified, one of the eight registers is specified with 3 bits in the instruction code.
Page 62: Register Indirect Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.5 Register indirect addressing [Function] In the register indirect addressing mode, memory is manipulated according to the contents of a register pair specified as an operand. The register pair to be accessed is specified by the register pair specification code in an instruction code.
Page 63: Based Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.6 Based addressing [Function] 8-bit immediate data is added to the contents of the base register, that is, the HL register pair, and the sum is used to address the memory. Addition is performed by expanding the offset data as a positive number to 16 bits.
Page 64: Chapter 4 Port Functions
CHAPTER 4 PORT FUNCTIONS 4.1 Port Functions The µ PD789467 Subseries provides the ports shown in Figure 4-1, enabling various methods of control. Numerous other functions are provided that can be used in addition to the digital I/O port functions. For more information on these additional functions, see CHAPTER 2 PIN FUNCTIONS.
Page 65: Port Configuration
CHAPTER 4 PORT FUNCTIONS 4.2 Port Configuration The ports include the following hardware. Table 4-2. Configuration of Port Item Configuration Control registers Port mode registers (PMm: m = 0, 1, 4, 6) Pull-up resistor option register 0 (PU0) Port function register 8 (PF8) Ports Total: 18 (CMOS I/O: 12, CMOS input: 6 (including pins shared with LCD) Pull-up resistors...
Page 66: Port 1
CHAPTER 4 PORT FUNCTIONS 4.2.2 Port 1 This is a 2-bit I/O port with an output latch. Port 1 can be specified in the input or output mode in 1-bit units using port mode register 1 (PM1). When using the P10 and P11 pins as input port pins, on-chip pull-up resistors can be connected in 2-bit units using pull-up resistor option register 0 (PU0).
Page 67: Port 4
CHAPTER 4 PORT FUNCTIONS 4.2.3 Port 4 This is a 4-bit I/O port with an output latch. Port 4 can be specified in the input or output mode in 1-bit units using port mode register 4 (PM4). When using the P40 to P43 pins as input port pins, on-chip pull-up resistors can be connected in 4-bit units using pull-up resistor option register 0 (PU0).
Page 68: Port 6
CHAPTER 4 PORT FUNCTIONS 4.2.4 Port 6 This is a 2-bit I/O port with an output latch. Port 6 can be specified in the input or output mode in 1-bit units using port mode register 6 (PM6). This port is also used as a timer output, external interrupt input, and analog input. This port is set in the input mode when the RESET signal is input.
Page 69 CHAPTER 4 PORT FUNCTIONS Figure 4-6. Block Diagram of P61 A/D converter – ADS0 ADS00 External interrupt PORT Output latch P61/INTP0/ANI0 (P61) PM61 ADS0: A/D input selection register 0 Port mode register Port 6 read signal Port 6 write signal Preliminary User’s Manual U15552EJ1V0UD...
Page 70: Port 8
CHAPTER 4 PORT FUNCTIONS 4.2.5 Port 8 This is a 6-bit input port. This port is also used as a segment output, and can be switched to the port function or segment output function in 1-bit units using port function register 8 (PF8). This port is set in the input mode when the RESET signal is input.
Page 71: Registers Controlling Port Function
CHAPTER 4 PORT FUNCTIONS 4.3 Registers Controlling Port Function The ports are controlled by the following three types of registers. • Port mode registers (PM0, PM1, PM4, PM6) • Pull-up resistor option register 0 (PU0) • Port function register 8 (PF8) Port mode registers (PM0, PM1, PM4, PM6) These registers are used to set port input/output in 1-bit units.
Page 72 CHAPTER 4 PORT FUNCTIONS Table 4-3. Port Mode Registers and Output Latch Settings When Using Alternate Functions Pin Name Alternate Function PM×× PM×× ADS00 Name × × P40 to P43 KR00 to KR03 Input × TO40 Output × INTP0 Input ×...
Page 73 CHAPTER 4 PORT FUNCTIONS Port function register 8 (PF8) Port function register 8 (PF8) sets the port function of port 8 in 1-bit units. The pins of port 8 are selected as either LCD segment signal outputs or general-purpose port pins according to the setting of PF8.
Page 74: Port Function Operation
CHAPTER 4 PORT FUNCTIONS 4.4 Port Function Operation The operation of a port differs depending on whether the port is set in the input or output mode, as described below. 4.4.1 Writing to I/O port In output mode A value can be written to the output latch of a port by using a transfer instruction. The contents of the output latch can be output from the pins of the port.
Page 75: Chapter 5 Clock Generator
CHAPTER 5 CLOCK GENERATOR 5.1 Clock Generator Functions The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following two types of system clock oscillators are used. • • • • Main system clock (ceramic/crystal) oscillator This circuit oscillates at 1.0 to 5.0 MHz.
Page 76 CHAPTER 5 CLOCK GENERATOR Figure 5-1. Block Diagram of Clock Generator Internal bus FRC SCC Suboscillation mode register (SCKM) Subsystem clock Watch timer oscillator LCD controller/driver Main system Clock to peripheral Prescaler clock hardware oscillator CPU clock Standby Wait controller controller STOP CLS CSS0...
Page 77: Registers Controlling Clock Generator
CHAPTER 5 CLOCK GENERATOR 5.3 Registers Controlling Clock Generator The clock generator is controlled by the following three registers. • Processor clock control register (PCC) • Suboscillation mode register (SCKM) • Subclock control register (CSS) Processor clock control register (PCC) PCC sets CPU clock selection and the division ratio.
Page 78 CHAPTER 5 CLOCK GENERATOR Suboscillation mode register (SCKM) SCKM selects a feedback resistor for the subsystem clock, and controls the oscillation of the clock. SCKM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets SCKM to 00H. Figure 5-3.
Page 79: System Clock Oscillators
CHAPTER 5 CLOCK GENERATOR 5.4 System Clock Oscillators 5.4.1 Main system clock oscillator The main system clock oscillator is oscillated by the crystal or ceramic resonator (5.0 MHz TYP.) connected across the X1 and X2 pins. An external clock can also be input to the circuit. In this case, input the clock signal to the X1 pin, and input the inverted signal to the X2 pin.
Page 80: Subsystem Clock Oscillator
CHAPTER 5 CLOCK GENERATOR 5.4.2 Subsystem clock oscillator The subsystem clock oscillator is oscillated by the crystal resonator (32.768 kHz TYP.) connected across the XT1 and XT2 pins. An external clock can also be input to the circuit. In this case, input the clock signal to the XT1 pin, and input the inverted signal to the XT2 pin.
Page 81 CHAPTER 5 CLOCK GENERATOR Figure 5-7. Examples of Incorrect Resonator Connection (1/2) (a) Too long wiring (b) Crossed signal line PORTn (n = 0, 1, 4, 6, 8) (c) Wiring near high fluctuating current (d) Current flowing through ground line of oscillator (potential at points A, B, and C fluctuates) High current High current...
Page 82: Divider Circuit
CHAPTER 5 CLOCK GENERATOR Figure 5-7. Examples of Incorrect Resonator Connection (2/2) (e) Signal is fetched (f) Parallel and near signal lines of main system clock and subsystem clock XT2 is wired parallel to X1. Remark When using the subsystem clock, read X1 and X2 as XT1 and XT2, respectively, and connect a resistor to the XT2 in series.
Page 83: Clock Generator Operation
CHAPTER 5 CLOCK GENERATOR 5.5 Clock Generator Operation The clock generator generates the following clocks and controls the operation modes of the CPU, such as the standby mode. • Main system clock • Subsystem clock • CPU clock • Clock to peripheral hardware The operation and function of the clock generator is determined by the processor clock control register (PCC), suboscillation mode register (SCKM), and subclock control register (CSS), as follows.
Page 84: Changing Setting Of System Clock And Cpu Clock
CHAPTER 5 CLOCK GENERATOR 5.6 Changing Setting of System Clock and CPU Clock 5.6.1 Time required for switching between system clock and CPU clock The CPU clock can be selected by using bit 1 (PCC1) of the processor clock control register (PCC) and bit 4 (CSS0) of the subclock control register (CSS).
Page 85: Switching Between System Clock And Cpu Clock
CHAPTER 5 CLOCK GENERATOR 5.6.2 Switching between system clock and CPU clock The following figure illustrates how the CPU clock and system clock switch. Figure 5-8. Example of Switching Between System Clock and CPU Clock RESET Input request signal rewrite rewrite rewrite System clock...
Page 86: Chapter 6 8-Bit Timers 30 And 40
CHAPTER 6 8-BIT TIMERS 30 AND 40 6.1 Functions of 8-Bit Timers 30 and 40 The 8-bit timer in the µ PD789467 Subseries has 2 channels (timer 30 and timer 40). The operation modes listed in the following table can be set via mode register settings. Table 6-1.
Page 87: Configuration Of 8-Bit Timers 30 And 40
CHAPTER 6 8-BIT TIMERS 30 AND 40 6.2 Configuration of 8-Bit Timers 30 and 40 The 8-bit timers 30 and 40 include the following hardware. Table 6-2. Configuration of 8-Bit Timers 30 and 40 Item Configuration 8 bits × 2 (TM30, TM40) Timer counters Compare registers: 8 bits ×...
Page 88 Figure 6-1. Block Diagram of Timer 30 Internal bus 8-bit timer mode control register 30 (TMC30) TCE30 TCL301 TCL300 TMD300 8-bit compare register 30 Decoder (CR30) Selector To Figure 6-2 (G) Match Timer 30 match signal Bit 7 of TM40 (in carrier generator mode) (from Figure 6-2 (A)) 8-bit timer counter 30...
Page 89 Figure 6-2. Block Diagram of Timer 40 Internal bus Carrier generator output 8-bit timer mode control control register 40 (TCA40) register 40 (TMC40) 8-bit compare 8-bit H width compare TCE40 TCL402 TCL401 TCL400 TMD401 TMD400 TOE40 register 40 (CR40) RMC40 NRZB40 NRZ40 register 40 (CRH40) Decoder From Figure 6-1 (G)
Page 90 CHAPTER 6 8-BIT TIMERS 30 AND 40 Figure 6-3. Block Diagram of Output Controller (Timer 40) TOE40 RMC40 NRZ40 output latch PM60 TO40/P60 Carrier clock (in carrier generator mode) or timer 40 output signal (in other than carrier generator mode) Carrier generator mode (1) 8-bit compare register 30 (CR30) This 8-bit register is used to continually compare the value set to CR30 with the count value in 8-bit timer...
Page 91 CHAPTER 6 8-BIT TIMERS 30 AND 40 (4) 8-bit timer counters 30 and 40 (TM30 and TM40) These are 8-bit registers that are used to count the count pulse. TM30 and TM40 are read with an 8-bit memory manipulation instruction. RESET input sets TM30 and TM40 to 00H.
Page 92: Registers Controlling 8-Bit Timers 30 And 40
CHAPTER 6 8-BIT TIMERS 30 AND 40 6.3 Registers Controlling 8-Bit Timers 30 and 40 The 8-bit timer 30 and 40 are controlled by the following four registers. • 8-bit timer mode control register 30 (TMC30) • 8-bit timer mode control register 40 (TMC40) •...
Page 93 CHAPTER 6 8-BIT TIMERS 30 AND 40 (1) 8-bit timer mode control register 30 (TMC30) 8-bit timer mode control register 30 (TMC30) is used to control the timer 30 count clock setting and the operation mode setting. TMC30 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets TMC30 to 00H.
Page 94 CHAPTER 6 8-BIT TIMERS 30 AND 40 (2) 8-bit timer mode control register 40 (TMC40) 8-bit timer mode control register 40 (TMC40) is used to control the timer 40 count clock setting and the operation mode setting. TMC40 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets TMC40 to 00H.
Page 95 CHAPTER 6 8-BIT TIMERS 30 AND 40 (3) Carrier generator output control register 40 (TCA40) This register is used to set the timer output data in carrier generator mode. TCA40 is set with an 8-bit memory manipulation instruction. RESET input sets TCA40 to 00H. Figure 6-6.
Page 96: Operation Of 8-Bit Timers 30 And 40
CHAPTER 6 8-BIT TIMERS 30 AND 40 6.4 Operation of 8-Bit Timers 30 and 40 6.4.1 Operation as 8-bit timer counter Timers 30 and 40 can be independently used as 8-bit timer counters. The following modes can be used for the 8-bit timer counters. •...
Page 97 CHAPTER 6 8-BIT TIMERS 30 AND 40 Table 6-3. Interval Time of Timer 30 (at f = 5.0 MHz Operation) TCL301 TCL300 Minimum Interval Time Maximum Interval Time Resolution (12.8 µ s) (12.8 µ s) (3.28 ms) (51.2 µ s) (51.2 µ...
Page 98 CHAPTER 6 8-BIT TIMERS 30 AND 40 Figure 6-9. Timing of Interval Timer Operation with 8-Bit Resolution (When CRn0 Is Set to 00H) Count clock TMn0 CRn0 TCEn0 Count start INTTMn0 TOn0 Remark n = 3, 4 Figure 6-10. Timing of Interval Timer Operation with 8-Bit Resolution (When CRn0 Is Set to FFH) Count clock TMn0 Clear...
Page 99 CHAPTER 6 8-BIT TIMERS 30 AND 40 Figure 6-11. Timing of Interval Timer Operation with 8-Bit Resolution (When CRn0 Changes from N to M (N < < < < M)) Count clock TMn0 Clear Clear Clear CRn0 TCEn0 Count start INTTMn0 Interrupt acknowledgement Interrupt acknowledgement...
Page 100 CHAPTER 6 8-BIT TIMERS 30 AND 40 Figure 6-13. Timing of Interval Timer Operation with 8-Bit Resolution (When Timer 40 Match Signal Is Selected for Timer 30 Count Clock) Timer 40 count clock TM40 Clear Clear Clear Clear CR40 TCE40 Count start INTTM40 Input clock to timer 30...
Page 101 CHAPTER 6 8-BIT TIMERS 30 AND 40 Operation as square-wave output with 8-bit resolution (timer 40 only) Square waves of any frequency can be output at an interval specified by the value preset in 8-bit compare register 40 (CR40). To operate timer 40 for square-wave output, settings must be made in the following sequence. <1>...
Page 102 CHAPTER 6 8-BIT TIMERS 30 AND 40 Figure 6-14. Timing of Square-Wave Output with 8-Bit Resolution Count clock TM40 Clear Clear Clear CR40 TCE40 Count start INTTM40 Interrupt acknowledgement Interrupt acknowledgement Interrupt acknowledgement Note TO40 Square-wave output cycle Note The initial value of TO40 is low level when output is enabled (TOE40 = 1). Square-wave output cycle = 2 (N + 1) ×...
Page 103: Operation As 16-Bit Timer Counter
CHAPTER 6 8-BIT TIMERS 30 AND 40 6.4.2 Operation as 16-bit timer counter Timers 30 and 40 can be used as 16-bit timer counters via a cascade connection. In this case, 8-bit timer counter 30 (TM30) is the higher 8 bits and 8-bit timer counter 40 (TM40) is the lower 8 bits. 8-bit timer 40 controls reset and clear.
Page 104 Figure 6-15. Timing of Interval Timer Operation with 16-Bit Resolution Count clock TM40 count value FFH 00H 7FH 80H FFH 00H 7FH 80H FFH 00H Not cleared because TM30 does not match Cleared because TM30 and TM40 match simultaneously CR40 TCE40 Count start TM30 count pulse...
Page 105 CHAPTER 6 8-BIT TIMERS 30 AND 40 Operation as square-wave output with 16-bit resolution Square waves of any frequency can be output at an interval specified by the count value preset in CR30 and CR40. To operate as a square-wave output with 16-bit resolution, settings must be made in the following sequence. <1>...
Page 106 Figure 6-16. Timing of Square-Wave Output with 16-Bit Resolution Count clock TM40 count value FFH 00H 7FH 80H FFH 00H 7FH 80H FFH 00H Not cleared because TM30 does not match Cleared because TM30 and TM40 match simultaneously CR40 TCE40 Count start TM30 count pulse X −...
Page 107: Operation As Carrier Generator
CHAPTER 6 8-BIT TIMERS 30 AND 40 6.4.3 Operation as carrier generator An arbitrary carrier clock generated by TM40 can be output in the cycle set in TM30. To operate timers 30 and 40 as carrier generators, settings must be made in the following sequence. <1>...
Page 108 CHAPTER 6 8-BIT TIMERS 30 AND 40 Figure 6-17. Timing of Carrier Generator Operation (When CR40 = N, CRH40 = M (M > > > > N)) Count clock TM40 count value Clear Clear Clear Clear CR40 CRH40 TCE40 Count start INTTM40 Carrier clock Count pulse...
Page 109 CHAPTER 6 8-BIT TIMERS 30 AND 40 Figure 6-18. Timing of Carrier Generator Operation (When CR40 = N, CRH40 = M (M < < < < N), Phases of Carrier Clock and NRZ40 Are Asynchronous) Count clock TM40 count value Clear Clear Clear...
Page 110 CHAPTER 6 8-BIT TIMERS 30 AND 40 Figure 6-19. Timing of Carrier Generator Operation (When CR40 = CRH40 = N) Count clock TM40 count value Clear Clear Clear Clear Clear CR40 CRH40 TCE40 Count start INTTM40 Carrier clock Count pulse TM30 CR30 TCE30...
Page 111: Operation As Pwm Output (Timer 40 Only)
CHAPTER 6 8-BIT TIMERS 30 AND 40 6.4.4 Operation as PWM output (timer 40 only) In the PWM output mode, a pulse of any duty ratio can be output by setting a low-level width using CR40 and a high-level width using CRH40. To operate timer 40 in PWM output mode, settings must be made in the following sequence.
Page 112 CHAPTER 6 8-BIT TIMERS 30 AND 40 Figure 6-20. PWM Output Mode Timing (Basic Operation) Count clock TM40 count value Clear Clear Clear Clear CR40 CRH40 TCE40 Count start INTTM40 Note TO40 Note The initial value of TO40 is low level when output is enabled (TOE40 = 1). Figure 6-21.
Page 113: Notes On Using 8-Bit Timers 30 And 40
CHAPTER 6 8-BIT TIMERS 30 AND 40 6.5 Notes on Using 8-Bit Timers 30 and 40 Error on starting timer An error of up to 1 clock is included in the time between when the timer is started and a match signal is generated.
Page 114: Chapter 7 Watch Timer
CHAPTER 7 WATCH TIMER 7.1 Watch Timer Functions The watch timer has the following functions. • Watch timer • Interval timer The watch and interval timers can be used at the same time. Figure 7-1 shows a block diagram of the watch timer. Figure 7-1.
Page 115: Watch Timer Configuration
CHAPTER 7 WATCH TIMER Watch timer The 4.19 MHz main system clock or 32.768 kHz subsystem clock is used to generate an interrupt request (INTWT) at 0.5-second intervals. Caution When the main system clock is operating at 5.0 MHz, it cannot be used to generate a 0.5- second interval.
Page 116: Register Controlling Watch Timer
CHAPTER 7 WATCH TIMER 7.3 Register Controlling Watch Timer The watch timer mode control register (WTM) is used to control the watch timer. • Watch timer mode control register (WTM) WTM selects a count clock for the watch timer and specifies whether to enable operation of the timer. It also specifies the prescaler interval and how the 5-bit counter is controlled.
Page 117: Watch Timer Operation
CHAPTER 7 WATCH TIMER 7.4 Watch Timer Operation 7.4.1 Operation as watch timer The watch timer is used to generate an interrupt request at 0.5-second interval using the main system clock (4.19 MHz) or subsystem clock (32.768 kHz). By setting bits 0 and 1 (WTM0 and WTM1) of the watch timer mode control register (WTM) to 1, the watch timer starts counting.
Page 118 CHAPTER 7 WATCH TIMER Figure 7-3. Watch Timer/Interval Timer Operation Timing 5-bit counter Overflow Overflow Start Count clock Watch timer interrupt INTWT Watch timer interrupt time (0.5 s) Watch timer interrupt time (0.5 s) Interval timer interrupt INTWTI Interval timer (T) Caution When operation of the watch timer and 5-bit counter has been enabled by setting the watch timer mode control register (WTM) (setting WTM0 (bit 0 of WTM) to 1), the time until the first interrupt request after this setting will not be exactly the same as the time set by WTM3 (bit 3 of...
Page 119: Chapter 8 Watchdog Timer
CHAPTER 8 WATCHDOG TIMER 8.1 Watchdog Timer Functions The watchdog timer has the following functions. • Watchdog timer • Interval timer Caution Select either the watchdog timer mode or interval timer mode using the watchdog timer mode register (WDTM). Watchdog timer The watchdog timer is used to detect inadvertent program loop.
Page 120: Watchdog Timer Configuration
CHAPTER 8 WATCHDOG TIMER 8.2 Watchdog Timer Configuration The watchdog timer includes the following hardware. Table 8-3. Configuration of Watchdog Timer Item Configuration Control registers Watchdog timer clock selection register (TCL2) Watchdog timer mode register (WDTM) Figure 8-1. Block Diagram of Watchdog Timer Internal bus WDTMK Prescaler...
Page 121: Registers Controlling Watchdog Timer
CHAPTER 8 WATCHDOG TIMER 8.3 Registers Controlling Watchdog Timer The watchdog timer is controlled by the following two registers. • Watchdog timer clock selection register (TCL2) • Watchdog timer mode register (WDTM) Watchdog timer clock selection register (TCL2) This register sets the watchdog timer count clock. TCL2 is set with an 8-bit memory manipulation instruction.
Page 122 CHAPTER 8 WATCHDOG TIMER Watchdog timer mode register (WDTM) This register sets an operation mode of the watchdog timer, and enables/disables counting of the watchdog timer. WDTM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets WDTM to 00H. Figure 8-3.
Page 123: Watchdog Timer Operation
CHAPTER 8 WATCHDOG TIMER 8.4 Watchdog Timer Operation 8.4.1 Operation as watchdog timer The watchdog timer detects an inadvertent program loop when bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 1. The count clock (inadvertent program loop detection time interval) of the watchdog timer can be selected by bits 1 and 2 (TCL21 and TCL22) of the watchdog timer clock selection register (TCL2).
Page 124: Operation As Interval Timer
CHAPTER 8 WATCHDOG TIMER 8.4.2 Operation as interval timer When bit 4 (WDTM4) and bit 3 (WDTM3) of the watchdog timer mode register (WDTM) are set to 0 and 1, respectively, the watchdog timer operates as an interval timer that repeatedly generates an interrupt at time intervals specified by a preset count value.
Page 125: Chapter 9 8-Bit A/D Converter
CHAPTER 9 8-BIT A/D CONVERTER Functions of 8-Bit A/D Converter The 8-bit A/D converter is an 8-bit resolution converter that converts analog inputs to digital signals. This converter can control one channel of analog inputs (ANI0). A/D conversion can only be started by software. A/D conversion is performed repeatedly, with an interrupt request (INTAD0) being issued each time an A/D conversion operation is completed.
Page 126 CHAPTER 9 8-BIT A/D CONVERTER Figure 9-1. Block Diagram of 8-Bit A/D Converter P-ch Sample & hold circuit Voltage comparator ANI0/INTP0/P61 Successive approximation register (SAR) Controller INTAD0 A/D conversion result register 0 (ADCR0) ADS00 ADCS0 FR02 FR01 FR00 A/D input selection A/D converter mode register 0 (ADS0) register 0 (ADM0)
Page 127 CHAPTER 9 8-BIT A/D CONVERTER Series resistor string The series resistor string is configured between V and V . It generates the reference voltages against which analog inputs are compared. ANI0 pin The ANI0 pin is the 1-channel analog input pin for the A/D converter. It is used to receive the analog signals for A/D conversion.
Page 128: Registers Controlling 8-Bit A/D Converter
CHAPTER 9 8-BIT A/D CONVERTER 9.3 Registers Controlling 8-Bit A/D Converter The following two registers are used to control the 8-bit A/D converter. • A/D converter mode register 0 (ADM0) • A/D input selection specification register 0 (ADS0) A/D converter mode register 0 (ADM0) ADM0 specifies the conversion time for analog inputs.
Page 129 CHAPTER 9 8-BIT A/D CONVERTER A/D input selection register 0 (ADS0) The ADS0 register specifies the port used to input the analog voltages to be converted to a digital signal. ADS0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears ADS0 to 00H.
Page 130: 8-Bit A/D Converter Operation
CHAPTER 9 8-BIT A/D CONVERTER 9.4 8-Bit A/D Converter Operation 9.4.1 Basic operation of 8-bit A/D converter <1> Set bit 0 of A/D input selection register 0 (ADS0) so that the P61/INTP0/ANI0 pin can be used as analog input. <2> The analog input voltage is sampled using the sample and hold circuit. <3>...
Page 131: Input Voltage And Conversion Result
CHAPTER 9 8-BIT A/D CONVERTER A/D conversion continues until bit 7 (ADCS0) of A/D converter mode register 0 (ADM0) is reset (0) by software. If an attempt is made to write to ADM0 or A/D input selection register 0 (ADS0) during A/D conversion, the A/D conversion in progress is canceled.
Page 132: Operation Mode Of 8-Bit A/D Converter
CHAPTER 9 8-BIT A/D CONVERTER 9.4.3 Operation mode of 8-bit A/D converter A/D input selection register 0 (ADS0) is used to select the function of the P61/INTP0/ANI0 pin to be used as an analog input for A/D conversion. A/D conversion can only be started by software, that is, by setting A/D converter mode register 0 (ADM0). The A/D conversion result is saved to A/D conversion result register 0 (ADCR0).
Page 133: Cautions Related To 8-Bit A/D Converter
CHAPTER 9 8-BIT A/D CONVERTER 9.5 Cautions Related to 8-Bit A/D Converter Current consumption in standby mode When the A/D converter enters a standby mode, it stops operating. Stopping conversion (bit 7 (ADCS0) of A/D converter mode register 0 (ADM0) = 0) can reduce the current consumption. Figure 9-7 shows how to reduce the current consumption in standby mode.
Page 134 CHAPTER 9 8-BIT A/D CONVERTER Conversion results immediately following start of A/D conversion The first A/D conversion value immediately following the start of A/D converter operation is undefined. Be sure to poll the A/D conversion end interrupt request (INTAD0) and perform processing such as discarding the first conversion result and using the second or later conversion result.
Page 135 CHAPTER 9 8-BIT A/D CONVERTER Noise prevention To maintain a resolution of 8 bits, watch for noise to the V and ANI0 pins. The higher the output impedance of the analog input source is, the larger the effect by noise. To reduce noise, attach an external capacitor to the relevant pins as shown in Figure 9-8.
Page 136 CHAPTER 9 8-BIT A/D CONVERTER Figure 9-11. A/D Conversion End Interrupt Request Generation Timing Rewriting to ADM0 Rewriting to ADM0 (to begin conversion (to begin conversion ADIF0 has been set, but conversion for ANI0) for ANI0) for ANI0 has not been completed. A/D conversion ANI0 ANI0...
Page 137: Chapter 10 Lcd Controller/Driver
CHAPTER 10 LCD CONTROLLER/DRIVER 10.1 Functions of LCD Controller/Driver The features of the LCD controller/driver of the µ PD789467 Subseries are as follows. Automatic output of segment and common signals based on automatic display data memory read Four different frame frequencies selectable Up to 23 segment signal outputs (S0 to S22) and four common signal outputs (COM0 to COM3) Operation with a subsystem clock A voltage booster is incorporated...
Page 138 Figure 10-1. Block Diagram of LCD Controller/Driver Internal bus LCD voltage LCD clock control LCD display mode Display data boost control register 0 memory register 0 register 0 FA00H FA11H FA16H (LCDVA0) LCDC03 LCDC02 LCDC01 LCDC00 LCDON0 VAON0 LIPS0 3 2 1 0 3 2 1 0 3 2 1 0 Port function...
Page 139: Registers Controlling Lcd Controller/Driver
CHAPTER 10 LCD CONTROLLER/DRIVER 10.3 Registers Controlling LCD Controller/Driver • LCD display mode register 0 (LCDM0) • LCD clock control register 0 (LCDC0) • LCD voltage boost control register 0 (LCDVA0) • Port function register 8 (PF8) LCD display mode register 0 (LCDM0) This register is used to enable/disable display operation, enable/disable voltage boost, and specify segment/common pin output and display mode.
Page 140 CHAPTER 10 LCD CONTROLLER/DRIVER Cautions 1. Bits 0, 1, 3, and 5 must be set to 0. 2. When the main system clock is selected as the LCD source clock, if the STOP mode is selected, an abnormal display may occur. Before selecting the STOP mode, disable display and select the static mode (LCDON0 = 0 and LCDM02 =1).
Page 141 CHAPTER 10 LCD CONTROLLER/DRIVER LCD clock control register 0 (LCDC0) LCDC0 specifies the LCD source clock and LCD clock. The frame frequency is determined by the LCD clock and the number of time divisions. LCDC0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets LCDC0 to 00H.
Page 142 CHAPTER 10 LCD CONTROLLER/DRIVER LCD voltage boost control register 0 (LCDVA0) LCDVA0 controls the voltage boost level during the voltage boost operation. LCDVA0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets LCDVA0 to 00H. Figure 10-4. Format of LCD Voltage Boost Control Register 0 Symbol <0>...
Page 143: Setting Lcd Controller/Driver
CHAPTER 10 LCD CONTROLLER/DRIVER 10.4 Setting LCD Controller/Driver Set the LCD controller/driver using the following procedure. Before changing the LCD clock or voltage boost level, disable display and voltage boost. 10.4.1 Setting before starting display <1> With the default setting after reset, select the static mode by setting bit 2 (LCDM02 = 1) of LCDM0. <2>...
Page 144: Lcd Display Data Memory
CHAPTER 10 LCD CONTROLLER/DRIVER 10.5 LCD Display Data Memory The LCD display data memory is mapped at addresses FA00H to FA16H. Data in the LCD display data memory can be displayed on the LCD panel using the LCD controller/driver. Figure 10-6 shows the relationship between the contents of the LCD display data memory and the segment/common outputs.
Page 145: Common And Segment Signals
CHAPTER 10 LCD CONTROLLER/DRIVER 10.6 Common and Segment Signals Each pixel of the LCD panel turns on when the potential difference between the corresponding common and segment signals becomes higher than a specific voltage (LCD drive voltage, V ). It turns off when the potential difference becomes lower than V Applying DC voltage to the common and segment signals for an LCD panel would deteriorate it.
Page 146 CHAPTER 10 LCD CONTROLLER/DRIVER Figure 10-7 shows the common signal waveforms, and Figure 10-8 shows the voltages and phases of the common and segment signals. Figure 10-7. Common Signal Waveforms COMn (Four-time slot mode) = 4 × T T: One LCD clock period : Frame frequency Figure 10-8.
Page 147: Display Modes
CHAPTER 10 LCD CONTROLLER/DRIVER 10.7 Display Modes 10.7.1 Four-time slot display example Figure 10-10 shows how the 11-digit LCD panel having the display pattern shown in Figure 10-9 is connected to the segment signals (S0 to S21) and the common signals (COM0 to COM3) of the µ PD789467 Subseries chip. This example displays data “23456.789012”...
Page 148 CHAPTER 10 LCD CONTROLLER/DRIVER Figure 10-10. Example of Connecting Four-Time Slot LCD Panel COM 3 COM 2 COM 1 COM 0 FA00H S 10 S 11 S 12 S 13 S 14 S 15 S 16 FA10H S 17 S 18 S 19 S 20 S 21...
Page 149 CHAPTER 10 LCD CONTROLLER/DRIVER Figure 10-11. Examples of Four-Time Slot LCD Drive Waveform COM0 COM1 COM2 COM3 +1/3V COM0-S12 −1/3V −V +1/3V COM1-S12 −1/3V −V Remark The waveforms of COM2-S12 and COM3-S12 are not shown above. Preliminary User’s Manual U15552EJ1V0UD...
Page 150: Supplying Lcd Drive Voltages
CHAPTER 10 LCD CONTROLLER/DRIVER 10.8 Supplying LCD Drive Voltages V , and V The µ PD789467 Subseries contains a booster circuit (×3 only) to generate a supply voltage to drive the LCD. The internal LCD reference voltage is output from the V pin.
Page 151: Chapter 11 Power-On-Clear Circuit
CHAPTER 11 POWER-ON-CLEAR CIRCUIT µ PD789467 Subseries provides a power-on-clear (POC) circuit. In the flash memory version ( µ PD78F9468), the POC circuit is always operating. However, it can only be used when selected by a mask option in mask ROM versions ( µ...
Page 152: Power-On-Clear Circuit Operation
CHAPTER 11 POWER-ON-CLEAR CIRCUITS 11.3 Power-on-Clear Circuit Operation The POC circuit compares the detection voltage (V ) with the power supply voltage (V ) and generates an internal reset signal if V < V Figure 11-2. Timing of Internal Reset Signal Generation of POC Circuit Power supply voltage (V Detection voltage (V 1.8 V...
Page 153: Chapter 12 Interrupt Function
CHAPTER 12 INTERRUPT FUNCTION 12.1 Interrupt Types The following two types of interrupts are used. Non-maskable interrupt This interrupt is acknowledged unconditionally. It does not undergo interrupt priority control and is given top priority over all other interrupt requests. A standby release signal is generated. One interrupt source from the watchdog timer is incorporated as a non-maskable interrupt.
Page 154 CHAPTER 12 INTERRUPT FUNCTION Table 12-1. Interrupt Source List Note 1 Interrupt Type Priority Interrupt Source Internal/ Vector Table Basic External Address Configuration Name Trigger Note 2 Type − Non- INTWDT Watchdog timer overflow (with Internal 0004H maskable watchdog timer mode 1 selected) Maskable INTWDT Watchdog timer overflow (with...
Page 155 CHAPTER 12 INTERRUPT FUNCTION Figure 12-1. Basic Configuration of Interrupt Function (A) Internal non-maskable interrupt Internal bus Vector table Interrupt request address generator Standby release signal (B) Internal maskable interrupt Internal bus Vector table address generator Interrupt request Standby release signal (C) External maskable interrupt Internal bus INTM0, KRM00...
Page 156: Registers Controlling Interrupt Function
CHAPTER 12 INTERRUPT FUNCTION 12.3 Registers Controlling Interrupt Function The following five types of registers are used to control the interrupt function. • Interrupt request flag register 0 (IF0) • Interrupt mask flag register 0 (MK0) • External interrupt mode register 0 (INTM0) •...
Page 157 CHAPTER 12 INTERRUPT FUNCTION Interrupt request flag register 0 (IF0) An interrupt request flag is set (1) when the corresponding interrupt request is generated, or when an instruction is executed. It is cleared (0) when the interrupt request is acknowledged, when the RESET signal is input, or when an instruction is executed.
Page 158 CHAPTER 12 INTERRUPT FUNCTION External interrupt mode register 0 (INTM0) INTM0 is used to specify the valid edge for INTP0. INTM0 is set with an 8-bit memory manipulation instruction. RESET input sets INTM0 to 00H. Figure 12-4. Format of External Interrupt Mode Register 0 Symbol Address After reset...
Page 159 CHAPTER 12 INTERRUPT FUNCTION Key return mode register 00 (KRM00) KRM00 sets the pin that detects a key return signal (falling edge of port 4). KRM00 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets KRM00 to 00H. Figure 12-6.
Page 160: Interrupt Servicing Operation
CHAPTER 12 INTERRUPT FUNCTION 12.4 Interrupt Servicing Operation 12.4.1 Non-maskable interrupt request acknowledgment operation The non-maskable interrupt request is unconditionally acknowledged even when interrupts are disabled. It is not subject to interrupt priority control and takes precedence over all other interrupts. When the non-maskable interrupt request is acknowledged, PSW and PC are saved to the stack in that order, the IE flag is reset to 0, the contents of the vector table are loaded to the PC, and then program execution branches.
Page 161 CHAPTER 12 INTERRUPT FUNCTION Figure 12-8. Flow from Generation of Non-Maskable Interrupt Request to Acknowledgment Start WDTM4 = 1 (watchdog timer mode is selected) Interval timer overflows WDTM3 = 0 (non-maskable interrupt is selected) Reset processing Interrupt request is generated Interrupt servicing starts WDTM: Watchdog timer mode register WDT:...
Page 162: Maskable Interrupt Request Acknowledgment Operation
CHAPTER 12 INTERRUPT FUNCTION 12.4.2 Maskable interrupt request acknowledgment operation A maskable interrupt request can be acknowledged when the interrupt request flag is set to 1 and the corresponding interrupt mask flag is cleared to 0. A vectored interrupt request is acknowledged in the interrupt enabled status (when the IE flag is set to 1).
Page 163: Multiple Interrupt Servicing
CHAPTER 12 INTERRUPT FUNCTION Figure 12-12. Interrupt Request Acknowledgment Timing (Example: MOV A, r) 8 clocks Clock Save PSW and PC, and MOV A, r Interrupt servicing program jump to interrupt servicing Interrupt If the interrupt request has generated an interrupt request flag (XXIF) by the time the instruction clocks under execution, n clocks (n = 4 to 10), are n −...
Page 164 CHAPTER 12 INTERRUPT FUNCTION Figure 12-14. Example of Multiple Interrupts Example 1. Acknowledging multiple interrupts INTxx servicing INTyy servicing Main servicing IE = 0 IE = 0 INTxx INTyy RETI RETI The interrupt request INTyy is acknowledged during the servicing of interrupt INTxx and multiple interrupt servicing is performed.
Page 165: Putting Interrupt Requests On Hold
CHAPTER 12 INTERRUPT FUNCTION 12.4.4 Putting interrupt requests on hold If an interrupt request (such as a maskable, non-maskable, or external interrupt) is generated when a certain type of instruction is being executed, the interrupt request will not be acknowledged until the instruction is completed. Such instructions (interrupt request pending instructions) are as follows.
Page 166: Chapter 13 Standby Function
CHAPTER 13 STANDBY FUNCTION 13.1 Standby Function and Configuration 13.1.1 Standby function The standby function is used to reduce the power consumption of the system and can be effected in the following two modes. HALT mode This mode is set when the HALT instruction is executed. The HALT mode stops the operation clock of the CPU.
Page 167: Register Controlling Standby Function
CHAPTER 13 STANDBY FUNCTION 13.1.2 Register controlling standby function The wait time after the STOP mode is released upon interrupt request until oscillation stabilizes is controlled with the oscillation stabilization time selection register (OSTS). OSTS is set with an 8-bit memory manipulation instruction. RESET input sets OSTS to 04H.
Page 168: Standby Function Operation
CHAPTER 13 STANDBY FUNCTION 13.2 Standby Function Operation 13.2.1 HALT mode HALT mode The HALT mode is set by executing the HALT instruction. The operation statuses in the HALT mode are shown in the following table. Table 13-1. Operation Statuses in HALT Mode Item HALT Mode Operation Status During Main HALT Mode Operation Status During Subsystem...
Page 169 CHAPTER 13 STANDBY FUNCTION Releasing HALT mode The HALT mode can be released by the following three sources. Releasing by unmasked interrupt request The HALT mode is released by an unmasked interrupt request. In this case, if interrupts are enabled to be acknowledged, vectored interrupt servicing is performed.
Page 170 CHAPTER 13 STANDBY FUNCTION Releasing by RESET input When the HALT mode is released by the RESET signal, execution branches to the reset vector address in the same manner as the ordinary reset operation, and program execution is started. Figure 13-3. Releasing HALT Mode by RESET Input HALT Note Wait...
Page 171: Stop Mode
CHAPTER 13 STANDBY FUNCTION 13.2.2 STOP mode STOP mode The STOP mode is set by executing the STOP instruction. Caution Because the standby mode can be released by an interrupt request signal, the standby mode is released as soon as it is set if there is an interrupt source whose interrupt request flag is set and interrupt mask flag is reset.
Page 172 CHAPTER 13 STANDBY FUNCTION Releasing STOP mode The STOP mode can be released by the following two sources. Releasing by unmasked interrupt request The STOP mode can be released by an unmasked interrupt request. In this case, if interrupts are enabled to be acknowledged, vectored interrupt servicing is performed, after the oscillation stabilization time has elapsed.
Page 173 CHAPTER 13 STANDBY FUNCTION Releasing by RESET input When the STOP mode is released by the RESET signal, the reset operation is performed after the oscillation stabilization time has elapsed. Figure 13-5. Releasing STOP Mode by RESET Input STOP Note Wait instruction RESET...
Page 174: Chapter 14 Reset Function
CHAPTER 14 RESET FUNCTION The following three operations are available to generate reset signals. (1) External reset signal input via RESET pin (2) Internal reset by detection of watchdog timer inadvertent program loop time (3) Internal reset using power-on-clear circuit (POC) The external and internal reset signals are functionally equivalent.
Page 175 CHAPTER 14 RESET FUNCTION Figure 14-2. Reset Timing by RESET Input Oscillation During normal Reset period Normal operation stabilization operation (oscillation stops) (reset processing) time wait RESET Internal reset signal Delay Delay Hi-Z Port pin Figure 14-3. Reset Timing by Overflow in Watchdog Timer Oscillation Reset period During normal...
Page 176 CHAPTER 14 RESET FUNCTION Figure 14-5. Reset Timing by Power-on Clear At power application Normal operation Reset period Oscillation stabilization time wait (reset processing) (oscillation stops) Power-on-clear voltage (V Internal reset signal Hi-Z Port pin In STOP mode STOP instruction execution Normal operation Oscillation stabilization Stop status...
Page 177 CHAPTER 14 RESET FUNCTION Table 14-1. Hardware Status After Reset Hardware Status After Reset Note 1 Program counter (PC) Contents of reset vector table (0000H, 0001H) set Stack pointer (SP) Undefined Program status word (PSW) Note 2 Data memory Undefined Note 2 General-purpose registers Undefined...
Page 178: Chapter 15 Μ Μ Μ Μ Pd78F9468
CHAPTER 15 µ µ µ µ PD78F9468 The µ PD78F9468 is available as the flash memory version of the µ PD789467 Subseries. The µ PD78F9468 is a version with the internal ROM of the µ PD789462, 789464, 789466, 789467 replaced with flash memory.
Page 179 CHAPTER 15 µ µ µ µ PD78F9468 The µ PD78F9468 and mask ROM version differ in the on-chip LCD controller/driver macro. The difference in LCD controller/driver between µ PD78F9468 and mask ROM version is shown in Table 15-2. Table 15-2. Difference in LCD Controller/Driver Between µ µ µ µ PD78F9468 and Mask ROM Version Flash Memory Version ( µ...
Page 180: Flash Memory Characteristics
CHAPTER 15 µ µ µ µ PD78F9468 15.1 Flash Memory Characteristics Flash memory programming is performed by connecting a dedicated flash programmer (Flashpro III (part no. FL- Note PR3, PG-FP3)/Flashpro IV (part no. FL-PR4, PG-FP4)) to the target system with the flash memory mounted on the target system (on-board).
Page 181: Communication Mode
CHAPTER 15 µ µ µ µ PD78F9468 15.1.2 Communication mode Use the communication mode shown in Table 15-3 to perform communication between the dedicated flash programmer and µ PD78F9468. Table 15-3. Communication Mode List Note 1 Communication TYPE Setting Pins used Number of V Mode pulses...
Page 182 CHAPTER 15 µ µ µ µ PD78F9468 Figure 15-3. Example of Connection with Dedicated Flash Programmer Dedicated flash programmer µ PD78F9468 VPP1 RESET RESET Note Note Connect this pin when the system clock is supplied by Flashpro III. If an oscillator is already connected to the X1 pin, the CLK pin does not need to be connected.
Page 183: On-Board Pin Processing
CHAPTER 15 µ µ µ µ PD78F9468 15.1.3 On-board pin processing When performing programming on the target system, provide a connector on the target system to connect the dedicated flash programmer. An on-board function that allows switching between normal operation mode and flash memory programming mode may be required in some cases.
Page 184 CHAPTER 15 µ µ µ µ PD78F9468 (1) Signal conflict If the dedicated flash programmer (output) is connected to a serial interface pin (input) that is connected to another device (output), a signal conflict occurs. To prevent this, isolate the connection with the other device or set the other device to the output high impedance status.
Page 185 CHAPTER 15 µ µ µ µ PD78F9468 <RESET pin> If the reset signal of the dedicated flash programmer is connected to the RESET pin connected to the reset signal generator on-board, a signal conflict occurs. To prevent this, isolate the connection with the reset signal generator.
Page 186: Connection On Flash Memory Writing Adapter
CHAPTER 15 µ µ µ µ PD78F9468 15.1.4 Connection on flash memory writing adapter The following shows an example of the recommended connection when using the flash memory writing adapter. Figure 15-8. Wiring Example of Flash Memory Writing Adapter Using 3-Wire Serial I/O Mode (2.7 to 5.5V) 52 51 50 49 48 47 46 45 44 43 42 41 40...
Page 187: Chapter 16 Mask Option
CHAPTER 16 MASK OPTION The mask ROM versions ( µ PD789462, 789464, 789466, and 789467) have the following mask option. • Power-on-clear (POC) circuit Use/non use of the POC circuit can be selected. <1> POC circuit used <2> POC circuit not used Caution The POC circuit normally operates in the flash memory version ( µ...
Page 188: Chapter 17 Instruction Set
CHAPTER 17 INSTRUCTION SET This chapter lists the instruction set of the µ PD789467 Subseries. For the details of the operation and machine language (instruction code) of each instruction, refer to 78K/0S Series User’s Manual Instructions (U11047E). 17.1 Operation 17.1.1 Operand identifiers and description methods Operands are described in “Operands”...
Page 189: Description Of "Operation" Column
CHAPTER 17 INSTRUCTION SET 17.1.2 Description of “Operation” column A register; 8-bit accumulator X register B register C register D register E register H register L register AX register pair; 16-bit accumulator BC register pair DE register pair HL register pair Program counter Stack pointer PSW:...
Page 190: Operation List
CHAPTER 17 INSTRUCTION SET 17.2 Operation List Mnemonic Operands Byte Clock Operation Flag Z AC CY r ← byte r, #byte (saddr) ← byte saddr, #byte sfr ← byte sfr, #byte A ← r Note 1 A, r r ← A Note 1 r, A A ←...
Page 191 CHAPTER 17 INSTRUCTION SET Mnemonic Operands Byte Clock Operation Flag Z AC CY rp ← word MOVW rp, #word AX ← (saddrp) AX, saddrp (saddrp) ← AX saddrp, AX AX ← rp Note AX, rp rp ← AX Note rp, AX AX ↔...
Page 192 CHAPTER 17 INSTRUCTION SET Mnemonic Operands Byte Clock Operation Flag Z AC CY A, CY ← A − byte − CY SUBC A, #byte (saddr), CY ← (saddr) − byte − CY saddr, #byte A, CY ← A − r − CY A, r A, CY ←...
Page 193 CHAPTER 17 INSTRUCTION SET Mnemonic Operands Byte Clock Operation Flag Z AC CY A − byte A, #byte (saddr) − byte saddr, #byte A − r A, r A − (saddr) A, saddr A − (addr16) A, !addr16 A − (HL) A, [HL] A −...
Page 194 CHAPTER 17 INSTRUCTION SET Mnemonic Operands Byte Clock Operation Flag Z AC CY (SP − 1) ← (PC + 3) , (SP − 2) ← (PC + 3) CALL !addr16 PC ← addr16, SP ← SP − 2 (SP − 1) ← (PC + 1) , (SP −...
Page 195: Instructions Listed By Addressing Type
CHAPTER 17 INSTRUCTION SET 17.3 Instructions Listed by Addressing Type 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, INC, DEC, ROR, ROL, RORC, ROLC, PUSH, POP, DBNZ 2nd Operand #byte saddr [DE] [HL] None !addr16 [HL+byte] $addr16 1st Operand Note Note...
Page 196 CHAPTER 17 INSTRUCTION SET 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW Note 2nd Operand #word saddrp None 1st Operand ADDW MOVW MOVW MOVW SUBW XCHW CMPW Note MOVW MOVW INCW DECW PUSH saddrp MOVW MOVW Note Only when rp = BC, DE, or HL. Bit manipulation instructions SET1, CLR1, NOT1, BT, BF 2nd Operand...
Page 197 CHAPTER 17 INSTRUCTION SET Call instructions/branch instructions CALL, CALLT, BR, BC, BNC, BZ, BNZ, DBNZ 2nd Operand !addr16 [addr5] $addr16 1st Operand Basic Instructions CALL CALLT Compound Instructions DBNZ Other instructions RET, RETI, NOP, EI, DI, HALT, STOP Preliminary User’s Manual U15552EJ1V0UD...
Page 198: Chapter 18 Electrical Specifications (Target)
CHAPTER 18 ELECTRICAL SPECIFICATIONS (TARGET) The following shows the target specifications (target values), which may not be satisfied in mass-produced product. = 25° ° ° ° C) Absolute Maximum Ratings (T Parameter Symbol Conditions Ratings Unit −0.3 to +6.5 Supply voltage −0.3 to +10.5 Note −0.3 to V...
Page 199: Main System Clock Oscillator Characteristics
CHAPTER 18 ELECTRICAL SPECIFICATIONS (TARGET) = − − − − 40 to +85°C, V Main System Clock Oscillator Characteristics = 1.8 to 5.5 V) Resonator Recommended Circuit Parameter Conditions MIN. TYP. MAX. Unit Ceramic Oscillation frequency Note 1 resonator Oscillation After V has reached the Note 2...
Page 200: Subsystem Clock Oscillator Characteristics
CHAPTER 18 ELECTRICAL SPECIFICATIONS (TARGET) = − − − − 40 to +85°C, V Subsystem Clock Oscillator Characteristics (T = 1.8 to 5.5 V) Resonator Recommended Circuit Parameter Conditions MIN. TYP. MAX. Unit Crystal Oscillation frequency 32.768 Note 1 resonator 4.5 ≤...
Page 201 CHAPTER 18 ELECTRICAL SPECIFICATIONS (TARGET) = − − − − 40 to +85°C, V DC Characteristics (T = 1.8 to 5.5 V) (1/2) Parameter Symbol Conditions MIN. TYP. MAX. Unit Output current, low Per pin Total for all pins −1 Output current, high Per pin (except P60/TO40) −7...
Page 202 CHAPTER 18 ELECTRICAL SPECIFICATIONS (TARGET) DC Characteristics (T = –40 to +85°C, V = 1.8 to 5.5 V) (2/2) Parameter Symbol Conditions MIN. TYP. MAX. Unit µ A Input leakage current, P00 to P03, P10, LIH1 high P11, P40 to P43, P60, P61, RESET µ...
Page 203: Basic Operation
CHAPTER 18 ELECTRICAL SPECIFICATIONS (TARGET) AC Characteristics = − − − − 40 to +85°C, V (1)Basic operation (T = 1.8 to 5.5 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit 2.7 ≤ V ≤ 5.5 V µ s Cycle time (Min.
Page 204 CHAPTER 18 ELECTRICAL SPECIFICATIONS (TARGET) AC Timing Measurement Points (Excluding X1, XT1 Input) 0.8V 0.8V Point of measurement 0.2V 0.2V Clock Timing (MIN.) X1 input (MAX.) (MIN.) XT1 input (MAX.) Interrupt Input Timing INTL INTH INTP0 Key Return Input Timing KRIL KR00 to KR03 RESET Input Timing...
Page 205: Lcd Characteristics
CHAPTER 18 ELECTRICAL SPECIFICATIONS (TARGET) = − − − − 40 to +85°C, V 8-Bit A/D Converter Characteristics (T = 1.8 to 5.5 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Resolution 2.7 ≤ V ≤ 5.5 V ±0.6 Notes 1, 2 Overall error %FSR 1.8 ≤...
Page 206: Data Memory Stop Mode Low Supply Voltage Data Retention Characteristics
CHAPTER 18 ELECTRICAL SPECIFICATIONS (TARGET) Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics = − − − − 40 to +85°C, V = 1.8 to 5.5 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Data retention supply voltage DDDR Note 1 Note 2...
Page 207 CHAPTER 18 ELECTRICAL SPECIFICATIONS (TARGET) Data Retention Timing Internal reset operation HALT mode STOP mode Operating mode Data retention mode DDDR SREL STOP instruction execution RESET WAIT HALT mode STOP mode Operating mode Data retention mode DDDR SREL STOP instruction execution Standby release signal (interrupt request) WAIT...
Page 208: Chapter 19 Package Drawing
CHAPTER 19 PACKAGE DRAWING 52-PIN PLASTIC LQFP (10x10) detail of lead end ITEM MILLIMETERS 12.0±0.2 10.0±0.2 10.0±0.2 12.0±0.2 0.32±0.06 0.13 0.65 (T.P.) 1.0±0.2 0.17 +0.03 −0.05 0.10 0.1±0.05 3° +4° −3° 1.5±0.1 0.25 0.6±0.15 S52GB-65-8ET-1 Preliminary User’s Manual U15552EJ1V0UD...
Page 209: Chapter 20 Recommended Soldering Conditions
For details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact an NEC sales representative. Note The µ PD789466 and 789467 are under development and have therefore not been evaluated.
Page 210: Appendix A Development Tools
APPENDIX A DEVELOPMENT TOOLS The following development tools are available for development of systems using the µ PD789467 Subseries. Figure A-1 shows development tools. • Support of PC98-NX series Unless specified otherwise, the products supported by IBM PC/AT™ compatibles can be used in the PC98-NX series.
Page 211 APPENDIX A DEVELOPMENT TOOLS Figure A-1. Development Tools Software package • Software package Language processing software Software for debugging • Assembler package • Integrated debugger • C compiler package • System simulator • Device file Note 1 • C compiler source file Control software •...
Page 212: Software Package
APPENDIX A DEVELOPMENT TOOLS A.1 Software Package SP78K0S Software package Various software tools for 78K/0S Series development are integrated into one package. The following tools are included. RA78K0S, CC78K0S, ID78K0-NS, SM78K0S, various device files Part number: µ S××××SP78K0S Remark ×××× in the part number differs depending on the operating system to be used. µ...
Page 213: Control Software
APPENDIX A DEVELOPMENT TOOLS Remark ×××× in the part number differs depending on the host machine and operating system to be used. µ S××××RA78K0S µ S××××CC78K0S ×××× Host Machine Supply Medium AB13 PC-9800 series, IBM PC/AT Japanese Windows 3.5” 2HD FD compatibles BB13 English Windows...
Page 214: Flash Memory Writing Tools
APPENDIX A DEVELOPMENT TOOLS A.4 Flash Memory Writing Tools Flashpro III Dedicated flash programmer for microcontrollers incorporating flash memory (Part No. FL-PR3, PG-FP3) Flash programmer FA-52GB-8ET Adapter for writing to flash memory and connected to Flashpro III. Flash memory writing adapter FA-52GB-8ET: for 52-pin plastic LQFP (GB-8ET type) Remark The FL-PR3 and FA-52GB-8ET are products made by Naito Densei Machida Mfg.
Page 215: Debugging Tools (Software)
APPENDIX A DEVELOPMENT TOOLS A.6 Debugging Tools (Software) ID78K0S-NS A debugger supporting in-circuit emulators for the 78K/0S Series: IE-78K0S-NS and IE- Integrated debugger 78K0S-NS-A. The ID78K0S-NS is Windows-based software. This program enhances the debugging functions for C language. Therefore, it can display the trace results corresponding to the source program by using the window integration function that links the source program, disassembled display, and memory display with the trace results.
Page 216: Cautions When Designing Target System
APPENDIX A DEVELOPMENT TOOLS A.7 Cautions when designing target system The following shows the conditions when connecting the emulation probe to the conversion connector and conversion socket. Design the system considering shapes and other conditions of the components to be mounted on the target system and be sure to follow the configuration below.
Page 217: Appendix B Register Index
APPENDIX B REGISTER INDEX B.1 Register Index (Alphabetic Order of Register Name) A/D conversion result register 0 (ADCR0) ......................126 A/D converter mode register 0 (ADM0) ........................ 128 A/D input selection register 0 (ADS0) ........................129 Carrier generator output control register 40 (TCA40) .................... 95 8-bit compare register 30 (CR30)...........................
Page 218 APPENDIX B REGISTER INDEX Port mode register 4 (PM4) ............................71 Port mode register 6 (PM6) ..........................71, 95 Processor clock control register (PCC) ........................77 Pull-up resistor option register 0 (PU0) ........................72 Subclock control register (CSS) ..........................78 Suboscillation mode register (SCKM) ........................78 Watch timer mode control register (WTM) ......................116 Watchdog timer clock selection register (TCL2)....................121 Watchdog timer mode register (WDTM).......................122...
Page 219: Register Index (Alphabetic Order Of Register Symbol)
APPENDIX B REGISTER INDEX B.2 Register Index (Alphabetic Order of Register Symbol) ADCR0: A/D conversion result register 0 ......................126 ADM0: A/D converter mode register 0 ......................128 ADS0: A/D input selection register 0 ......................129 CR30: 8-bit compare register 30 ........................90 CR40: 8-bit compare register 40 ........................
Page 220 APPENDIX B REGISTER INDEX TCA40: Carrier generator output control register 40 ..................95 TCL2: Watchdog timer clock selection register....................121 TM30: 8-bit timer counter 30 ..........................91 TM40: 8-bit timer counter 40 ..........................91 TMC30: 8-bit timer mode control register 30.......................93 TMC40: 8-bit timer mode control register 40.......................94 WDTM: Watchdog timer mode register ......................122 WTM:...
Page 221 Facsimile Message Although NEC has taken all possible steps to ensure that the documentation supplied to our customers is complete, bug free and up-to-date, we readily accept that From: errors may occur. Despite all the care and precautions we've taken, you may Name encounter problems in the documentation.

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