NEC UPD703116 User Manual page 349

32-bit single-chip microcontrollers

Table of Contents

(11) Timer 2 capture/compare 1 to 4 status register 0 (CCSTATE0)

The CCSTATE0 register indicates the status of the timer 2 sub-channel sub capture/compare register

(CVSEn0) and the timer 2 sub-channel main capture/compare register (CVPEn0) (n = 1 to 4).

This register can be read/written in 16-bit units.

When the higher 8 bits of the CCSTATE0 register are used as the CCSTATE0H register, and the lower 8 bits

are used as the CCSTATE0L register, they can be read/written in 8-bit or 1-bit units.

Caution The BFFEn1 and BFFEn0 bits are read-only bits.

Bit position

14, 10, 6, 2

13, 12, 9, 8,

CHAPTER 9 TIMER/COUNTER FUNCTION

Indicates the capture/compare event occurrence status.

0: In capture register mode: No capture operation has occurred.

In compare register mode: No compare match has occurred.

1: In capture register mode: At least one capture operation has occurred.

In compare register mode: At least one compare match has occurred.

The CEFEn bit can be cleared (0) by performing write access to the

CCSTATE0 register while no capture operation or compare match

occurs. When bit manipulation is performed for the CEFE1 (CEFE3)

bit and the CEFE2 (CEFE4) bit, both bits are cleared.

Indicates the capture buffer status.

The BFFEn1 and BFFEn0 bits return a value only when sub-channel

n sub capture/compare register (CVSEn0) buffer operation (bit

BFEEn of CMSEm0 register = 1) is selected or when capture register

mode (bit CCSEn of CMSEm0 register = 0) is selected. "0" is read

when the compare register mode (CCSEn bit = 1) is selected.

User's Manual U14492EJ5V0UD

Capture buffer status

No value in buffer

Sub-channel n master register (CVPEn0) contains a

capture value. Slave register (CVSEn0) does not

contain a value.

Both sub-channel n master register (CVPEn0) and

slave register (CVSEn0) contain a capture value.

Initial value