NEC UPD703116 User Manual page 314

Table 9-6. Capture Trigger Signal (TM1n) to 16-Bit Capture Register
Remarks 1. CC1n0 and CC1n1 are capture/compare registers. Which of these registers is used is
The valid edge of the capture trigger is specified by signal edge selection register 1n (SESA1n). If both
the rising edge and the falling edge are selected as the capture triggers, it is possible to measure the
input pulse width from external. If a single edge is selected as the capture trigger, the input pulse cycle
can be measured.
(e) PWM output operation
PWM output operation is performed from the TO1n pin by setting TM1n to the general-purpose timer
mode (CMD bit = 0) using timer unit mode register n (TUMn).
The resolution is 16 bits, and the count clock can be selected from among seven internal clocks (f
f /4, f /8, f
CLK CLK
Figure 9-49. TM1n Block Diagram (During PWM Output Operation)
f /2
CLK
f /4
CLK
f /8
CLK
f /16
CLK
f /32
CLK
f /64
CLK
f /128
CLK
Caution Be sure to set the count clock of TM1n to 8 MHz or lower.
Remarks 1. f : Base clock
CLK
2. n = 0, 1
314
CHAPTER 9 TIMER/COUNTER FUNCTION
Capture Register
CC1n0
CC1n1
specified with capture/compare control register n (CCRn).
2. n = 0, 1
/16, f /32, f /64, f
CLK CLK CLK CLK
Clear
TM1n (16 bits)
16
Compare register
(CM1n0)
16
Compare register
(CM1n1)
User's Manual U14492EJ5V0UD
Capture Trigger Signal
INTP1n0
INTP1n0 or INTP1n1
/128).
INTCM1n0
ALVT10 TUMn register
S Q
R
INTCM1n1
/2,
CLK
TO1n