NEC UPD703116 User Manual page 213

(2) Release of IDLE mode
IDLE mode is released by a non-maskable interrupt request, an unmasked maskable interrupt request
Note
(INTPn) , or RESET pin input (n = 0 to 6, 20 to 25).
Note When a digital filter using clock sampling is selected as the noise eliminator for INTP20 to INTP25, the
IDLE mode cannot be released.
(a) Release by a non-maskable interrupt request or an unmasked maskable interrupt request
The IDLE mode can be released by an interrupt request only when transition to IDLE mode is performed
with the INTM and NMIM bits of the PSC register set to 0.
IDLE mode is released by a non-maskable interrupt request or by an unmasked maskable interrupt
request (INTPn) regardless of the priority (n = 0 to 6, 20 to 25). The operation after release is as follows.
Caution When the NMIM and INTM bits of the PSC register = 1, the IDLE mode cannot be
released by the non-maskable interrupt request signal and unmasked maskable
interrupt request signal.
Table 8-5. Operation After IDLE Mode Is Released by Interrupt Request
Release Source
Non-maskable interrupt request
Maskable interrupt request
If the system is set to IDLE mode during a maskable interrupt servicing routine, operation will differ as
follows.
(i) If an interrupt request is generated with a lower priority than that of the interrupt request that is
currently being serviced, IDLE mode is released, but the newly generated interrupt request is not
acknowledged. The new interrupt request is held pending.
(ii) If an interrupt request (including non-maskable interrupt requests) is generated with a higher priority
than that of the interrupt request that is currently being serviced, IDLE mode is released and the
newly generated interrupt request is acknowledged.
If the system is set to IDLE mode during an NMI servicing routine, IDLE mode is released, but the
interrupt is not acknowledged (interrupt is held pending).
Interrupt servicing that is started when IDLE mode is released by NMI pin input is handled in the same
way as normal NMI interrupt servicing that occurs during an emergency (because the NMI interrupt
handler address is unique). Therefore, when a program must be able to distinguish between these two
situations, a software status must be prepared in advance and that status must be set before setting the
PSMR register using a store instruction or a bit manipulation instruction. By checking for this status
during NMI interrupt servicing, an ordinary NMI can be distinguished from the processing that is started
when IDLE mode is released by NMI pin input.
(b) Release by RESET pin input
This is the same as a normal reset operation.
CHAPTER 8 CLOCK GENERATION FUNCTION
Enable Interrupt (EI) Status
Branch to handler address
Branch to handler address or
execute next instruction
User's Manual U14492EJ5V0UD
Disable Interrupt (DI) Status
Execute next instruction
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