NEC UPD703116 User Manual page 271

(e) When BFCMnx = CM0n3 is set in software processing started by INTTM0n
Figure 9-29. Operation Timing in PWM Mode 1 (Asymmetric Triangular Wave, BFCMnx = CM0n3)
count value
0000H
BFCMnx
CM0nx
Interrupt request
DTMnx
Positive phase
(TO0n0, TO0n2, TO0n4)
Negative phase
(TO0n1, TO0n3, TO0n5)
Remarks 1. n = 0, 1
2. x = 0 to 2
3. b = CM0n3
4. t: Dead time = (DTRRn + 1)/f
5. The above figure shows an active high case.
Since TM0n and CM0nx match is detected during count down of TM0n when BFCMnx = CM0n3 has
been set, the F/F remains reset as is and does not get set. Therefore, the positive phase side (TO0n0,
TO0n2, TO0n4 pins) outputs a low level, and the negative phase side (TO0n1, TO0n3, TO0n5 pins)
continues to output a high level. Moreover, the timing of matching with TM0n with CM0nx = CM0n3 is the
cycle when transfer is performed from BFCMnx to CM0nx by INTCM0n3.
The above explanation applies to an active high case. In an active low case, the levels of positive and
negative phases are merely inverted and other operations remain the same.
CHAPTER 9 TIMER/COUNTER FUNCTION
CM0n3
a
TM0
CM0nx CM0nx
match match
a b
a
INTCM0n3
F/F
t
t
(f : Base clock)
CLK CLK
User's Manual U14492EJ5V0UD
CM0n3
b b
b b
INTTM0n INTCM0n3
b
b b
INTTM0n
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