NEC V850E/RS1 Manuals

Manuals and User Guides for NEC V850E/RS1. We have 1 NEC V850E/RS1 manual available for free PDF download: User Manual

NEC V850E/RS1 User Manual (852 pages)

32-/16-bit Single-Chip Microcontroller with CAN Interface

Brand: NEC | Category: Microcontrollers | Size: 5.77 MB

Table of Contents

7
- Preface
  5
  - Table of Contents
    7
List of Tables

27
- Chapter 1 Introduction
  
  29
  - Outline
    29
  - Features
    30
  - Table 1-1: Product Versions
    30
  - Applications
    32
  - Ordering Information
    32
  - Pin Configuration (Top View)
    33
  - Configuration of Function Block
    35
  - Internal Block Diagram
    35
  - On-Chip Units
    36
  - Table 1-2: Port Functions and Control Function
    38
- Chapter 2 Pin Functions
  
  39
- Chapter 3 CPU Function
  
  61
  - Features
    61
  - CPU Register Set
    62
  - Program Register Set
    63
  - Table 3-1: Program Registers
    63
  - System Register Set
    64
  - Table 3-2: System Register Numbers
    64
  - Special Registers
    70
  - Operation Modes
    74
  - Address Space
    75
  - CPU Address Space
    75
  - Image
    76
  - Wrap-Around of CPU Address Space
    77
  - Memory Map
    78
  - Memory Areas
    81
  - Recommended Use of Address Space
    84
  - Cautions
    86
  - Table 3-3: Access Conditions
    90
  - Programmable I/O Area
    92
  - Programmable Peripheral I/O Control Register (BPC)
    92
  - Peripheral I/O Registers
    93
  - Table 3-4: Peripheral I/O Registers
    95
- Chapter 4 Port Functions
  
  105
  - Features
    105
  - Basic Port Configuration
    105
  - Table 4-1: I/O Buffer Power Supplies for Pins
    106
  - Port Configuration
    107
  - Table of Port Configuration
    107
  - Table 4-2: Control Register Setting
    107
  - Table 4-3: Port Configuration
    110
  - Port Function Swap Control Register
    111
  - Port 0
    112
  - Table 4-4: Valid Edge Specification
    117
  - Port 1
    118
  - Table 4-5: Valid Edge Specification
    123
  - Port 3
    124
  - Table 4-6: Valid Edge Specification
    132
  - Port 4
    133
  - Port 5
    136
  - Port 7
    141
  - Port 9
    143
  - Table 4-7: Valid Edge Specification
    154
  - Port CM
    155
  - Port CS
    159
  - Port CT
    162
  - Port DL
    166
  - Port Function Operation
    169
  - Write to I/O Ports
    169
  - Read from I/O Port
    169
  - I/O Port Calculation
    169
  - Port Type
    170
  - Table 4-8: Port Type
    170
  - Port Block Types
    173
  - Port Block Type E-SD1
    173
  - Port Block Type E-SD4
    174
  - Port Block Type E-SD7E
    175
  - Port Block Type E-SDW4
    176
  - Port Block Type N-SDW7
    177
  - Port Block Type N-SD7
    178
  - Port Block Type L-SD1
    179
  - Port Block Type G-SD7
    180
  - Port Block Type U-SD8
    181
  - Port Block Type N-SD2
    182
  - Port Block Type E-SDW10
    183
  - Port Block Diagram E-SD1L
    184
  - Port Block Type W-SDW11
    185
  - Port Block Type E-SD7
    186
  - Port Block Type A-1
    187
  - Port Block Type U-SDW11E
    188
  - Port Block Type G-SD7A
    189
  - Port Block Type G-SDW8E
    190
  - Port Block Type G-SD6
    191
  - Port Block Type G-SDJ2
    192
  - Port Block Type G-SDJ5
    193
  - Port Block Type G-SDJ8E
    194
  - Port Block Type E-DWJ4
    195
  - Port Block Type U-SDW11
    196
  - Port Block Type W-SD11
    197
  - Port Block Type W-SD12E
    198
  - Port Block Type U-SDW10
    199
  - Port Block Type G-SDW6
    200
  - Port Block Type E-D1
    201
  - Port Block Type E-D4
    202
  - Port Block Type D-7E
    203
  - Port Block Type C-D1
    204
  - Port Block Type B
    205
- Chapter 5 Bus Control Function
  
  207
  - Features
    207
  - Bus Control Pins
    208
  - Pin Status When Internal ROM, Internal RAM, or Peripheral I/O Is Accessed
    208
  - Pin Status in each Operation Mode
    208
  - Table 5-1: Bus Control Pins (Multiplexed Bus)
    208
  - Table 5-2: Pin Status When Internal ROM, Internal RAM, or Peripheral I/O Is Accessed
    208
  - Memory Block Function
    209
  - Chip Select Control Function
    210
  - Table 5-3: Allocation of the Memory Blocks
    210
  - Bus Access
    211
  - Number of Clocks for Access
    211
  - Bus Size Setting Function
    212
  - Access by Bus Size
    213
  - Wait Function
    219
  - Programmable Wait Function
    219
  - External Wait Function
    220
  - Relationship between Programmable Wait and External Wait
    220
  - Programmable Address Wait Function
    221
  - Idle State Insertion Function
    222
  - Bus Hold Function
    223
  - Functional Outline
    223
  - Bus Hold Procedure
    224
  - Operation in Power Save Mode
    224
  - Bus Priority
    225
  - Boundary Operation Conditions
    225
  - Program Space
    225
  - Data Space
    225
  - Table 5-4: Bus Priority
    225
  - Bus Timing
    226
- Chapter 6 Clock Generator
  
  233
  - Overview
    233
  - Configuration
    234
  - Control Registers
    235
  - PLL Function
    243
  - Control Register
    245
  - Programmable Clock Output Function (PCL)
    250
  - Control Registers
    250
  - Usage
    252
  - To Use PLL1
    252
  - Table 6-1: Divide and PLL0 Time Value
    252
  - Table 6-2: Divide and PLL1 Time Value
    252
  - To Use Clock through Mode
    253
  - To Use the Programmable Clock Output Function (PCL)
    253
  - Table 6-3: Divide Value of F PLL Frequency and F PCL Frequency
    254
- Chapter 7 16-Bit Timer/Event Counter P
  
  255
- Chapter 8 16-Bit Timer/Event Counter Q
  
  303
  - Features
    303
  - Function Outline
    303
  - Configuration
    304
  - Table 8-1: TMQ Configuration
    304
  - Table 8-2: TMQ Pin List
    304
  - Control Registers
    311
  - Operation
    319
  - Anytime Write and Reload
    319
  - Interval Timer Mode (Tqnmd2 to Tqnmd0 = 000)
    324
  - External Event Counter Mode (Tqnmd2 to Tqnmd0 = 001)
    327
  - External Trigger Pulse Mode (Tqnmd2 to Tqnmd0 = 010)
    331
  - One-Shot Pulse Mode (Tqnmd2 to Tqnmd0 = 011)
    334
  - PWM Mode (Tqnmd2 to Tqnmd0 = 110)
    337
  - Free-Running Mode (Tqnmd2 to Tqnmd0 = 101)
    342
  - Pulse Width Measurement Mode (Tqnmd2 to Tqnmd0 = 110)
    349
  - Timer Synchronization Operation Function
    351
  - Table 8-3: Tuned Operation Mode of Timer
    351
  - Table 8-4: Timer Modes Usable in Tuned Operation Mode
    351
  - Table 8-5: Timer Output Functions
    352
- Chapter 9 16-Bit Interval Timer M
  
  355
  - Features
    355
  - Configuration
    356
  - Table 9-1: Configuration of TMM
    356
  - Control Register
    357
  - Operation
    358
  - Interval Timer Mode
    358
  - Clock Generator and Clock Enable Timing
    358
- Chapter 10 Functions of Watchdog Timer 2
  
  359
  - Functions
    359
  - Configuration
    360
  - Control Registers
    360
  - Table 10-1: Configuration of Watchdog Timer 2
    360
  - Table 10-2: Watchdog Timer 2 Clock Selection
    362
  - Operation
    364
- Chapter 11 A/D Converter
  
  367
  - Functions
    367
  - Configuration
    369
  - Table 11-1: Configuration of A/D Converter
    369
  - Control Registers
    371
  - Operation
    380
  - Basic Operation
    380
  - Trigger Mode
    381
  - Table 11-2: Software Trigger Mode (ADSCM0H Register Configuration)
    381
  - Table 11-3: External Trigger Mode (ADSCM0H and SELCNT1 Registers Configuration)
    381
  - Operation Mode
    383
  - Extended Functions
    391
  - Automatic Discharge Operation
    391
  - Diagnostic Mode
    391
  - Precautions on Operation
    392
  - Stopping A/D
    392
  - Trigger Input During A/D Conversion Operation
    392
  - External or Timer Trigger Interval
    392
  - Operation in Standby Modes
    392
  - Compare Match Interrupt in Timer Trigger Mode (External Trigger Mode)
    393
  - Timing that Makes the A/D Conversion Result Undefined
    393
  - Cautions
    395
  - How to Read A/D Converter Characteristics Table
    398
- Chapter 12 Asynchronous Serial Interface a (UARTA)
  
  403
  - Features
    403
  - Configuration
    404
  - Table 12-1: Configuration of UARTA0 and UARTA1
    404
  - Table 12-2: List of Pins of Asynchronous Serial Interface a
    404
  - Control Registers
    406
  - Control Registers
    407
  - Interrupt Request Signals
    415
  - Table 12-3: Interrupts and Their Default Priority
    415
  - Operation
    416
  - Data Format
    416
  - UART Transmission
    417
  - Procedure of Continuous Transmission
    418
  - UART Reception
    420
  - Reception Errors
    421
  - Table 12-4: Reception Error Causes
    421
  - Types and Operation of Parity
    423
  - Noise Filter of Receive Data
    424
  - Dedicated Baud Rate Generator
    425
  - Table 12-5: Baud Rate Generator Set Data
    427
  - Table 12-6: Permissible Maximum/Minimum Baud Rate Error
    429
  - Caution for Use in On-Chip Debug Mode
    430
- Chapter 13 3-Wire Serial Interface (CSIB)
  
  431
  - Features
    431
  - Configuration
    431
  - Table 13-1: Configuration of CSIB0, CSIB1
    431
  - Table 13-2: List of 3-Wire Serial Interface Pins
    432
  - Control Registers Overview
    433
  - Control Registers Description
    434
  - Transfer Data Length Change Function
    441
  - Interrupt Request Signals
    442
  - Table 13-3: Interrupts and Their Default Priority
    442
  - Operation
    443
  - Single Transfer Mode (Master Mode, Transmission/Reception Mode)
    443
  - Single Transfer Mode (Master Mode, Reception Mode)
    444
  - Continuous Mode (Master Mode, Transmission/Reception Mode)
    445
  - Continuous Mode (Master Mode, Reception Mode)
    446
  - Continuous Reception Mode (Error)
    447
  - Continuous Mode (Slave Mode, Transmission/Reception Mode)
    448
  - Continuous Mode (Slave Mode, Reception Mode)
    449
  - Clock Timing
    450
  - Output Pin Status with Operation Disabled
    452
  - Operation Flow
    453
  - Prescaler 3
    461
  - Control Registers of Prescaler 3
    461
  - Generation of Count Clock
    462
- Chapter 14 Queued CSI (CSI30, CSI31)
  
  463
  - Features
    463
  - Queued CSI Block Diagram
    464
  - Input/Output Pins
    464
  - Table 14-1: Input/Output Pins of the CSI3
    464
  - Queued CSI Control Registers
    465
  - Table 14-2: CSI30
    465
  - Table 14-3: CSI31
    465
  - Explanation of Queued CSI Functions
    476
  - Transmit Buffer
    476
  - Serial Data Direction Select Function
    477
  - Data Length Select Function
    478
  - Slave Mode
    479
  - Master Mode
    479
  - Transmission Clock Select Function
    480
  - Description of the Single Buffer Transfer Mode
    481
  - Description of the FIFO Buffer Transfer Mode
    483
  - Description of the Operation Modes
    485
  - Additional Timing and Delay Selections
    486
  - Default Pin Levels
    489
  - Transmit Buffer Overflow Interrupt Signal (Intc3No)
    490
  - Operating Procedure
    491
- Chapter 15 DMA Functions (DMA Controller)
  
  503
  - Features
    503
  - Configuration
    504
  - Control Registers
    505
  - Table 15-1: Interrupt Source for DMA Trigger Factor Register (Dtfrn) (1/2
    518
  - DMA Transfer Rules
    520
  - Transfer Targets
    520
  - DMA Channel Priority
    520
  - DMA Transfer Start Factors
    520
  - Table 15-2: Transfer Targets
    520
  - DMA Transfer End
    521
  - Transfer Modes
    522
  - Single Transfer Mode
    522
  - Fixed Channel Transfer Mode
    523
  - Block Transfer Mode
    524
  - Summary on the Transfer Modes
    524
  - Table 15-3: Comparison of DMA Transfer Modes
    524
- Chapter 16 FCAN Controller
  
  525
  - Overview
    525
  - Features
    525
  - Overview of Functions
    526
  - Table 16-1: Overview of Functions
    526
  - Configuration
    527
  - CAN Protocol
    528
  - Frame Format
    528
  - Frame Types
    529
  - Data Frame and Remote Frame
    529
  - Table 16-2: Frame Types
    529
  - Table 16-3: RTR Frame Settings
    531
  - Table 16-4: Frame Format Setting (IDE Bit) and Number of Identifier (ID) Bits
    532
  - Table 16-5: Data Length Setting
    532
  - Table 16-6: Operation in Error Status
    536
  - Error Frame
    537
  - Table 16-7: Definition of Error Frame Fields
    537
  - Overload Frame
    538
  - Table 16-8: Definition of Overload Frame Fields
    538
  - Functions
    539
  - Determining Bus Priority
    539
  - Bit Stuffing
    539
  - Table 16-9: Determining Bus Priority
    539
  - Table 16-10: Bit Stuffing
    539
  - Multi Masters
    540
  - Multi Cast
    540
  - CAN Sleep Mode/Can Stop Mode Function
    540
  - Error Control Function
    540
  - Table 16-11: Error Types
    540
  - Table 16-12: Output Timing of Error Frame
    541
  - Table 16-13: Types of Error States
    542
  - Table 16-14: Error Counter
    543
  - Baud Rate Control Function
    547
  - Connection with Target System
    551
  - Internal Registers of CAN Controller
    552
  - CAN Controller Configuration
    552
  - Table 16-15: List of CAN Controller Registers
    552
  - Register Access Type
    553
  - Table 16-16: Register Access Type
    553
  - Table 16-17: CAN Module Register Bit Configuration
    584
  - Register Bit Configuration
    586
  - Table 16-18: CAN Global Register Bit Configuration
    586
  - Table 16-19: Message Buffer Register Bit Configuration
    587
  - Control Registers
    588
  - Bit Set/Clear Function
    624
  - CAN Controller Initialization
    626
  - Initialization of CAN Module
    626
  - Initialization of Message Buffer
    626
  - Redefinition of Message Buffer
    626
  - Transition from Initialization Mode to Operation Mode
    627
  - Resetting Error Counter Cnerc of CAN Module
    628
  - Message Reception
    629
  - Receive History List Function
    630
  - Mask Function
    632
  - Multi Buffer Receive Block Function
    634
  - Remote Frame Reception
    635
  - Message Transmission
    636
  - Transmit History List Function
    638
  - Automatic Block Transmission (ABT)
    639
  - Transmission Abort Process
    641
  - Remote Frame Transmission
    641
  - Power Saving Modes
    642
  - CAN Sleep Mode
    642
  - CAN Stop Mode
    644
  - Example of Using Power Saving Modes
    646
  - Interrupt Function
    647
  - Table 16-20: List of CAN Module Interrupt Sources
    647
  - Diagnosis Functions and Special Operational Modes
    648
  - Receive-Only Mode
    648
  - Single-Shot Mode
    649
  - Self-Test Mode
    650
  - Time Stamp Function
    651
  - Baud Rate Settings
    652
  - Bit Rate Setting Conditions
    652
  - Table 16-21: Settable Bit Rate Combinations
    653
  - Representative Examples of Baud Rate Settings
    656
  - Table 16-22: Representative Examples of Baud Rate Settings (F CANMOD = 8 Mhz)
    656
  - Table 16-23: Representative Examples of Baud Rate Settings (F CANMOD = 16 Mhz)
    658
  - Operation of CAN Controller
    660
- Chapter 17 Interrupt/Exception Processing Function
  
  685
  - Features
    685
  - Table 17-1: Interrupt/Exception Source List
    685
  - Non-Maskable Interrupts
    688
  - Operation
    690
  - Restore
    691
  - NP Flag
    692
  - Eliminating Noise on NMI Pin
    692
  - Function to Detect Edge of NMI Pin
    693
  - Maskable Interrupts
    694
  - Operation
    694
  - Restore
    696
  - Priorities of Maskable Interrupts
    697
  - Interrupt Control Register (Xxicn)
    701
  - Table 17-2: Interrupt Control Register (Xxicn) (1/2
    702
  - Interrupt Mask Registers 0 to 3 (IMR0 to IMR3)
    704
  - In-Service Priority Register (ISPR)
    705
  - Maskable Interrupt Status Flag
    706
  - Watchdog Timer Mode Register 2 (WDTM2)
    707
  - Eliminating Noise on INTP0 to INTP7 Pins
    708
  - Function to Detect Edge of INTP0 to INTP7 Pins
    708
  - Table 17-3: Watchdog Timer 2 Clock Selection
    708
  - Table 17-4: Valid Edge Specification
    709
  - Table 17-5: Valid Edge Specification
    710
  - Table 17-6: Valid Edge Specification
    711
  - Table 17-7: Valid Edge Specification
    712
  - Software Exception
    714
  - Operation
    714
  - Restore
    715
  - Exception Status Flag (EP)
    716
  - Exception Trap
    717
  - Illegal Opcode Definition
    717
  - Interrupt Acknowledge Time of CPU
    721
  - Periods in Which Interrupts Are Not Acknowledged by CPU
    722
- Chapter 18 Standby Function
  
  723
  - Overview
    723
  - Table 18-1: Standby Modes
    723
  - Status Transition
    724
  - HALT Mode
    727
  - Setting and Operation Status
    727
  - Releasing HALT Mode
    727
  - Table 18-2: Operation after Releasing HALT Mode by Interrupt Request
    727
  - Table 18-3: Operation Status in HALT Mode
    728
  - IDLE1 Mode
    729
  - Setting and Operation Status
    729
  - Releasing IDLE1 Mode
    729
  - Table 18-4: Operation after Releasing IDLE1 Mode by Interrupt Request
    730
  - Table 18-5: Operation Status in IDLE1 Mode
    730
  - IDLE2 Mode
    731
  - Setting and Operation Status
    731
  - Releasing IDLE2 Mode
    731
  - Table 18-6: Operation after Releasing IDLE2 Mode by Interrupt Request
    732
  - Table 18-7: Operation Status in IDLE2 Mode
    732
  - Securing Setup Time When Releasing IDLE2 Mode
    733
  - STOP Mode
    734
  - Setting and Operation Status
    734
  - Table 18-8: Operation after Releasing STOP Mode by Interrupt Request
    735
  - Table 18-9: Operation Status in STOP Mode
    735
  - Securing Oscillation Stabilization Time
    736
  - Control Registers
    737
- Chapter 19 RESET Function
  
  739
- Chapter 20 Regulator
  
  747
  - Outline
    747
  - Operation
    748
- Chapter 21 Flash Memory
  
  749
  - Features
    749
  - Erasure Unit
    750
  - Address Assignment in the Memory Map
    751
  - Writing with Flash Programmer
    752
  - Programming Environment
    752
  - Communication Mode
    753
  - Table 21-1: Signal Generation of Dedicated Flash Programmer (PG-FP4)
    755
  - Pin Connection
    756
  - FLMD0 Pin
    756
  - FLMD1 Pin
    757
  - Table 21-2: Relationship between FLMD0 and FLMD1 Pins and Operation Mode
    757
  - Serial Interface Pin
    758
  - Table 21-3: Pins Used by each Serial Interface
    758
  - RESET Pin
    760
  - Port Pins (Including NMI)
    760
  - Other Signal Pins
    760
  - Recommended Circuit Example of the Flash Write Mode
    761
  - Programming Method
    762
  - Flash Memory Control
    762
  - Flash Memory Programming Mode
    763
  - Selection of Communication Mode
    764
  - Communication Command
    764
  - Table 21-4: List of Communication Modes
    764
  - Table 21-5: Flash Memory Control Command
    765
  - Table 21-6: Response Commands
    765
- Chapter 22 On-Chip Debug Function
  
  767
  - Functional Outline
    767
  - Type of On-Chip Debug Unit
    767
  - Debug Functions
    767
  - Security Function
    770
  - Table 22-1: ID Code
    770
  - Control Register
    771
  - Operation of On-Chip Debug Function
    773
  - Connection to N-Wire Emulator
    774
  - Table 22-2: Pin Functions of Connector for Emulator Connection (Target System Side)
    776
  - Restrictions and Cautions on On-Chip Debug Function
    778
- Chapter 23 Power-On-Clear Circuit
  
  779
- Chapter 24 Low-Voltage Detector
  
  781
- Chapter 25 Clock Monitor
  
  789
- Chapter 26 CRC Function
  
  793
  - Functions
    793
  - Configuration
    793
  - Table 26-1: CRC Configuration
    793
  - Registers
    794
  - Operation
    795
  - Usage Method
    796
- Chapter 27 Electrical Specification
  
  799
  - General
    799
  - Absolute Maximum Ratings
    799
  - Absolute Maximum Ratings (Μpd70F3402)
    800
  - Absolute Maximum Ratings (Μpd70F3403, Μpd70F3403A)
    800
  - Capacitance
    800
  - Recommended Operating Conditions
    801
  - Recommended Operating Conditions (Μpd70F3402)
    801
  - Recommended Operating Conditions (Μpd70F3403, Μpd70F3403A)
    801
  - Oscillator Characteristics
    802
  - General Condition
    802
  - Oscillator Timing and Recommended Oscillator Connection
    802
  - Voltage Regulator Characteristics
    803
  - General Condition
    803
  - Regulator 0
    803
  - Regulator 1
    803
  - DC Characteristics
    804
  - General Condition
    804
  - DC Input/Output Level
    804
  - DC Power Supply Current (Μpd70F3402)
    806
  - DC Power Supply Current (Μpd70F3403, Μpd70F3403A)
    806
  - AC Characteristics
    807
  - General Condition
    807
  - AC Test Input Waveform
    807
  - Input Waveform
    808
  - Output Waveform
    808
  - RESET, NMI, Interrupt and FLMD0 Timing
    809
  - Timer P and Timer Q Input/Output
    810
  - Bus Interface Timing (Μpd70F3403, Μpd70F3403A Only)
    811
  - Csibn Timing
    815
  - Uartan Timing
    816
  - CAN Interface Timing (Μpd70F3402)
    817
  - CAN Interface Timing (Μpd70F3403, Μpd70F3403A)
    817
  - CAN Interface Timing Diagram
    817
  - Csi3N Timing
    818
  - A/D Converter Characteristics
    824
  - Power-On-Clear (POC)
    825
  - Low-Voltage Indicator (LVI)
    826
  - Power on Sequence
    827
  - Flash Memory Characteristics
    828
  - General Condition
    828
  - Basic Flash Characteristics (Μpd70F3402)
    828
  - Basic Flash Characteristics (Μpd70F3403, Μpd70F3403A)
    828
  - External Flash Programmer Serial Write Operation Characteristics
    829
  - Flash Programming Characteristics
    830
- Chapter 28 Package Drawing
  
  831
- Chapter 29 Recommended Soldering Conditions
  
  833
  - Table 29-1: Soldering Conditions
    833

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NEC V850E/RS1 User Manual (852 pages)

Table of Contents

Table of Contents

List of Tables

Chapter 1 Introduction

Chapter 2 Pin Functions

Chapter 3 CPU Function

Chapter 4 Port Functions

Chapter 5 Bus Control Function

Chapter 6 Clock Generator

Chapter 7 16-Bit Timer/Event Counter P

Chapter 8 16-Bit Timer/Event Counter Q

Chapter 9 16-Bit Interval Timer M

Chapter 10 Functions of Watchdog Timer 2

Chapter 11 A/D Converter

Chapter 12 Asynchronous Serial Interface a (UARTA)

Chapter 13 3-Wire Serial Interface (CSIB)

Chapter 14 Queued CSI (CSI30, CSI31)

Chapter 15 DMA Functions (DMA Controller)

Chapter 16 FCAN Controller

Chapter 17 Interrupt/Exception Processing Function

Chapter 18 Standby Function

Chapter 19 RESET Function

Chapter 20 Regulator

Chapter 21 Flash Memory

Chapter 22 On-Chip Debug Function

Chapter 23 Power-On-Clear Circuit

Chapter 24 Low-Voltage Detector

Chapter 25 Clock Monitor

Chapter 26 CRC Function

Chapter 27 Electrical Specification

Chapter 28 Package Drawing

Chapter 29 Recommended Soldering Conditions

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