NEC UPD703116 User Manual page 780

32-bit single-chip microcontrollers

Table of Contents

(6) Timer input timing

= –40 to +85°C:

PD703116, 703116(A), 70F3116, 70F3116(A),

= –40 to +110°C:

= 3.0 to 3.6 V, V

TIUDn, TCUDn high-/low-level width

TIUDn, TCUDn input time difference

TCLRn high-/low-level width

TIn high-/low-level width

When setting the timer 2 count clock/control edge selection register 0 (CSE0)'s CESE1 bit to 1 and CESE0 bit

Remarks 1. T: Digital filter sampling clock

T can be selected by setting the following registers.

• When using TIUDn, TCUDn, and TCLRn (n = 10, 11), the following cycles can be selected by

setting the NRCn1 and NRCn0 bits of timer n noise elimination time selection register (NRCn).

• When using TCLR2 and TI2, the following cycles can be selected by setting the PRM2 bit of the

timer 1/timer 2 clock selection register (PRM02).

• When using TCLR3 and TI3, the following cycles can be selected by setting the NRC31 and

NRC30 bits of timer 3 noise elimination time selection register (NRC3).

: Internal system clock frequency

TIUDm (input)

TCUDm (input)

TCLRn (input)

m = 10, 11 n = 10, 11, 2, 3

CHAPTER 18 ELECTRICAL SPECIFICATIONS

PD703116(A1), 70F3116(A1),

= 5 V ±0.5 V, V

/2 is selected for the timer n base clock: f

/4 is selected for the timer n base clock: f

/2 is selected for the timer 2 base clock: f

/4 is selected for the timer 2 base clock: f

is selected for the timer 3 base clock: f

/2 is selected for the timer 3 base clock: f

User's Manual U14492EJ5V0UD

n = 10, 11, 2 (other than for

through input), 3

n = 2 (for through input

n = 2 (other than for through

n = 2 (for through input