NEC UPD703116 User Manual page 261

[Output waveform width in respect to set value]
• PWM cycle = BFCMn3 × 2 × T
• Dead-time width
T
Dnm
• Active width of positive phase (TO0n0, TO0n2, TO0n4 pins)
= { (CM0n3 − CM0nX
• Active width of negative phase (TO0n1, TO0n3, TO0n5 pins)
= (CM0nX + CM0nX
down
f : Base clock
CLK
T : TM0n count clock
TM0n
CM0nX : Set value of CM0n0 to CM0n2 while TM0n is counting up
up
CM0nX : Set value of CM0n0 to CM0n2 while TM0n is counting down
down
The pin level when the TO0n0 to TO0n5 pins are reset is the high impedance state. When the control mode is
selected thereafter, the following levels are output until the TM0n is started.
• TO0n0, TO0n2, TO0n4... When low active → High level
• TO0n1, TO0n3, TO0n5... When low active → Low level
The active level is set with the ALVTO bit of the TOMRn register. The default is low active.
Caution If a value such that the positive phase or negative phase active width is "0" or a negative
value in the above formula, the TO0n0 to TO0n5 pins output a waveform fixed to the
inactive level waveform with active width "0".
Remark m = 0 to 2
n = 0, 1
CHAPTER 9 TIMER/COUNTER FUNCTION
TM0n
= (DTRRn + 1)/f
CLK
) + (CM0n3 − CM0nX
up down
) × T − T
up TM0n Dnm
When high active → Low level
When high active → High level
User's Manual U14492EJ5V0UD
) } × T − T
TM0n Dnm
261