NEC UPD703116 User Manual page 809

Mnemonic Operands
RETI
0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0
0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0
SAR reg1, reg2 r r r r r 1 1 1 1 1 1 R R R R R
0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0
r r r r r 0 1 0 1 0 1 i i i i i GR[reg2] ← GR[reg2] arithmetically shift right by zero-
imm5, reg2
SASF cccc, reg2
r r r r r 1 1 1 1 1 1 0 c c c c
0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
r r r r r 0 0 0 1 1 0 R R R R R GR[reg2] ← saturated (GR[reg2] + GR[reg1])
SATADD reg1, reg2
r r r r r 0 1 0 0 0 1 i i i i i GR[reg2] ← saturated (GR[reg2] + sign-extend (imm5))
imm5, reg2
r r r r r 0 0 0 1 0 1 R R R R R GR[reg2] ← saturated (GR[reg2] − GR[reg1])
SATSUB reg1, reg2
SATSUBI imm16, reg1, r r r r r 1 1 0 0 1 1 R R R R R
reg2 i i i i i i i i i i i i i i i i
r r r r r 0 0 0 1 0 0 R R R R R GR[reg2] ← saturated (GR[reg1] − GR[reg2])
SATSUBR reg1, reg2
SETF cccc, reg2
r r r r r 1 1 1 1 1 1 0 c c c c
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SET1 bit#3, disp16 0 0 b b b 1 1 1 1 1 0 R R R R R
[reg1]
d d d d d d d d d d d d d d d d
reg2, [reg1]
r r r r r 1 1 1 1 1 1 R R R R R
0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0
SHL reg1, reg2 r r r r r 1 1 1 1 1 1 R R R R R
0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0
imm5, reg2
r r r r r 0 1 0 1 1 0 i i i i i
SHR reg1, reg2
r r r r r 1 1 1 1 1 1 R R R R R
0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
r r r r r 0 1 0 1 0 0 i i i i i GR[reg2] ← GR[reg2] logically shift right
imm5, reg2
r r r r r 0 1 1 0 d d d d d d d adr ← ep + zero-extend (disp7)
SLD.B disp7[ep],
reg2
r r r r r 0 0 0 0 1 1 0 d d d d adr ← ep + zero-extend (disp4)
SLD.BU disp4[ep],
reg2
r r r r r 1 0 0 0 d d d d d d d adr ← ep + zero-extend (disp8)
SLD.H disp8[ep],
reg2
APPENDIX C INSTRUCTION SET LIST
Opcode
if PSW.EP = 1
← EIPC
then PC
PSW ← EIPSW
else if PSW.NP = 1
← FEPC
then PC
PSW ← FEPSW
← EIPC
else PC
PSW ← EIPSW
GR[reg2] ← GR[reg2] arithmetically shift right by
GR[reg1]
extend (imm5)
if conditions are satisfied
then GR[reg2] ← (GR[reg2] Logically shift left by 1)
OR 00000001H
else GR[reg2] ← (GR[reg2] Logically shift left by 1)
OR 00000000H
GR[reg2] ← saturated (GR[reg1] − sign-extend
(imm16))
if conditions are satisfied
then GR[reg2] ← 00000001H
else GR[reg2] ← 00000000H
adr ← GR[reg1] + sign-extend (disp16)
Z flag ← Not (Load-memory-bit (adr, bit#3))
Store-memory-bit (adr, bit#3, 1)
adr ← GR[reg1]
Z flag ← Not (Load-memory-bit (adr, reg2))
Store-memory-bit (adr, reg2, 1)
GR[reg2] ← GR[reg2] logically shift left by GR[reg1]
GR[reg2] ← GR[reg2] logically shift left
by zero-extend (imm5)
GR[reg2] ← GR[reg2] logically shift right by GR[reg1]
by zero-extend (imm5)
GR[reg2] ← sign-extend (Load-memory (adr, Byte))
GR[reg2] ← zero-extend (Load-memory (adr, Byte))
Note 18
GR[reg2] ← sign-extend (Load-memory (adr,
Note 19
Halfword))
User's Manual U14492EJ5V0UD
Operation Execution Clock
i
4
1
1
1
1
1
1
1
1
1
3
Note 3
3
Note 3
1
1
1
1
1
1
1
Flags
r I CY OV S Z
4 4 R R R R
× × ×
1 1 0
× × ×
1 1
0
1 1
× × × ×
1 1
× × × ×
1 1
× × × ×
1 1
× × × ×
1 1
× × × ×
1 1
1 1
×
3 3
Note 3 Note 3
×
3 3
Note 3 Note 3
× × ×
1 1 0
× × ×
1 1 0
× × ×
1 1 0
× × ×
1 1 0
1
Note 9
1
Note 9
1
Note 9
(4/5)
SAT
R
×
×
×
×
×
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