NEC UPD703116 User Manual page 279

32-bit single-chip microcontrollers
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(b) When BFCMnx = CM0n3 is set
Figure 9-34. Operation Timing in PWM Mode 2 (Sawtooth Wave, BFCMnx = CM0n3)
count value
Interrupt request
Positive phase
(TO0n0, TO0n2, TO0n4)
Negative phase
(TO0n1, TO0n3, TO0n5)
Remarks 1. n = 0, 1
2. x = 0 to 2
3. b = CM0n3
4. t: Dead time = (DTRRn + 1)/f
5. The above figure shows an active high case.
If match signal INTCM0n3 for TM0n and CM0n3 and the match signal for TM0n and CM0nx conflict,
reset of the F/F takes precedence, so that the F/F does not get set following match of CM0nx (= CM0n3)
with TM0n.
CHAPTER 9 TIMER/COUNTER FUNCTION
a
TM0n
0000H
CM0nx
match
a
BFCMnx
b
a
CM0nx
INTCM0n3
F/F
Set by rising edge of
TM0CEn bit
DTMnx
t
t
(f
: Base clock)
CLK
CLK
User's Manual U14492EJ5V0UD
CM0n3
CM0n3
b
b
INTCM0n3
t
t
CM0n3
b
b
INTCM0n3
279

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