NEC UPD703116 User Manual page 265

(b) When BFCMnx > CM0n3 is set in software processing started by INTTM0n
Figure 9-23. Operation Timing in PWM Mode 1 (Asymmetric Triangular Wave, BFCMnx > CM0n3)
TM0n
count value
0000H
BFCMnx
CM0nx
Interrupt request
DTMnx
Positive phase
(TO0n0, TO0n2, TO0n4)
Negative phase
(TO0n1, TO0n3, TO0n5)
Remarks 1. n = 0, 1
2. x = 0 to 2
3. b > CM0n3
4. t: Dead time = (DTRRn + 1)/f
5. The above figure shows an active high case.
When a value greater than CM0n3 is set to BFCMnx, the positive phase side (TO0n0, TO0n2, TO0n4
pins) outputs a high level, and the negative phase side (TO0n1, TO0n3, TO0n5 pins) continues to output
a low level. This feature is effective for outputting a low-level or high-level width exceeding the PWM
cycle in an application such as inverter control.
The above explanation applies to an active high case. In an active low case, the levels of positive and
negative phases are merely inverted and other operations remain the same.
Figure 9-24 shows the change timing from the 100% duty state.
CHAPTER 9 TIMER/COUNTER FUNCTION
CM0n3
a
CM0nx
match
a b
a
INTCM0n3
F/F
t
(f : Base clock)
CLK CLK
User's Manual U14492EJ5V0UD
CM0n3
b b
b b
INTTM0n INTCM0n3
b
b b
INTTM0n
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