NEC UPD703116 User Manual page 166

INTC acknowledged
CPU processing
Note For the ISPR register, see 7.3.6 In-service priority register (ISPR).
The INT input masked by the interrupt controllers and the INT input that occurs while another interrupt is being
serviced (when PSW.NP = 1 or PSW.ID = 1) are held pending internally by the interrupt controller. In such case, if the
interrupts are unmasked, or when PSW.NP = 0 and PSW.ID = 0 as set by the RETI and LDSR instructions, input of
the pending INT starts the new maskable interrupt servicing.
166
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION
Figure 7-4. Servicing Configuration of Maskable Interrupt
INT input
xxIF = 1
xxMK = 0
Priority higher than
that of interrupt currently
being serviced?
Priority higher
than that of other interrupt
request?
Highest default
priority of interrupt requests
with the same priority?
Maskable interrupt request
PSW.NP
PSW.ID
EIPC
EIPSW
ECR.EICC
PSW.EP
PSW.ID
Corresponding
Note
bit of ISPR
PC
Interrupt servicing
User's Manual U14492EJ5V0UD
No
Yes
No
Is the interrupt
mask released?
Yes
No
Yes
No
Yes
No
Yes
Interrupt request held pending
1
0
1
0
restored PC
Interrupt request held pending
PSW
exception code
0
1
1
handler address