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NEC V850ES/JJ3 Hardware User Manual

NEC V850ES/JJ3 Hardware User Manual

32-bit single-chip microcontrollers

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User's Manual

V850ES/JJ3

32-bit Single-Chip Microcontrollers

Hardware

μ

PD70F3743

μ

PD70F3744

μ

PD70F3745

μ

PD70F3746

Document No. U18376EJ3V0UD00 (3rd edition)

Date Published August 2008 N

Printed in Japan

2006

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Page 1 User’s Manual V850ES/JJ3 32-bit Single-Chip Microcontrollers Hardware μ PD70F3743 μ PD70F3744 μ PD70F3745 μ PD70F3746 Document No. U18376EJ3V0UD00 (3rd edition) Date Published August 2008 N 2006 Printed in Japan...
Page 2 [MEMO] User’s Manual U18376EJ3V0UD...
Page 3 NOTES FOR CMOS DEVICES VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between V (MAX) and V (MIN) due to noise, etc., the device may malfunction.
Page 4 Silicon Storage Technology, Inc. IECUBE is a registered trademark of NEC Electronics Corporation in Japan and Germany. MINICUBE is a registered trademark of NEC Electronics Corporation in Japan and Germany or a trademark in the United States of America.
Page 5 NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Page 6 PREFACE Readers This manual is intended for users who wish to understand the functions of the V850ES/JJ3 and design application systems using the V850ES/JJ3. Purpose This manual is intended to give users an understanding of the hardware functions of the V850ES/JJ3 shown in the Organization below.
Page 7 Conventions Data significance: Higher digits on the left and lower digits on the right Active low representation: xxx (overscore over pin or signal name) Memory map address: Higher addresses on the top and lower addresses on the bottom Note: Footnote for item marked with Note in the text Caution: Information requiring particular attention Remark:...
Page 8 Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents related to V850ES/JJ3 Document Name Document No. V850ES Architecture User’s Manual U15943E V850ES/JJ3 Hardware User’s Manual This manual...
Page 9: Table Of Contents
CONTENTS CHAPTER 1 INTRODUCTION .........................19 General .............................19 Features............................21 Application Fields ........................22 Ordering Information ......................22 Pin Configuration (Top View) ....................23 Function Block Configuration....................25 1.6.1 Internal block diagram ....................... 25 1.6.2 Internal units ..........................26 CHAPTER 2 PIN FUNCTIONS........................29 List of Pin Functions.......................29 Pin States ..........................40 Pin I/O Circuit Types, I/O Buffer Power Supplies and Connection of Unused Pins..41 Cautions ...........................45...
Page 10 4.3.10 Port CD ............................126 4.3.11 Port CM ...........................127 4.3.12 Port CS ............................129 4.3.13 Port CT ............................131 4.3.14 Port DH ............................133 4.3.15 Port DL ............................135 Block Diagrams........................138 Port Register Settings When Alternate Function Is Used ..........170 Cautions ..........................179 4.6.1 Cautions on setting port pins ....................179 4.6.2...
Page 11 6.5.2 Registers ..........................219 6.5.3 Usage ............................222 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) ..............223 Overview..........................223 Functions ..........................223 Configuration .........................224 Registers ..........................226 Operation..........................238 7.5.1 Interval timer mode (TPnMD2 to TPnMD0 bits = 000)............. 239 7.5.2 External event count mode (TPnMD2 to TPnMD0 bits = 001)..........249 7.5.3 External trigger pulse output mode (TPnMD2 to TPnMD0 bits = 010)........
Page 12 10.4.1 Operation as watch timer ......................426 10.4.2 Operation as interval timer.......................427 10.4.3 Cautions...........................428 CHAPTER 11 FUNCTIONS OF WATCHDOG TIMER 2 ..............429 11.1 Functions..........................429 11.2 Configuration ........................430 11.3 Registers ..........................431 11.4 Operation..........................433 CHAPTER 12 REAL-TIME OUTPUT FUNCTION (RTO)..............434 12.1 Function..........................
Page 13 15.5 Interrupt Request Signals.....................494 15.6 Operation..........................495 15.6.1 Data format..........................495 15.6.2 SBF transmission/reception format..................497 15.6.3 SBF transmission ........................499 15.6.4 SBF reception.......................... 500 15.6.5 UART transmission........................502 15.6.6 Continuous transmission procedure ..................503 15.6.7 UART reception ........................505 15.6.8 Reception errors ........................
Page 14 17.3 Configuration ........................572 17.4 Registers ..........................576 17.5 C Bus Mode Functions....................... 592 17.5.1 Pin configuration ........................592 17.6 C Bus Definitions and Control Methods ................593 17.6.1 Start condition..........................593 17.6.2 Addresses..........................594 17.6.3 Transfer direction specification ....................595 17.6.4 ACK ............................596 17.6.5 Stop condition ..........................597 17.6.6...
Page 15 18.13 Cautions ..........................665 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION ..........670 19.1 Features..........................670 19.2 Non-Maskable Interrupts ......................674 19.2.1 Operation..........................676 19.2.2 Restore............................ 677 19.2.3 NP flag............................. 678 19.3 Maskable Interrupts ......................679 19.3.1 Operation..........................679 19.3.2 Restore............................ 681 19.3.3 Priorities of maskable interrupts ....................682 19.3.4 Interrupt control register (xxICn) ....................
Page 16 21.6 STOP Mode..........................721 21.6.1 Setting and operation status ....................721 21.6.2 Releasing STOP mode ......................721 21.6.3 Securing oscillation stabilization time when releasing STOP mode .........724 21.7 Subclock Operation Mode ....................725 21.7.1 Setting and operation status ....................725 21.7.2 Releasing subclock operation mode ..................725 21.8 Sub-IDLE Mode ........................
Page 17 27.1 Features..........................757 27.2 Memory Configuration ......................758 27.3 Functional Outline.........................760 27.4 Rewriting by Dedicated Flash Programmer ...............763 27.4.1 Programming environment ...................... 763 27.4.2 Communication mode......................764 27.4.3 Flash memory control ......................770 27.4.4 Selection of communication mode................... 771 27.4.5 Communication commands ..................... 772 27.4.6 Pin connection .........................
Page 18 Debugging Tools (Software)....................845 Embedded Software ......................846 Flash Memory Writing Tools ....................847 APPENDIX B MAJOR DIFFERENCES BETWEEN V850ES/JJ3 AND V850ES/JJ2 ..... 848 APPENDIX C REGISTER INDEX ......................850 APPENDIX D INSTRUCTION SET LIST ..................... 862 Conventions .......................... 862 Instruction Set (in Alphabetical Order) ................
Page 19: Chapter 1 Introduction
CHAPTER 1 INTRODUCTION The V850ES/JJ3 is one of the products in the NEC Electronics V850 single-chip microcontrollers designed for low- power operation for real-time control applications. General The V850ES/JJ3 is a 32-bit single-chip microcontroller that includes the V850ES CPU core and peripheral functions such as ROM/RAM, a timer/counter, serial interfaces, an A/D converter, and a D/A converter.
Page 20 CHAPTER 1 INTRODUCTION Table 1-1. V850ES/JJ3 Product List μ μ μ μ Part Number PD70F3743 PD70F3744 PD70F3745 PD70F3746 Internal Flash memory 384 KB 512 KB 768 KB 1024 KB memory 32 KB 40 KB 60 KB 60 KB Memory Logical space...
Page 21: Features
CHAPTER 1 INTRODUCTION Features Minimum instruction execution time: 31.25 ns (operating with main clock (f ) of 32 MHz) 32 bits × 32 registers General-purpose registers: Signed multiplication (16 × 16 → 32): 1 to 2 clocks CPU features: Signed multiplication (32 × 32 → 64): 1 to 5 clocks Saturated operations (overflow and underflow detection functions included) 32-bit shift instruction: 1 clock Bit manipulation instructions...
Page 22: Application Fields
144-pin plastic LQFP (fine pitch) (20 × 20) PD70F3744GJ-GAE-AX 512 KB μ 144-pin plastic LQFP (fine pitch) (20 × 20) PD70F3745GJ-GAE-AX 768 KB μ 144-pin plastic LQFP (fine pitch) (20 × 20) PD70F3746GJ-GAE-AX 1024 KB Remark The V850ES/JJ3 microcontrollers are lead-free products. User’s Manual U18376EJ3V0UD...
Page 23: Pin Configuration (Top View)
CHAPTER 1 INTRODUCTION Pin Configuration (Top View) 144-pin plastic LQFP (fine pitch) (20 × 20) μ μ PD70F3743GJ-GAE-AX PD70F3744GJ-GAE-AX μ μ PD70F3745GJ-GAE-AX PD70F3746GJ-GAE-AX PDL3/AD3 REF0 PDL2/AD2 P10/ANO0 PDL1/AD1 P11/ANO1 PDL0/AD0 REF1 P00/TIP61/TOP61 P01/TIP60/TOP60 PCT7 Note 1 FLMD0 PCT6/ASTB PCT5 Note 2 REGC PCT4/RD PCT3...
Page 24 CHAPTER 1 INTRODUCTION Pin names A0 to A23: Address bus Read strobe AD0 to AD15: Address/data bus REGC: Regulator control ADTRG: A/D trigger input RESET: Reset Analog input RTP00 to RTP05, ANI0 to ANI15: ANO0, ANO1: Analog output RTP10 to RTP15: Real-time output port ASCKA0: Asynchronous serial clock...
Page 25: Function Block Configuration
CHAPTER 1 INTRODUCTION Function Block Configuration 1.6.1 Internal block diagram INTC Instruction INTP0 to INTP8 Note 1 queue HLDRQ 16-bit timer/ TIQ00 to TIQ03 Multiplier HLDAK 32-bit barrel counter Q: 16 × 16 → 32 ASTB shifter TOQ00 to TOQ03 1 ch WAIT System...
Page 26: Internal Units
CHAPTER 1 INTRODUCTION 1.6.2 Internal units (1) CPU The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other instruction processing. Other dedicated on-chip hardware, such as a multiplier (16 bits × 16 bits → 32 bits) and a barrel shifter (32 bits) contribute to faster complex processing.
Page 27 Watchdog timer 2 generates a non-maskable interrupt request signal (INTWDT2) or a system reset signal (WDT2RES) after an overflow occurs. (11) Serial interface The V850ES/JJ3 includes three kinds of serial interfaces: asynchronous serial interface A (UARTA), 3-wire variable-length serial interface B (CSIB), and an I C bus interface (I In the case of UARTA, data is transferred via the TXDA0 to TXDA3 pins and RXDA0 to RXDA3 pins.
Page 28 CHAPTER 1 INTRODUCTION (19) Ports The general-purpose port functions and control pin functions are listed below. Port Alternate Function 7-bit I/O Timer I/O, NMI, external interrupt, A/D converter trigger, debug reset 2-bit I/O D/A converter analog output 10-bit I/O External interrupt, serial interface, timer I/O 3-bit I/O Serial interface 6-bit I/O...
Page 29: Chapter 2 Pin Functions
CHAPTER 2 PIN FUNCTIONS List of Pin Functions The names and functions of the pins of the V850ES/JJ3 are described below. There are three types of pin I/O buffer power supplies: AV , AV , and EV . The relationship between these...
Page 30 CHAPTER 2 PIN FUNCTIONS (1) Port pins (1/4) Pin Name Pin No. Function Alternate Function Port 0 TIP61/TOP61 7-bit I/O port TIP60/TOP60 Input/output can be specified in 1-bit units. N-ch open-drain output can be specified in 1-bit units. INTP0/ADTRG 5 V tolerant. INTP1 Note INTP2/DRST...
Page 31 CHAPTER 2 PIN FUNCTIONS (2/4) Pin Name Pin No. Function Alternate Function Port 6 RTP10 16-bit I/O port RTP11 Input/output can be specified in 1-bit units. RTP12 N-ch open-drain output can be specified in 1-bit units. RTP13 5 V tolerant. RTP14 RTP15 SIB5...
Page 32 CHAPTER 2 PIN FUNCTIONS (3/4) Pin Name Pin No. Function Alternate Function Port 9 A0/KR6/TXDA1/SDA02 16-bit I/O port A1/KR7/RXDA1/SCL02 Input/output can be specified in 1-bit units. A2/TIP41/TOP41 N-ch open-drain output can be specified in 1-bit units. A3/TIP40/TOP40 5 V tolerant. A4/TIP31/TOP31 A5/TIP30/TOP30 A6/TIP21/TOP21...
Page 33 CHAPTER 2 PIN FUNCTIONS (4/4) Pin Name Pin No. Function Alternate Function PCT0 Port CT 8-bit I/O port PCT1 Input/output can be specified in 1-bit units. − PCT2 − PCT3 PCT4 − PCT5 PCT6 ASTB − PCT7 PDH0 Port DH 8-bit I/O port PDH1 Input/output can be specified in 1-bit units.
Page 34 CHAPTER 2 PIN FUNCTIONS (2) Non-port pins (1/6) Pin Name Pin No. Function Alternate Function Output Address bus for external memory P90/KR6/TXDA1/SDA02 (when using separate bus) P91/KR7/RXDA1/SCL02 N-ch open-drain output selectable P92/TIP41/TOP41 5 V tolerant. P93/TIP40/TOP40 P94/TIP31/TOP31 P95/TIP30/TOP30 P96/TIP21/TOP21 P97/SIB1/TIP20/TOP20 P98/SOB1 P99/SCKB1 P910/SIB3...
Page 35 CHAPTER 2 PIN FUNCTIONS (2/6) Pin Name Pin No. Function Alternate Function ANI0 Input Analog voltage input for A/D converter ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7 ANI8 ANI9 ANI10 P710 ANI11 P711 ANI12 P712 ANI13 P713 ANI14 P714 ANI15 P715 ANO0 Output...
Page 36 CHAPTER 2 PIN FUNCTIONS (3/6) Pin Name Pin No. Function Alternate Function HLDAK Output Bus hold acknowledge output PCM2 HLDRQ Input Bus hold request input PCM3 INTP0 Input External interrupt request input (maskable, analog P03/ADTRG noise elimination). Analog noise elimination/digital INTP1 noise elimination selectable for the INTP3 pin.
Page 37 CHAPTER 2 PIN FUNCTIONS (4/6) Pin Name Pin No. Function Alternate Function RXDA0 Input Serial receive data input (UARTA0 to UARTA3) P31/INTP7/SIB4 5 V tolerant RXDA1 P91/A1/KR7/SCL02 RXDA2 P39/SCL00 RXDA3 P80/INTP8 SCKB0 Serial clock I/O (CSIB0 to CSIB5) N-ch open-drain output selectable SCKB1 P99/A9 5 V tolerant...
Page 38 CHAPTER 2 PIN FUNCTIONS (5/6) Pin Name Pin No. Function Alternate Function TIP41 Input Capture trigger input (TMP4), 5 V tolerant P92/A2/TOP41 External event count input/capture trigger input/external P915/A15/INTP6/TOP50 TIP50 trigger input (TMP5), 5 V tolerant TIP51 Capture trigger input (TMP5), 5 V tolerant P914/A14/INTP5/TOP51 TIP60 External event count input/capture trigger input/external...
Page 39 CHAPTER 2 PIN FUNCTIONS (6/6) Pin Name Pin No. Function Alternate Function − − Positive power supply pin for internal − − Ground potential for internal WAIT Input External wait input PCM0 Output Write strobe for external memory (lower 8 bits) PCT0 Write strove for external memory (higher 8 bits) PCT1...
Page 40: Pin States
CHAPTER 2 PIN FUNCTIONS Pin States The operation states of pins in the various modes are described below. Table 2-2. Pin Operation States in Various Modes Pin Name When Power During Reset HALT IDLE1, STOP Idle Bus Hold Note 2 Note 2 Note 3 Is Turned...
Page 41: Pin I/O Circuit Types, I/O Buffer Power Supplies And Connection Of Unused Pins
CHAPTER 2 PIN FUNCTIONS Pin I/O Circuit Types, I/O Buffer Power Supplies and Connection of Unused Pins (1/3) Alternate Function Pin No. I/O Circuit Type Recommended Connection TIP61/TOP61 10-D Input: Independently connect to EV via a resistor. TIP60/TOP60 Output: Leave open. INTP0/ADTRG INTP1 INTP2/DRST...
Page 42 CHAPTER 2 PIN FUNCTIONS (2/3) Alternate Function Pin No. I/O Circuit Type Recommended Connection P60 to P65 RTP10 to RTP15 43 to 48 10-G Input: Independently connect to EV via a resistor. SIB5 10-D Output: Leave open. SOB5 10-G SCKB5 10-D TIP70/TOP70 P610...
Page 43 CHAPTER 2 PIN FUNCTIONS (3/3) Alternate Function Pin No. I/O Circuit Type Recommended Connection PCT0, PCT1 WR0, WR1 95, 96 Input: Independently connect to EV via a resistor. − PCT2, PCT3 97, 98 Output: Leave open. PCT4 − PCT5 PCT6 ASTB −...
Page 44 CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuits Type 10-N Type 2 Data P-ch IN/OUT Open drain IN/OUT N-ch Output disable Note Schmitt-triggered input with hysteresis characteristics Input Type 5 enable N-ch OCDM0 bit Data P-ch Type 11-G Output N-ch REF0 disable...
Page 45: Cautions
CHAPTER 2 PIN FUNCTIONS Cautions When the power is turned on, the following pin may output an undefined level temporarily, even during reset. • P53/SIB2/KR3/TIQ00/TOQ00/RTP03/DDO pin User’s Manual U18376EJ3V0UD...
Page 46: Chapter 3 Cpu Function
CHAPTER 3 CPU FUNCTION The CPU of the V850ES/JJ3 is based on RISC architecture and executes almost all instructions with one clock by using a 5-stage pipeline. Features Minimum instruction execution time: 31.25 ns (at 32 MHz operation) μ 30.5 s (with subclock (f ) = 32.768 kHz operation)
Page 47: Cpu Register Set
CHAPTER 3 CPU FUNCTION CPU Register Set The registers of the V850ES/JJ3 can be classified into two types: general-purpose program registers and dedicated system registers. All the registers are 32 bits wide. For details, refer to the V850ES Architecture User's Manual.
Page 48: Program Register Set
CHAPTER 3 CPU FUNCTION 3.2.1 Program register set The program registers include general-purpose registers and a program counter. (1) General-purpose registers (r0 to r31) Thirty-two general-purpose registers, r0 to r31, are available. Any of these registers can be used to store a data variable or an address variable.
Page 49: System Register Set
CHAPTER 3 CPU FUNCTION 3.2.2 System register set The system registers control the status of the CPU and hold interrupt information. These registers can be read or written by using system register load/store instructions (LDSR and STSR), using the system register numbers listed below. Table 3-2.
Page 50 CHAPTER 3 CPU FUNCTION (1) Interrupt status saving registers (EIPC and EIPSW) EIPC and EIPSW are used to save the status when an interrupt occurs. If a software exception or a maskable interrupt occurs, the contents of the program counter (PC) are saved to EIPC, and the contents of the program status word (PSW) are saved to EIPSW (these contents are saved to the NMI status saving registers (FEPC and FEPSW) if a non-maskable interrupt occurs).
Page 51 CHAPTER 3 CPU FUNCTION (2) NMI status saving registers (FEPC and FEPSW) FEPC and FEPSW are used to save the status when a non-maskable interrupt (NMI) occurs. If an NMI occurs, the contents of the program counter (PC) are saved to FEPC, and those of the program status word (PSW) are saved to FEPSW.
Page 52 CHAPTER 3 CPU FUNCTION (4) Program status word (PSW) The program status word (PSW) is a collection of flags that indicate the status of the program (result of instruction execution) and the status of the CPU. If the contents of a bit of this register are changed by using the LDSR instruction, the new contents are validated immediately after completion of LDSR instruction execution.
Page 53 CHAPTER 3 CPU FUNCTION (2/2) Note The result of the operation that has performed saturation processing is determined by the contents of the OV and S flags. The SAT flag is set to 1 only when the OV flag is set to 1 when a saturation operation is performed.
Page 54 CHAPTER 3 CPU FUNCTION (6) Exception/debug trap status saving registers (DBPC and DBPSW) DBPC and DBPSW are exception/debug trap status registers. If an exception trap or debug trap occurs, the contents of the program counter (PC) are saved to DBPC, and those of the program status word (PSW) are saved to DBPSW.
Page 55: Operation Modes
In this mode, the internal flash memory can be programmed by using a flash programmer. (3) On-chip debug mode The V850ES/JJ3 is provided with an on-chip debug function that employs the JTAG (Joint Test Action Group) communication specifications. For details, see CHAPTER 28 ON-CHIP DEBUG FUNCTION.
Page 56: Address Space
CHAPTER 3 CPU FUNCTION Address Space 3.4.1 CPU address space For instruction addressing, up to a combined total of 16 MB of an external memory area and an internal ROM area, plus an internal RAM area, are supported in a linear address space (program space) of up to 64 MB. For operand addressing (data access), up to 4 GB of a linear address space (data space) is supported.
Page 57: Wraparound Of Cpu Address Space
CHAPTER 3 CPU FUNCTION 3.4.2 Wraparound of CPU address space (1) Program space Of the 32 bits of the PC (program counter), the higher 6 bits are fixed to 0 and only the lower 26 bits are valid. The higher 6 bits ignore a carry or borrow from bit 25 to 26 during branch address calculation. Therefore, the highest address of the program space, 03FFFFFFH, and the lowest address, 00000000H, are contiguous addresses.
Page 58: Memory Map
CHAPTER 3 CPU FUNCTION 3.4.3 Memory map The areas shown below are reserved in the V850ES/JJ3. Figure 3-2. Data Memory Map (Physical Addresses) 0 3 F F F F F F H 0 3 F F F F F F H...
Page 59 CHAPTER 3 CPU FUNCTION Figure 3-3. Program Memory Map 0 3 F F F F F F H Use prohibited (program fetch prohibited area) 0 3 F F F 0 0 0 H 0 3 F F E F F F H Internal RAM area (60 KB) 0 3 F F 0 0 0 0 H 0 3 F E F F F F H...
Page 60: Areas
CHAPTER 3 CPU FUNCTION 3.4.4 Areas (1) Internal ROM area Up to 1 MB is reserved as an internal ROM area. (a) Internal ROM (384 KB) μ 384 KB are allocated to addresses 00000000H to 0005FFFFH in the PD70F3743. Accessing addresses 00060000H to 000FFFFFH is prohibited. Figure 3-4.
Page 61 CHAPTER 3 CPU FUNCTION (c) Internal ROM (768 KB) μ 768 KB are allocated to addresses 00000000H to 000BFFFFH in the PD70F3745. Accessing addresses 000C0000H to 000FFFFFH is prohibited. Figure 3-6. Internal ROM Area (768 KB) 0 0 0 F F F F F H Access-prohibited area 0 0 0 C 0 0 0 0 H...
Page 62 CHAPTER 3 CPU FUNCTION (2) Internal RAM area Up to 60 KB are reserved as the internal RAM area. (a) Internal RAM (32 KB) μ 32 KB are allocated to addresses 03FF7000H to 03FFEFFFH in the PD70F3743. Accessing addresses 03FF0000H to 03FF6FFFH is prohibited. Figure 3-8.
Page 63 CHAPTER 3 CPU FUNCTION (c) Internal RAM (60 KB) μ 60 KB are allocated to addresses 03FF0000H to 03FFEFFFH in the PD70F3745 and 70F3746. Figure 3-10. Internal RAM Area (60 KB) Physical address space Logical address space 0 3 F F E F F F H F F F F E F F F H Internal RAM (60 KB)
Page 64 CHAPTER 3 CPU FUNCTION (3) On-chip peripheral I/O area 4 KB of addresses 03FFF000H to 03FFFFFFH are reserved as the on-chip peripheral I/O area. Figure 3-11. On-Chip Peripheral I/O Area Physical address space Logical address space 0 3 F F F F F F H F F F F F F F F H On-chip peripheral I/O area (4 KB)
Page 65: Recommended Use Of Address Space
(2) Data space With the V850ES/JJ3, it seems that there are sixty-four 64 MB address spaces on the 4 GB CPU address space. Therefore, the least significant bit (bit 25) of a 26-bit address is sign-extended to 32 bits and allocated as an address.
Page 66 CHAPTER 3 CPU FUNCTION (a) Application example of wraparound If R = r0 (zero register) is specified for the LD/ST disp16 [R] instruction, a range of addresses 00000000H ±32 KB can be addressed by sign-extended disp16. All the resources, including the internal hardware, can be addressed by one pointer.
Page 67 CHAPTER 3 CPU FUNCTION Figure 3-12. Recommended Memory Map Program space Data space F F F F F F F F H On-chip peripheral I/O F F F F F 0 0 0 H F F F F E F F F H Internal RAM F F F F F F F F H F F F F 0 0 0 0 H...
Page 68: Peripheral I/O Registers
CHAPTER 3 CPU FUNCTION 3.4.6 Peripheral I/O registers (1/12) Address Function Register Name Symbol Manipulatable Bits Default Value √ Note FFFFF004H Port DL register 0000H √ √ Note FFFFF004H Port DLL register PDLL √ √ Note FFFFF005H Port DLH register PDLH √...
Page 69 CHAPTER 3 CPU FUNCTION (2/12) Address Function Register Name Symbol Manipulatable Bits Default Value √ FFFFF0C2H DMA transfer count register 1 DBC1 Undefined √ FFFFF0C4H DMA transfer count register 2 DBC2 Undefined √ FFFFF0C6H DMA transfer count register 3 DBC3 Undefined √...
Page 70 CHAPTER 3 CPU FUNCTION (3/12) Address Function Register Name Symbol Manipulatable Bits Default Value √ √ FFFFF132H Interrupt control register TP1OVIC √ √ FFFFF134H Interrupt control register TP1CCIC0 √ √ FFFFF136H Interrupt control register TP1CCIC1 √ √ FFFFF138H Interrupt control register TP2OVIC √...
Page 71 CHAPTER 3 CPU FUNCTION (4/12) Address Function Register Name Symbol Manipulatable Bits Default Value √ √ FFFFF198H Interrupt control register TP7CCIC0 √ √ FFFFF19AH Interrupt control register TP7CCIC1 √ √ FFFFF19CH Interrupt control register TP8OVIC √ √ FFFFF19EH Interrupt control register TP8CCIC0 √...
Page 72 CHAPTER 3 CPU FUNCTION (5/12) Address Function Register Name Symbol Manipulatable Bits Default Value √ FFFFF228H A/D conversion result register 12 ADA0CR12 Undefined √ FFFFF229H A/D conversion result register 12H ADA0CR12H Undefined √ FFFFF22AH A/D conversion result register 13 ADA0CR13 Undefined √...
Page 73 CHAPTER 3 CPU FUNCTION (6/12) Address Function Register Name Symbol Manipulatable Bits Default Value √ √ FFFFF422H Port 1 mode register √ FFFFF426H Port 3 mode register FFFFH √ √ FFFFF426H Port 3 mode register L PM3L √ √ FFFFF427H Port 3 mode register H PM3H √...
Page 74 CHAPTER 3 CPU FUNCTION (7/12) Address Function Register Name Symbol Manipulatable Bits Default Value √ √ FFFFF540H TMQ0 control register 0 TQ0CTL0 √ √ FFFFF541H TMQ0 control register 1 TQ0CTL1 √ √ FFFFF542H TMQ0 I/O control register 0 TQ0IOC0 √ √...
Page 75 CHAPTER 3 CPU FUNCTION (8/12) Address Function Register Name Symbol Manipulatable Bits Default Value √ √ FFFFF5C5H TMP3 option register 0 TP3OPT0 √ FFFFF5C6H TMP3 capture/compare register 0 TP3CCR0 0000H √ FFFFF5C8H TMP3 capture/compare register 1 TP3CCR1 0000H √ FFFFF5CAH TMP3 counter read buffer register TP3CNT 0000H...
Page 76 CHAPTER 3 CPU FUNCTION (9/12) Address Function Register Name Symbol Manipulatable Bits Default Value √ √ FFFFF612H TMP8 I/O control register 0 TP8IOC0 √ √ FFFFF613H TMP8 I/O control register 1 TP8IOC1 √ √ FFFFF614H TMP8 I/O control register 2 TP8IOC2 √...
Page 77 CHAPTER 3 CPU FUNCTION (10/12) Address Function Register Name Symbol Manipulatable Bits Default Value √ FFFFF891H Low-voltage detection level select register LVIS √ √ FFFFF892H Internal RAM data status register RAMS √ √ FFFFF8B0H Prescaler mode register 0 PRSM0 √ FFFFF8B1H Prescaler compare register 0 PRSCM0...
Page 78 CHAPTER 3 CPU FUNCTION (11/12) Address Function Register Name Symbol Manipulatable Bits Default Value √ √ FFFFFC60H Port 0 function register √ FFFFFC66H Port 3 function register 0000H √ √ FFFFFC66H Port 3 function register L PF3L √ √ FFFFFC67H Port 3 function register H PF3H √...
Page 79 CHAPTER 3 CPU FUNCTION (12/12) Address Function Register Name Symbol Manipulatable Bits Default Value √ FFFFFD36H CSIB3 transmit data register CB3TX 0000H √ FFFFFD36H CSIB3 transmit data register L CB3TXL √ √ FFFFFD40H CSIB4 control register 0 CB4CTL0 √ √ FFFFFD41H CSIB4 control register 1 CB4CTL1...
Page 80: Special Registers
3.4.7 Special registers Special registers are registers that are protected from being written with illegal data due to a program hang-up. The V850ES/JJ3 has the following eight special registers. • Power save control register (PSC) • Clock control register (CKC) •...
Page 81 CHAPTER 3 CPU FUNCTION (1) Setting data to special registers Set data to the special registers in the following sequence. <1> Disable DMA operation. <2> Prepare data to be set to the special register in a general-purpose register. <3> Write the data prepared in <2> to the PRCMD register. <4>...
Page 82 CHAPTER 3 CPU FUNCTION (2) Command register (PRCMD) The PRCMD register is an 8-bit register that protects the registers that may seriously affect the application system from being written, so that the system does not inadvertently stop due to a program hang-up. The first write access to a special register is valid after data has been written in advance to the PRCMD register.
Page 83 CHAPTER 3 CPU FUNCTION (3) System status register (SYS) Status flags that indicate the operation status of the overall system are allocated to this register. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: Address: FFFFF802H...
Page 84: Cautions
The VSWC register controls wait of bus access to the on-chip peripheral I/O registers. Three clocks are required to access an on-chip peripheral I/O register (without a wait cycle). The V850ES/JJ3 requires wait cycles according to the operating frequency. Set the following value to the VSWC register in accordance with the frequency used.
Page 85 CHAPTER 3 CPU FUNCTION (2) Accessing specific on-chip peripheral I/O registers This product has two types of internal system buses. One is a CPU bus and the other is a peripheral bus that interfaces with low-speed peripheral hardware. The clock of the CPU bus and the clock of the peripheral bus are asynchronous. If an access to the CPU and an access to the peripheral hardware conflict, therefore, unexpected illegal data may be transferred.
Page 86 CHAPTER 3 CPU FUNCTION (3) Restriction on conflict between sld instruction and interrupt request (a) Description If a conflict occurs between the decode operation of an instruction in <2> immediately before the sld instruction following an instruction in <1> and an interrupt request before the instruction in <1> is complete, the execution result of the instruction in <1>...
Page 87: Chapter 4 Port Functions
Input/output specifiable in 1-bit units Basic Port Configuration The V850ES/JJ3 features a total of 128 I/O ports consisting of ports 0, 1, 3 to 9, CD, CM, CS, CT, DH, and DL. The port configuration is shown below. Figure 4-1. Port Configuration Diagram...
Page 88: Port Configuration
CHAPTER 4 PORT FUNCTIONS Port Configuration Table 4-2. Port Configuration Item Configuration Control register Port n mode register (PMn: n = 0, 1, 3 to 9, CD, CM, CS, CT, DH, DL) Port n mode control register (PMCn: n = 0, 3 to 6, 8, 9, CM, CS, CT, DH, DL) Port n function control register (PFCn: n = 0, 3 to 6, 9) Port n function control expansion register (PFCEn: n = 3, 5, 9) Port n function register (PFn: n = 0, 3 to 6, 8, 9)
Page 89 CHAPTER 4 PORT FUNCTIONS (2) Port n mode register (PMn) The PMn register specifies the input or output mode of the corresponding port pin. Each bit of this register corresponds to one pin of port n, and the input or output mode can be specified in 1-bit units.
Page 90 CHAPTER 4 PORT FUNCTIONS (4) Port n function control register (PFCn) The PFCn register specifies the alternate function of a port pin to be used if the pin has two alternate functions. Each bit of this register corresponds to one pin of port n, and the alternate function of a port pin can be specified in 1-bit units.
Page 91 CHAPTER 4 PORT FUNCTIONS (6) Port n function register (PFn) The PFn register specifies normal output or N-ch open-drain output. Each bit of this register corresponds to one pin of port n, and the output mode of the port pin can be specified in 1-bit units.
Page 92 CHAPTER 4 PORT FUNCTIONS (7) Port setting Set a port as illustrated below. Figure 4-2. Setting of Each Register and Pin Function Port mode Output mode “0” PMn register Input mode “1” Alternate function (when two alternate functions are available) “0”...
Page 93: Port 0
CHAPTER 4 PORT FUNCTIONS 4.3.1 Port 0 Port 0 is a 7-bit port for which I/O settings can be controlled in 1-bit units. Port 0 includes the following alternate-function pins. Table 4-4. Port 0 Alternate-Function Pins Pin Name Pin No. Alternate-Function Pin Name Remark Block Type...
Page 94 CHAPTER 4 PORT FUNCTIONS (2) Port 0 mode register (PM0) After reset: FFH Address: FFFFF420H PM06 PM05 PM04 PM03 PM02 PM01 PM00 PM0n I/O mode control (n = 0 to 6) Output mode Input mode User’s Manual U18376EJ3V0UD...
Page 95 CHAPTER 4 PORT FUNCTIONS (3) Port 0 mode control register (PMC0) After reset: 00H Address: FFFFF440H PMC0 PMC06 PMC05 PMC04 PMC03 PMC02 PMC01 PMC00 PMC06 Specification of P06 pin operation mode I/O port INTP3 input PMC05 Specification of P05 pin operation mode I/O port INTP2 input PMC04...
Page 96 CHAPTER 4 PORT FUNCTIONS (4) Port 0 function control register (PFC0) After reset: 00H Address: FFFFF460H PFC0 PFC03 PFC01 PFC00 PFC03 Specification of P03 pin alternate function INTP0 input ADTRG input PFC01 Specification of P01 pin alternate function TIP60 input TOP60 output PFC00 Specification of P00 pin alternate function...
Page 97: Port 1
CHAPTER 4 PORT FUNCTIONS 4.3.2 Port 1 Port 1 is a 2-bit port for which I/O settings can be controlled in 1-bit units. Port 1 includes the following alternate-function pins. Table 4-5. Port 1 Alternate-Function Pins Pin Name Pin No. Alternate-Function Pin Name Remark Block Type...
Page 98: Port 3
CHAPTER 4 PORT FUNCTIONS 4.3.3 Port 3 Port 3 is a 10-bit port for which I/O settings can be controlled in 1-bit units. Port 3 includes the following alternate-function pins. Table 4-6. Port 3 Alternate-Function Pins Pin Name Pin No. Alternate-Function Pin Name Remark Block Type...
Page 99 CHAPTER 4 PORT FUNCTIONS (1) Port 3 register (P3) After reset: 0000H (output latch) Address: P3 FFFFF406H, P3L FFFFF406H, P3H FFFFF407H P3 (P3H) (P3L) Output data control (in output mode) (n = 0 to 9) Outputs 0 Outputs 1 Remarks 1. The P3 register can be read or written in 16-bit units. However, when using the higher 8 bits of the P3 register as the P3H register and the lower 8 bits as the P3L register, P3 can be read or written in 8-bit or 1-bit units.
Page 100 CHAPTER 4 PORT FUNCTIONS (3) Port 3 mode control register (PMC3) After reset: 0000H Address: PMC3 FFFFF446H, PMC3L FFFFF446H, PMC3H FFFFF447H PMC3 (PMC3H) PMC39 PMC38 (PMC3L) PMC35 PMC34 PMC33 PMC32 PMC31 PMC30 PMC39 Specification of P39 pin operation mode I/O port RXDA2 input/SCL00 I/O PMC38 Specification of P38 pin operation mode...
Page 101 CHAPTER 4 PORT FUNCTIONS (4) Port 3 function control register (PFC3) After reset: 0000H Address: PFC3 FFFFF466H, PFC3L FFFFF466H, PFC3L FFFFF467H PFC3 (PFC3H) PFC39 PFC38 (PFC3L) PFC35 PFC34 PFC33 PFC32 PFC31 PFC30 Remarks 1. For details of alternate function specification, see 4.3.3 (6) Port 3 alternate function specifications.
Page 102 CHAPTER 4 PORT FUNCTIONS (6) Port 3 alternate function specifications PFC39 Specification of P39 pin alternate function RXDA2 input SCL00 input PFC38 Specification of P38 pin alternate function TXDA2 output SDA00 I/O PFC35 Specification of P35 pin alternate function TIP11 input TOP11 output PFC34 Specification of P34 pin alternate function...
Page 103 CHAPTER 4 PORT FUNCTIONS (7) Port 3 function register (PF3) After reset: 0000H Address: PF3 FFFFFC66H, PF3L FFFFFC66H, PF3H FFFFFC67H PF3 (PF3H) PF39 PF38 (PF3L) PF37 PF36 PF35 PF34 PF33 PF32 PF31 PF30 PF3n Control of normal output or N-ch open-drain output (n = 0 to 9) Normal output (CMOS output) N-ch open-drain output Caution When an output pin is pulled up at EV...
Page 104: Port 4
CHAPTER 4 PORT FUNCTIONS 4.3.4 Port 4 Port 4 is a 3-bit port that controls I/O in 1-bit units. Port 4 includes the following alternate-function pins. Table 4-7. Port 4 Alternate-Function Pins Pin Name Pin No. Alternate-Function Pin Name Remark Block Type SIB0/SDA01 Selectable as N-ch open-drain output...
Page 105 CHAPTER 4 PORT FUNCTIONS (3) Port 4 mode control register (PMC4) After reset: 00H Address: FFFFF448H PMC4 PMC42 PMC41 PMC40 PMC42 Specification of P42 pin operation mode I/O port SCKB0 I/O PMC41 Specification of P41 pin operation mode I/O port SOB0 output/SCL01 I/O PMC40 Specification of P40 pin operation mode...
Page 106: Port 5
CHAPTER 4 PORT FUNCTIONS 4.3.5 Port 5 Port 5 is a 6-bit port that controls I/O in 1-bit units. Port 5 includes the following alternate-function pins. Table 4-8. Port 5 Alternate-Function Pins Pin Name Pin No. Alternate-Function Pin Name Remark Block Type TIQ01/KR0/TOQ01/RTP00 Selectable as N-ch open-drain output...
Page 107 CHAPTER 4 PORT FUNCTIONS (3) Port 5 mode control register (PMC5) After reset: 00H Address: FFFFF44AH PMC5 PMC55 PMC54 PMC53 PMC52 PMC51 PMC50 PMC55 Specification of P55 pin operation mode I/O port SCKB2 I/O/KR5 input/RTP05 output PMC54 Specification of P54 pin operation mode I/O port SOB2 output/KR4 input/RTP04 output PMC53...
Page 108 CHAPTER 4 PORT FUNCTIONS (5) Port 5 function control expansion register (PFCE5) After reset: 00H Address: FFFFF70AH PFCE5 PFCE55 PFCE54 PFCE53 PFCE52 PFCE51 PFCE50 Remark For details of alternate function specification, see 4.3.5 (6) Port 5 alternate function specifications. (6) Port 5 alternate function specifications PFCE55 PFC55 Specification of P55 pin alternate function...
Page 109 CHAPTER 4 PORT FUNCTIONS PFCE50 PFC50 Specification of P50 pin alternate function Setting prohibited Note TIQ01 input/KR0 input TOQ01 output RTP00 output Note The KRn pin and TIQ0m pin are alternate-function pins. When using the pin as the TIQ0m pin, disable KRn pin key return detection, which is the alternate function.
Page 110: Port 6
CHAPTER 4 PORT FUNCTIONS 4.3.6 Port 6 Port 6 is a 16-bit port for which I/O settings can be controlled in 1-bit units. Port 6 includes the following alternate-function pins. Table 4-9. Port 6 Alternate-Function Pins Pin Name Pin No. Alternate-Function Pin Name Remark Block Type...
Page 111 CHAPTER 4 PORT FUNCTIONS (1) Port 6 register (P6) After reset: 0000H (output latch) Address: P6 FFFFF40CH P6L FFFFF40CH, P6LH FFFFF40DH P6 (P6H) P615 P614 P613 P612 P611 P610 (P6L) Output data control (in output mode) (n = 0 to 15) Outputs 0 Outputs 1 Remarks 1.
Page 112 CHAPTER 4 PORT FUNCTIONS (3) Port 6 mode control register (PMC6) After reset: 0000H Address: PMC6 FFFFF44CH PMC6L FFFFF44CH, PMC6H FFFFF44DH PMC6 (PMC6H) PMC613 PMC612 PMC611 PMC610 PMC69 PMC68 PMC67 PMC66 PMC65 PMC64 PMC63 PMC62 PMC61 PMC60 (PMC6L) PMC613 Specification of P613 pin operation mode I/O port TIP81 input/TOP81 output PMC612...
Page 113 CHAPTER 4 PORT FUNCTIONS (4) Port 6 function control register H (PFC6H) After reset: 00H Address: FFFFF46DH PFC6H PFC613 PFC612 PFC69 PFC613 Specification of P613 pin alternate function TIP81 input TOP81 output PFC612 Specification of P612 pin alternate function TIP80 input TOP80 output PFC69 Specification of P69 pin alternate function...
Page 114: Port 7
CHAPTER 4 PORT FUNCTIONS 4.3.7 Port 7 Port 7 is a 16-bit port for which I/O settings can be controlled in 1-bit units. Port 7 includes the following alternate-function pins. Table 4-10. Port 7 Alternate-Function Pins Pin Name Pin No. Alternate-Function Pin Name Remark Block Type...
Page 115 CHAPTER 4 PORT FUNCTIONS (1) Port 7 register H, port 7 register L (P7H, P7L) After reset: 00H (output latch) Address: P7L FFFFF40EH, P7H FFFFF40FH P715 P714 P713 P712 P711 P710 Output data control (in output mode) (n = 0 to 15) Outputs 0 Outputs 1 Caution Do not read or write the P7H and P7L registers during A/D conversion (see 13.6 (4)
Page 116: Port 8
CHAPTER 4 PORT FUNCTIONS 4.3.8 Port 8 Port 8 is a 2-bit port for which I/O settings can be controlled in 1-bit units. Port 8 includes the following alternate-function pins. Table 4-11. Port 8 Alternate-Function Pins Pin Name Pin No. Alternate-Function Pin Name Remark Block Type...
Page 117 CHAPTER 4 PORT FUNCTIONS (3) Port 8 mode control register (PMC8) After reset: 00H Address: FFFFF450H PMC8 PMC81 PMC80 PMC81 Specification of P81 pin operation mode I/O port TXDA3 output PMC80 Specification of P80 pin operation mode I/O port Note RXDA3 input/INTP8 input Note The INTP8 and RXDA3 pins are alternate-function pins.
Page 118: Port 9
CHAPTER 4 PORT FUNCTIONS 4.3.9 Port 9 Port 9 is a 16-bit port for which I/O settings can be controlled in 1-bit units. Port 9 includes the following alternate-function pins. Table 4-12. Port 9 Alternate-Function Pins Pin Name Pin No. Alternate-Function Pin Name Remark Block Type...
Page 119 CHAPTER 4 PORT FUNCTIONS (1) Port 9 register (P9) After reset: 0000H (output latch) Address: P9 FFFFF412H, P9L FFFFF412H, P9H FFFFF413H P9 (P9H) P915 P914 P913 P912 P911 P910 (P9L) Output data control (in output mode) (n = 0 to 15) Outputs 0 Outputs 1 Remarks 1.
Page 120 CHAPTER 4 PORT FUNCTIONS (3) Port 9 mode control register (PMC9) (1/2) After reset: 0000H Address: PMC9 FFFFF452H, PMC9L FFFFF452H, PMC9H FFFFF453H PMC9 (PMC9H) PMC915 PMC914 PMC913 PMC912 PMC911 PMC910 PMC99 PMC98 (PMC9L) PMC97 PMC96 PMC95 PMC94 PMC93 PMC92 PMC91 PMC90 PMC915 Specification of P915 pin operation mode...
Page 121 CHAPTER 4 PORT FUNCTIONS (2/2) PMC97 Specification of P97 pin operation mode I/O port A7 output/SIB1 input/TIP20 input/TOP20 output PMC96 Specification of P96 pin operation mode I/O port A6 output/TIP21 input/TOP21 output PMC95 Specification of P95 pin operation mode I/O port A5 output/TIP30 input/TOP30 output PMC94 Specification of P94 pin operation mode...
Page 122 CHAPTER 4 PORT FUNCTIONS (4) Port 9 function control register (PFC9) Caution When performing separate address bus output (A0 to A15), set the PMC9 register to FFFFH for all 16 bits at once after clearing the PFC9 or PFCE9 register to 0000H. After reset: 0000H Address: PFC9 FFFFF472H, PFC9L FFFFF472H, PFC9H FFFFF473H...
Page 123 CHAPTER 4 PORT FUNCTIONS (6) Port 9 alternate function specifications PFCE915 PFC915 Specification of P915 pin alternate function A15 output INTP6 input TIP50 input TOP50 output PFCE914 PFC914 Specification of P914 pin alternate function A14 output INTP5 input TIP51 input TOP51 output PFC913 Specification of P913 pin alternate function...
Page 124 CHAPTER 4 PORT FUNCTIONS PFCE96 PFC96 Specification of P96 pin alternate function A6 output Setting prohibited TIP21 input TOP21 output PFCE95 PFC95 Specification of P95 pin alternate function A5 output TIP30 input TOP30 output Setting prohibited PFCE94 PFC94 Specification of P94 pin alternate function A4 output TIP31 input TOP31 output...
Page 125 CHAPTER 4 PORT FUNCTIONS (7) Port 9 function register (PF9) After reset: 0000H Address: PF3 FFFFFC72H, PF9L FFFFFC72H, PF9H FFFFFC73H PF9 (PF9H) PF915 PF914 PF913 PF912 PF911 PF910 PF99 PF98 (PF9L) PF97 PF96 PF95 PF94 PF93 PF92 PF91 PF90 PF9n Control of normal output or N-ch open-drain output (n = 0 to 15) Normal output (CMOS output) N-ch open-drain output...
Page 126: Port Cd
CHAPTER 4 PORT FUNCTIONS 4.3.10 Port CD Port CD is a 4-bit port for which I/O settings can be controlled in 1-bit units. Port CD includes the following alternate-function pins. Table 4-13. Port CD Alternate-Function Pins Pin Name Pin No. Alternate-Function Pin Name Remark Block Type...
Page 127: Port Cm
CHAPTER 4 PORT FUNCTIONS 4.3.11 Port CM Port CM is a 6-bit port for which I/O settings can be controlled in 1-bit units. Port CM includes the following alternate-function pins. Table 4-14. Port CM Alternate-Function Pins Pin Name Pin No. Alternate-Function Pin Name Remark Block Type...
Page 128 CHAPTER 4 PORT FUNCTIONS (3) Port CM mode control register (PMCCM) After reset: 00H Address: FFFFF04CH PMCCM PMCCM3 PMCCM2 PMCCM1 PMCCM0 PMCCM3 Specification of PCM3 pin operation mode I/O port HLDRQ input PMCCM2 Specification of PCM2 pin operation mode I/O port HLDAK output PMCCM1 Specification of PCM1 pin operation mode...
Page 129: Port Cs
CHAPTER 4 PORT FUNCTIONS 4.3.12 Port CS Port CS is an 8-bit port for which I/O settings can be controlled in 1-bit units. Port CS includes the following alternate-function pins. Table 4-15. Port CS Alternate-Function Pins Pin Name Pin No. Alternate-Function Pin Name Remark Block Type...
Page 130 CHAPTER 4 PORT FUNCTIONS (3) Port CS mode control register (PMCCS) After reset: 00H Address: FFFFF048H PMCCS PMCCS3 PMCCS2 PMCCS1 PMCCS0 PMCCS3 Specification of PCS3 pin operation mode I/O port CS3 output PMCCS2 Specification of PCS2 pin operation mode I/O port CS2 output PMCCS1 Specification of PCS1 pin operation mode...
Page 131: Port Ct
CHAPTER 4 PORT FUNCTIONS 4.3.13 Port CT Port CT is an 8-bit port for which I/O settings can be controlled in 1-bit units. Port CT includes the following alternate-function pins. Table 4-16. Port CT Alternate-Function Pins Pin Name Pin No. Alternate-Function Pin Name Remark Block Type...
Page 132 CHAPTER 4 PORT FUNCTIONS (3) Port CT mode control register (PMCCT) After reset: 00H Address: FFFFF04AH PMCCT PMCCT6 PMCCT4 PMCCT1 PMCCT0 PMCCT6 Specification of PCT6 pin operation mode I/O port ASTB output PMCCT4 Specification of PCT4 pin operation mode I/O port RD output PMCCT1 Specification of PCT1 pin operation mode...
Page 133: Port Dh
CHAPTER 4 PORT FUNCTIONS 4.3.14 Port DH Port DH is an 8-bit port for which I/O settings can be controlled in 1-bit units. Port DH includes the following alternate-function pins. Table 4-17. Port DH Alternate-Function Pins Pin Name Pin No. Alternate-Function Pin Name Remark Block Type...
Page 134 CHAPTER 4 PORT FUNCTIONS (3) Port DH mode control register (PMCDH) After reset: 00H Address: FFFFF046H PMCDH PMCDH7 PMCDH6 PMCDH5 PMCDH4 PMCDH3 PMCDH2 PMCDH1 PMCDH0 PMCDHn Specification of PDHn pin operation mode (n = 0 to 7) I/O port Am output (address bus output) (m = 16 to 23) User’s Manual U18376EJ3V0UD...
Page 135: Port Dl
CHAPTER 4 PORT FUNCTIONS 4.3.15 Port DL Port DL is a 16-bit port for which I/O settings can be controlled in 1-bit units. Port DL includes the following alternate-function pins. Table 4-18. Port DL Alternate-Function Pins Pin Name Pin No. Alternate-Function Pin Name Remark Block Type...
Page 136 CHAPTER 4 PORT FUNCTIONS (1) Port DL register (PDL) After reset: 0000H (output latch) Address: PDL FFFFF004H, PDLL FFFFF004H, PDLH FFFFF005H PDL (PDLH) PDL15 PDL14 PDL13 PDL12 PDL11 PDL10 PDL9 PDL8 (PDLL) PDL7 PDL6 PDL5 PDL4 PDL3 PDL2 PDL1 PDL0 PDLn Output data control (in output mode) (n = 0 to 15) Outputs 0...
Page 137 CHAPTER 4 PORT FUNCTIONS (3) Port DL mode control register (PMCDL) After reset: 0000H Address: PMCDL FFFFF044H, PMCDLL FFFFF044H, PMCDLH FFFFF045H PMCDL (PMCDLH) PMCDL15 PMCDL14PMCDL13 PMCDL12 PMCDL11PMCDL10 PMCDL9 PMCDL8 (PMCDLL) PMCDL7 PMCDL6 PMCDL5 PMCDL4 PMCDL3 PMCDL2 PMCDL1 PMCDL0 PMCDLn Specification of PDLn pin operation mode (n = 0 to 15) I/O port ADn I/O (address/data bus I/O) Caution When the SMSEL bit of the EXIMC register = 1 (separate mode) and the BS30 to BS00 bits...
Page 138: Block Diagrams
CHAPTER 4 PORT FUNCTIONS Block Diagrams Figure 4-3. Block Diagram of Type A-1 PMmn PORT Address P-ch A/D input signal N-ch User’s Manual U18376EJ3V0UD...
Page 139 CHAPTER 4 PORT FUNCTIONS Figure 4-4. Block Diagram of Type A-2 PMmn PORT Address P-ch D/A output signal N-ch Figure 4-5. Block Diagram of Type B-1 PMmn PORT Address User’s Manual U18376EJ3V0UD...
Page 140 CHAPTER 4 PORT FUNCTIONS Figure 4-6. Block Diagram of Type C-1 PFmn PMmn PORT P-ch N-ch Address User’s Manual U18376EJ3V0UD...
Page 141 CHAPTER 4 PORT FUNCTIONS Figure 4-7. Block Diagram of Type D-1 PMCmn PMmn PORT Address Input signal when alternate function is used User’s Manual U18376EJ3V0UD...
Page 142 CHAPTER 4 PORT FUNCTIONS Figure 4-8. Block Diagram of Type D-2 PMCmn PMmn Output signal when alternate function is used PORT Address User’s Manual U18376EJ3V0UD...
Page 143 CHAPTER 4 PORT FUNCTIONS Figure 4-9. Block Diagram of Type D-3 PMCmn Output enable signal of address/data bus Output buffer off signal PMmn Output signal when alternate function is used PORT Address Input enable signal of address/data bus Input signal when alternate function is used User’s Manual U18376EJ3V0UD...
Page 144 CHAPTER 4 PORT FUNCTIONS Figure 4-10. Block Diagram of Type E-1 PFmn PMCmn PMmn PORT P-ch N-ch Note Address Input signal when alternate function is used Note Hysteresis characteristics are not available in port mode. User’s Manual U18376EJ3V0UD...
Page 145 CHAPTER 4 PORT FUNCTIONS Figure 4-11. Block Diagram of Type E-2 PFmn PMCmn PMmn Output signal when alternate function is used PORT P-ch N-ch Address User’s Manual U18376EJ3V0UD...
Page 146 CHAPTER 4 PORT FUNCTIONS Figure 4-12. Block Diagram of Type E-3 PFmn Output enable signal when alternate function is used PMCmn PMmn Output signal when alternate function is used PORT P-ch N-ch Note Address Input signal when alternate function is used Note Hysteresis characteristics are not available in port mode.
Page 147 CHAPTER 4 PORT FUNCTIONS Figure 4-13. Block Diagram of Type G-1 PFmn PFCmn PMCmn PMmn Output signal when alternate function is used PORT P-ch N-ch Note Address Input signal when alternate function is used Note Hysteresis characteristics are not available in port mode. User’s Manual U18376EJ3V0UD...
Page 148 CHAPTER 4 PORT FUNCTIONS Figure 4-14. Block Diagram of Type G-2 PFmn PFCmn PMCmn PMmn Output signal when alternate function is used PORT P-ch N-ch Note Address Input signal when alternate function is used Note Hysteresis characteristics are not available in port mode. User’s Manual U18376EJ3V0UD...
Page 149 CHAPTER 4 PORT FUNCTIONS Figure 4-15. Block Diagram of Type G-3 PFmn PFCmn PMCmn PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used P-ch PORT N-ch Address User’s Manual U18376EJ3V0UD...
Page 150 CHAPTER 4 PORT FUNCTIONS Figure 4-16. Block Diagram of Type G-5 PFmn Output enable signal when alternate function is used PFCmn PMCmn PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used P-ch PORT N-ch Address...
Page 151 CHAPTER 4 PORT FUNCTIONS Figure 4-17. Block Diagram of Type G-6 PFmn PFCmn PMCmn PMmn Output signal when alternate function is used P-ch PORT N-ch Note Address Input signal 1 when alternate function is used Input signal 2 when alternate function is used Note Hysteresis characteristics are not available in port mode.
Page 152 CHAPTER 4 PORT FUNCTIONS Figure 4-18. Block Diagram of Type G-12 PFmn PFCmn PMCmn PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used P-ch PORT N-ch Note Address Input signal when alternate function is used Note Hysteresis characteristics are not available in port mode.
Page 153 CHAPTER 4 PORT FUNCTIONS Figure 4-19. Block Diagram of Type L-1 PFmn INTR Note 1 INTRmn INTF Note 1 INTFmn PMCmn PMmn PORT P-ch N-ch Note 2 Address Input signal 1 when Edge Noise detection elimination alternate function is used Notes 1.
Page 154 CHAPTER 4 PORT FUNCTIONS Figure 4-20. Block Diagram of Type L-2 PFmn INTR Note 1 INTRmn INTF Note 1 INTFmn PMCmn PMmn PORT P-ch N-ch Note 2 Address Input signal 1-1 when Edge Noise alternate function is used detection elimination Input signal 1-2 when alternate function is used Notes 1.
Page 155 CHAPTER 4 PORT FUNCTIONS Figure 4-21. Block Diagram of Type N-1 PFmn INTR Note 1 INTRmn INTF Note 1 INTFmn PFCmn PMCmn PMmn PORT P-ch N-ch Note 2 Address Input signal 1 when Edge Noise alternate function is used detection elimination Input signal 2 when alternate function is used...
Page 156 CHAPTER 4 PORT FUNCTIONS Figure 4-22. Block Diagram of Type N-2 PFmn INTR Note 1 INTRmn INTF Note 1 INTFmn PFCmn PMCmn PMmn Output signal when alternate function is used PORT P-ch N-ch Note 2 Address Input signal when Edge Noise alternate function is used detection...
Page 157 CHAPTER 4 PORT FUNCTIONS Figure 4-23. Block Diagram of Type N-3 PFmn INTR Note 1 INTRmn INTF Note 1 INTFmn PFCmn PMCmn PMmn PORT P-ch N-ch Note 2 Address Input signal 1-1 when Edge Noise alternate function is used detection elimination Input signal 1-2 when alternate function is used...
Page 158 CHAPTER 4 PORT FUNCTIONS Figure 4-24. Block Diagram of Type U-1 PFmn Output enable signal when alternate PFCE function is used PFCEmn PFCmn PMCmn PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used PORT P-ch N-ch...
Page 159 CHAPTER 4 PORT FUNCTIONS Figure 4-25. Block Diagram of Type U-5 PFmn PFCE PFCEmn PFCmn PMCmn PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used P-ch PORT N-ch Note Address Input signal 1-1 when alternate function is used Input signal 1-2 when Noise...
Page 160 CHAPTER 4 PORT FUNCTIONS Figure 4-26. Block Diagram of Type U-6 PFmn OCDM0 OCDM0 PFCE PFCEmn PFCmn PMCmn PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used P-ch PORT N-ch Note Address Input signal 1-1 when alternate function is used Noise...
Page 161 CHAPTER 4 PORT FUNCTIONS Figure 4-27. Block Diagram of Type U-7 PFmn OCDM0 OCDM0 PFCE PFCEmn PFCmn PMCmn PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used Output signal when on-chip debugging P-ch PORT N-ch...
Page 162 CHAPTER 4 PORT FUNCTIONS Figure 4-28. Block Diagram of Type U-8 PFmn OCDM0 OCDM0 PFCE PFCEmn PFCmn PMCmn PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used P-ch PORT N-ch Address Note Input signal when Noise alternate function is used...
Page 163 CHAPTER 4 PORT FUNCTIONS Figure 4-29. Block Diagram of Type U-9 PFmn OCDM0 OCDM0 Output enable signal when alternate function is used PFCE PFCEmn PFCmn PMCmn PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used P-ch PORT N-ch...
Page 164 CHAPTER 4 PORT FUNCTIONS Figure 4-30. Block Diagram of Type U-10 PFmn PFCE PFCEmn PFCmn PMCmn PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used Output signal 3 when alternate function is used P-ch PORT N-ch...
Page 165 CHAPTER 4 PORT FUNCTIONS Figure 4-31. Block Diagram of Type U-11 PFmn PFCE PFCEmn PFCmn PMCmn PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used PORT P-ch N-ch Address Note Input signal 1 when Noise elimination alternate function is used...
Page 166 CHAPTER 4 PORT FUNCTIONS Figure 4-32. Block Diagram of Type U-12 PFmn PFCE PFCEmn PFCmn PMCmn PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used P-ch PORT N-ch Address Note Input signal when alternate function is used Note Hysteresis characteristics are not available in port mode.
Page 167 CHAPTER 4 PORT FUNCTIONS Figure 4-33. Block Diagram of Type U-13 PFmn PFCE PFCEmn PFCmn PMCmn PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used P-ch PORT N-ch Note Address Input signal when alternate function is used Note Hysteresis characteristics are not available in port mode.
Page 168 CHAPTER 4 PORT FUNCTIONS Figure 4-34. Block Diagram of Type U-14 PFmn PFCE PFCEmn PFCmn PMCmn PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used P-ch PORT N-ch Note Address Input signal 1 when alternate function is used Input signal 2 when alternate function is used...
Page 169 CHAPTER 4 PORT FUNCTIONS Figure 4-35. Block Diagram of Type U-15 PFmn INTR Note 1 INTRmn INTF Note 1 INTFmn PFCE PFCEmn PFCmn PMCmn PMmn Output signal 1 when alternate function is used Output signal 2 when alternate function is used P-ch PORT N-ch...
Page 170: Port Register Settings When Alternate Function Is Used
CHAPTER 4 PORT FUNCTIONS Figure 4-36. Block Diagram of Type AA-1 PFmn External reset signal OCDM0 OCDM0 INTR Note 1 INTRmn INTF Note 1 INTFmn PMCmn PMmn PORT P-ch N-ch Note 2 Address Input signal when Edge Noise detection on-chip debugging elimination N-ch Input signal when...
Page 171 Table 4-19. Using Port Pins as Alternate-Function Pins (1/8) Pin Name Alternate Function Pnx Bit of PMnx Bit of PMCnx Bit of PFCEnx Bit of PFCnx Bit of Other Bits Pn Register PMn Register PMCn Register PFCEn Register PFCn Register (Registers) Name −...
Page 172 Table 4-19. Using Port Pins as Alternate-Function Pins (2/8) Pin Name Alternate Function Pnx Bit of PMnx Bit of PMCnx Bit of PFCEnx Bit of PFCnx Bit of Other Bits Pn Register PMn Register PMCn Register PFCEn Register PFCn Register (Registers) Name −...
Page 173 Table 4-19. Using Port Pins as Alternate-Function Pins (3/8) Pin Name Alternate Function Pnx Bit of PMnx Bit of PMCnx Bit of PFCEnx Bit of PFCnx Bit of Other Bits Pn Register PMn Register PMCn Register PFCEn Register PFCn Register (Registers) Name SIB2...
Page 174 Table 4-19. Using Port Pins as Alternate-Function Pins (4/8) Pin Name Alternate Function Pnx Bit of PMnx Bit of PMCnx Bit of PFCEnx Bit of PFCnx Bit of Other Bits Pn Register PMn Register PMCn Register PFCEn Register PFCn Register (Registers) Name −...
Page 175 Table 4-19. Using Port Pins as Alternate-Function Pins (5/8) Pin Name Alternate Function Pnx Bit of PMnx Bit of PMCnx Bit of PFCEnx Bit of PFCnx Bit of Other Bits Pn Register PMn Register PMCn Register PFCEn Register PFCn Register (Registers) Name Output...
Page 176 Table 4-19. Using Port Pins as Alternate-Function Pins (6/8) Pin Name Alternate Function Pnx Bit of PMnx Bit of PMCnx Bit of PFCEnx Bit of PFCnx Bit of Other Bits Pn Register PMn Register PMCn Register PFCEn Register PFCn Register (Registers) Name Output...
Page 177 Table 4-19. Using Port Pins as Alternate-Function Pins (7/8) Pin Name Alternate Function Pnx Bit of PMnx Bit of PMCnx Bit of PFCEnx Bit of PFCnx Bit of Other Bits Pn Register PMn Register PMCn Register PFCEn Register PFCn Register (Registers) Name −...
Page 178 Table 4-19. Using Port Pins as Alternate-Function Pins (8/8) Pin Name Alternate Function Pnx Bit of PMnx Bit of PMCnx Bit of PFCEnx Bit of PFCnx Bit of Other Bits Pn Register PMn Register PMCn Register PFCEn Register PFCn Register (Registers) Name −...
Page 179: Cautions
4.6.1 Cautions on setting port pins (1) In the V850ES/JJ3, the general-purpose port function and several peripheral function I/O pin share a pin. To switch between the general-purpose port (port mode) and the peripheral function I/O pin (alternate-function mode), set by the PMCn register. In regards to this register setting sequence, note with caution the following.
Page 180 CHAPTER 4 PORT FUNCTIONS The order of setting in which malfunction may occur on switching from the P41 pin to the SCL01 pin are shown below. Setting Order Setting Contents Pin States Pin Level <1> Initial value Port mode (input) Hi-Z (PMC41 bit = 0, PFC41 bit = 0,...
Page 181 CHAPTER 4 PORT FUNCTIONS Figure 4-37. Example of Switching from P02 to NMI (Incorrect) 0 → 1 PMC0 PMC0m bit = 0: Port mode PMC0m bit = 1: Alternate-function mode NMI interrupt occurrence Rising edge detector P02/NMI PMC02 bit = 0: Low level ↓...
Page 182: Cautions On Bit Manipulation Instruction For Port N Register (Pn)
Explanation: The targets of writing to and reading from the Pn register of a port whose PMnm bit is 1 are the output latch and pin status, respectively. A bit manipulation instruction is executed in the following order in the V850ES/JJ3. <1> The Pn register is read in 8-bit units.
Page 183: Cautions On On-Chip Debug Pins
CHAPTER 4 PORT FUNCTIONS 4.6.3 Cautions on on-chip debug pins The DRST, DCK, DMS, DDI, and DDO pins are on-chip debug pins. After reset by the RESET pin, the P05/INTP2/DRST pin is initialized to function as an on-chip debug pin (DRST). If a high level is input to the DRST pin at this time, the on-chip debug mode is set, and the DCK, DMS, DDI, and DDO pins can be used.
Page 184: Chapter 5 Bus Control Function
CHAPTER 5 BUS CONTROL FUNCTION The V850ES/JJ3 is provided with an external bus interface function by which external memories such as ROM and RAM, and I/O can be connected. Features Output is selectable from a multiplexed bus with a minimum of 3 bus cycles and a separate bus with a minimum of 2 bus cycles.
Page 185: Bus Control Pins
Caution When a write access is performed to the internal ROM area, address, data, and control signals are activated in the same way as access to the external memory area. 5.2.2 Pin status in each operation mode For the pin status of the V850ES/JJ3 in each operation mode, see 2.2 Pin States. User’s Manual U18376EJ3V0UD...
Page 186: Memory Block Function
CHAPTER 5 BUS CONTROL FUNCTION Memory Block Function The 16 MB external memory space is divided into memory blocks of (lower) 2 MB, 2 MB, 4 MB, and 8 MB. The programmable wait function and bus cycle operation mode for each of these blocks can be independently controlled in one-block units.
Page 187: External Bus Interface Mode Control Function
CHAPTER 5 BUS CONTROL FUNCTION External Bus Interface Mode Control Function The V850ES/JJ3 includes the following two external bus interface modes. • Multiplexed bus mode • Separate bus mode These two modes can be selected by using the EXIMC register.
Page 188: Bus Access
Each external memory area selected by CSn can be set by using the BSC register. However, the bus size can be set to 8 bits and 16 bits only. The external memory area of the V850ES/JJ3 is selected by CS0 to CS3. (1) Bus size configuration register (BSC) The BSC register can be read or written in 16-bit units.
Page 189: Access By Bus Size
5.5.3 Access by bus size The V850ES/JJ3 accesses the on-chip peripheral I/O and external memory in 8-bit, 16-bit, or 32-bit units. The bus size is as follows. • The bus size of the on-chip peripheral I/O is fixed to 16 bits.
Page 190 CHAPTER 5 BUS CONTROL FUNCTION (2) Byte access (8 bits) (a) 16-bit data bus width <1> Access to even address (2n) <2> Access to odd address (2n + 1) Address Address 2n + 1 Byte data External data Byte data External data (b) 8-bit data bus width <1>...
Page 191 CHAPTER 5 BUS CONTROL FUNCTION (3) Halfword access (16 bits) (a) With 16-bit data bus width <1> Access to even address (2n) <2> Access to odd address (2n + 1) First access Second access Address Address Address 2n + 1 2n + 1 2n + 2 Halfword data...
Page 192 CHAPTER 5 BUS CONTROL FUNCTION (4) Word access (32 bits) (a) 16-bit data bus width (1/2) <1> Access to address (4n) First access Second access Address Address 4n + 1 4n + 3 4n + 2 Word data External data Word data External data <2>...
Page 193 CHAPTER 5 BUS CONTROL FUNCTION (a) 16-bit data bus width (2/2) <3> Access to address (4n + 2) First access Second access Address Address 4n + 3 4n + 5 4n + 2 4n + 4 Word data External data Word data External data <4>...
Page 194 CHAPTER 5 BUS CONTROL FUNCTION (b) 8-bit data bus width (1/2) <1> Access to address (4n) First access Second access Third access Fourth access Address Address Address Address 4n + 1 4n + 2 4n + 3 Word data External data Word data External data Word data...
Page 195 CHAPTER 5 BUS CONTROL FUNCTION (b) 8-bit data bus width (2/2) <3> Access to address (4n + 2) First access Second access Third access Fourth access Address Address Address Address 4n + 2 4n + 3 4n + 4 4n + 5 Word data External data Word data...
Page 196: Wait Function
DWC0 register are complete. 3. When the V850ES/JJ3 is used in separate bus mode and operated at f > 20 MHz, be sure to insert one or more waits.
Page 197: External Wait Function
CHAPTER 5 BUS CONTROL FUNCTION 5.6.2 External wait function To synchronize an extremely slow external memory, I/O, or asynchronous system, any number of wait states can be inserted in the bus cycle by using the external wait pin (WAIT). When the PCM0 pin is set to alternate function, the external wait function is enabled. Access to each area of the internal ROM, internal RAM, and on-chip peripheral I/O is not subject to control by the external wait function, in the same manner as the programmable wait function.
Page 198: Relationship Between Programmable Wait And External Wait
CHAPTER 5 BUS CONTROL FUNCTION 5.6.3 Relationship between programmable wait and external wait Wait cycles are inserted as the result of an OR operation between the wait cycles specified by the set value of the programmable wait and the wait cycles controlled by the WAIT pin. Programmable wait Wait control Wait via WAIT pin...
Page 199: Programmable Address Wait Function
2. Write to the AWC register after reset, and then do not change the set values. Also, do not access an external memory area until the initial settings of the AWC register are complete. 3. When the V850ES/JJ3 is operated at f > 20 MHz, be sure to insert the address hold wait and the address setup wait.
Page 200: Idle State Insertion Function
CHAPTER 5 BUS CONTROL FUNCTION Idle State Insertion Function To facilitate interfacing with low-speed memories, one idle state (TI) can be inserted after the T3 state in the bus cycle that is executed for each space selected by the chip select function in the multiplex address/data bus mode. In the separate bus mode, one idle state (TI) can be inserted after the T2 state.
Page 201: Bus Hold Function
CHAPTER 5 BUS CONTROL FUNCTION Bus Hold Function 5.8.1 Functional outline The HLDRQ and HLDAK functions are valid if the PCM2 and PCM3 pins are set to alternate function. When the HLDRQ pin is asserted (low level), indicating that another bus master has requested bus mastership, the external address/data bus goes into a high-impedance state and is released (bus hold status).
Page 202: Bus Hold Procedure
CHAPTER 5 BUS CONTROL FUNCTION 5.8.2 Bus hold procedure The bus hold status transition procedure is shown below. <1> HLDRQ = 0 acknowledged <2> All bus cycle start requests inhibited Normal status <3> End of current bus cycle <4> Shift to bus idle status <5>...
Page 203: Bus Priority
CHAPTER 5 BUS CONTROL FUNCTION Bus Priority Bus hold, DMA transfer, operand data accesses, instruction fetch (branch), and instruction fetch (successive) are executed in the external bus cycle. Bus hold has the highest priority, followed by DMA transfer, operand data access, instruction fetch (branch), and instruction fetch (successive).
Page 204: Bus Timing
CHAPTER 5 BUS CONTROL FUNCTION 5.10 Bus Timing Figure 5-4. Multiplexed Bus Read Timing (Bus Size: 16 Bits, 16-Bit Access) CLKOUT A23 to A16 ASTB CS3 to CS0 WAIT AD15 to AD0 Idle state Programmable External wait wait 8-bit Access Odd Address Even Address AD15 to AD8...
Page 205 CHAPTER 5 BUS CONTROL FUNCTION Figure 5-6. Multiplexed Bus Write Timing (Bus Size: 16 Bits, 16-Bit Access) CLKOUT A23 to A16 ASTB CS3 to CS0 WAIT AD15 to AD0 WR1, WR0 Programmable External wait wait 8-bit Access Odd Address Even Address AD15 to AD8 Active Undefined...
Page 206 CHAPTER 5 BUS CONTROL FUNCTION Figure 5-8. Multiplexed Bus Hold Timing (Bus Size: 16 Bits, 16-Bit Access) Note Note CLKOUT HLDRQ HLDAK A23 to A16 Undefined Undefined Undefined Undefined AD15 to AD0 ASTB CS3 to CS0 1111 1111 Note This idle state (TI) does not depend on the BCC register settings. Remarks 1.
Page 207 CHAPTER 5 BUS CONTROL FUNCTION Figure 5-9. Separate Bus Read Timing (Bus Size: 16 Bits, 16-Bit Access) CLKOUT CS3 to CS0 WAIT A23 to A0 AD15 to AD0 External Programmable Idle state wait wait 8-bit Access Odd Address Even Address AD15 to AD8 Active Hi-Z...
Page 208 CHAPTER 5 BUS CONTROL FUNCTION Figure 5-11. Separate Bus Write Timing (Bus Size: 16 Bits, 16-Bit Access) CLKOUT CS3 to CS0 WAIT A23 to A0 WR1, WR0 AD15 to AD0 Programmable External wait wait 8-bit Access Odd Address Even Address AD15 to AD8 Active Undefined...
Page 209 CHAPTER 5 BUS CONTROL FUNCTION Figure 5-13. Separate Bus Hold Timing (Bus Size: 8 Bits, Write) Note Note CLKOUT HLDRQ HLDAK A23 to A0 Undefined Undefined AD7 to AD0 WR1, WR0 CS3 to CS0 1111 1111 Note This idle state (TI) does not depend on the BCC register settings. Remark The broken lines indicate high impedance.
Page 210: Chapter 6 Clock Generation Function
CHAPTER 6 CLOCK GENERATION FUNCTION Overview The following clock generation functions are available. Main clock oscillator • In clock-through mode = 2.5 to 10 MHz (f = 2.5 to 10 MHz) • In PLL mode = 2.5 to 5 MHz (×4: f = 10 to 20 MHz) = 2.5 to 4 MHz (×8: f = 20 to 32 MHz)
Page 211: Configuration
CHAPTER 6 CLOCK GENERATION FUNCTION Configuration Figure 6-1. Clock Generator FRC bit Timer M clock Subclock Watch timer clock, oscillator watchdog timer 2 clock /2 to f Watch timer clock Prescaler 3 IDLE CLS, CK3 control MFRC PLLON bits IDLE mode CK2 to CK0 bits Note...
Page 212 CHAPTER 6 CLOCK GENERATION FUNCTION (1) Main clock oscillator The main resonator oscillates the following frequencies (f • In clock-through mode = 2.5 to 10 MHz • In PLL mode = 2.5 to 5 MHz (×4) = 2.5 to 4 MHz (×8) (2) Subclock oscillator The sub-resonator oscillates a frequency of 32.768 kHz (f (3) Main clock oscillator stop control...
Page 213: Registers
CHAPTER 6 CLOCK GENERATION FUNCTION Registers (1) Processor clock control register (PCC) The PCC register is a special register. Data can be written to this register only in combination of specific sequences (see 3.4.7 Special registers). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 03H.
Page 214 CHAPTER 6 CLOCK GENERATION FUNCTION After reset: 03H Address: FFFFF828H < > < > < > Note MFRC Use of subclock on-chip feedback resistor Used Not used Main clock oscillator control Oscillation enabled Oscillation stopped • Even if the MCK bit is set (1) while the system is operating with the main clock as the CPU clock, the operation of the main clock does not stop.
Page 215 CHAPTER 6 CLOCK GENERATION FUNCTION (a) Example of setting main clock operation → subclock operation <1> CK3 bit ← 1: Use of a bit manipulation instruction is recommended. Do not change the CK2 to CK0 bits. <2> Subclock operation: Read the CLS bit to check if subclock operation has started. It takes the following time after the CK3 bit is set until subclock operation is started.
Page 216 CHAPTER 6 CLOCK GENERATION FUNCTION (b) Example of setting subclock operation → main clock operation <1> MCK bit ← 0: Main clock starts oscillating <2> Insert waits by the program and wait until the oscillation stabilization time of the main clock elapses. <3>...
Page 217 CHAPTER 6 CLOCK GENERATION FUNCTION (2) Internal oscillation mode register (RCM) The RCM register is an 8-bit register that sets the operation mode of the internal oscillator. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H Address: FFFFF80CH <...
Page 218: Operation
CHAPTER 6 CLOCK GENERATION FUNCTION Operation 6.4.1 Operation of each clock The following table shows the operation status of each clock. Table 6-1. Operation Status of Each Clock Register Setting and PCC Register Operation Status CLK Bit = 0, MCK Bit = 0 CLS Bit = 1, CLS Bit = 1, MCK Bit = 0...
Page 219: Pll Function
Overview In the V850ES/JJ3, an operating clock that is 4 or 8 times higher than the oscillation frequency output by the PLL function or the clock-through mode can be selected as the operating clock of the CPU and on-chip peripheral functions.
Page 220 CHAPTER 6 CLOCK GENERATION FUNCTION (2) Clock control register (CKC) The CKC register is a special register. Data can be written to this register only in a combination of specific sequence (see 3.4.7 Special registers). The CKC register controls the internal system clock in the PLL mode. This register can be read or written in 8-bit or 1-bit units.
Page 221 CHAPTER 6 CLOCK GENERATION FUNCTION (3) Lock register (LOCKR) Phase lock occurs at a given frequency following power application or immediately after the STOP mode is released, and the time required for stabilization is the lockup time (frequency stabilization time). This state until stabilization is called the lockup status, and the stabilized state is called the locked status.
Page 222: Usage
CHAPTER 6 CLOCK GENERATION FUNCTION (4) PLL lockup time specification register (PLLS) The PLLS register is an 8-bit register used to select the PLL lockup time when the PLLCTL.PLLON bit is changed from 0 to 1. This register can be read or written in 8-bit units. Reset sets this register to 03H.
Page 223: Chapter 7 16-Bit Timer/Event Counter P (Tmp)
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Timer P (TMP) is a 16-bit timer/event counter. The V850ES/JJ3 has nine timer/event counter channels, TMP0 to TMP8. Overview An outline of TMPn is shown below. • Clock selection: 8 ways • Capture/trigger input pins: 2 •...
Page 224: Configuration
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Configuration TMPn includes the following hardware. Table 7-1. Configuration of TMPn Item Configuration Timer register 16-bit counter Registers TMPn capture/compare registers 0, 1 (TPnCCR0, TPnCCR1) TMPn counter read buffer register (TPnCNT) CCR0, CCR1 buffer registers Note 1 Timer inputs 2 (TIPn0...
Page 225 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (1) 16-bit counter This 16-bit counter can count internal clocks or external events. The count value of this counter can be read by using the TPnCNT register. When the TPnCTL0.TPnCE bit = 0, the value of the 16-bit counter is FFFFH. If the TPnCNT register is read at this time, 0000H is read.
Page 226: Registers
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Registers The registers that control TMPn are as follows. • TMPn control register 0 (TPnCTL0) • TMPn control register 1 (TPnCTL1) • TMPn I/O control register 0 (TPnIOC0) • TMPn I/O control register 1 (TPnIOC1) •...
Page 227 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (1) TMPn control register 0 (TPnCTL0) The TPnCTL0 register is an 8-bit register that controls the operation of TMPn. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. The same value can always be written to the TPnCTL0 register by software.
Page 228 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) After reset: 00H Address: TP0CTL1 FFFFF591H, TP1CTL1 FFFFF5A1H, TP2CTL1 FFFFF5B1H, TP3CTL1 FFFFF5C1H, TP4CTL1 FFFFF5D1H, TP5CTL1 FFFFF5E1H, TP6CTL1 FFFFF5F1H, TP7CTL1 FFFFF601H, TP8CTL1 FFFFF611H <6> <5> TPnCTL1 TPnEST TPnEEE TPnMD2 TPnMD1 TPnMD0 (n = 0 to 8) TPnEST Software trigger control −...
Page 229 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (3) TMPn I/O control register 0 (TPnIOC0) The TPnIOC0 register is an 8-bit register that controls the timer output (TOPn0, TOPn1 pins). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
Page 230 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (4) TMPn I/O control register 1 (TPnIOC1) The TPnIOC1 register is an 8-bit register that controls the valid edge of the capture trigger input signals (TIPn0, TIPn1 pins). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
Page 231 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (5) TMPn I/O control register 2 (TPnIOC2) The TPnIOC2 register is an 8-bit register that controls the valid edge of the external event count input signal (TIPn0 pin) and external trigger input signal (TIPn0 pin). This register can be read or written in 8-bit or 1-bit units.
Page 232 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (6) TMPn option register 0 (TPnOPT0) The TPnOPT0 register is an 8-bit register used to set the capture/compare operation and detect an overflow. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
Page 233 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (7) TMPn capture/compare register 0 (TPnCCR0) The TPnCCR0 register can be used as a capture register or a compare register depending on the mode. This register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the TPnOPT0.TPnCCS0 bit.
Page 234 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (a) Function as compare register The TPnCCR0 register can be rewritten even when the TPnCTL0.TPnCE bit = 1. The set value of the TPnCCR0 register is transferred to the CCR0 buffer register. When the value of the 16-bit counter matches the value of the CCR0 buffer register, a compare match interrupt request signal (INTTPnCC0) is generated.
Page 235 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (8) TMPn capture/compare register 1 (TPnCCR1) The TPnCCR1 register can be used as a capture register or a compare register depending on the mode. This register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the TPnOPT0.TPnCCS1 bit.
Page 236 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (a) Function as compare register The TPnCCR1 register can be rewritten even when the TPnCTL0.TPnCE bit = 1. The set value of the TPnCCR1 register is transferred to the CCR1 buffer register. When the value of the 16-bit counter matches the value of the CCR1 buffer register, a compare match interrupt request signal (INTTPnCC1) is generated.
Page 237 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (9) TMPn counter read buffer register (TPnCNT) The TPnCNT register is a read buffer register that can read the count value of the 16-bit counter. If this register is read when the TPnCTL0.TPnCE bit = 1, the count value of the 16-bit timer can be read. This register is read-only, in 16-bit units.
Page 238: Operation
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Operation TMPn can perform the following operations. TPnCTL1.TPnEST Bit TIPn0 Pin Capture/Compare Compare Register Operation (Software Trigger Bit) (External Trigger Input) Register Setting Write Interval timer mode Invalid Invalid Compare only Anytime write Note 1 External event count mode Invalid...
Page 239: Interval Timer Mode (Tpnmd2 To Tpnmd0 Bits = 000)
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) 7.5.1 Interval timer mode (TPnMD2 to TPnMD0 bits = 000) In the interval timer mode, an interrupt request signal (INTTPnCC0) is generated at the specified interval if the TPnCTL0.TPnCE bit is set to 1. A square wave whose half cycle is equal to the interval can be output from the TOPn0 pin.
Page 240 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) When the TPnCE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H in synchronization with the count clock, and the counter starts counting. At this time, the output of the TOPn0 pin is inverted. Additionally, the set value of the TPnCCR0 register is transferred to the CCR0 buffer register.
Page 241 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-4. Register Setting for Interval Timer Mode Operation (2/2) (c) TMPn I/O control register 0 (TPnIOC0) TPnOL1 TPnOE1 TPnOL0 TPnOE0 TPnIOC0 0: Disable TOPn0 pin output 1: Enable TOPn0 pin output Setting of output level with operation of TOPn0 pin disabled 0: Low level 1: High level...
Page 242 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (1) Interval timer mode operation flow Figure 7-5. Software Processing Flow in Interval Timer Mode FFFFH 16-bit counter 0000H TPnCE bit TPnCCR0 register TOPn0 pin output INTTPnCC0 signal <1> <2> <1> Count operation start flow START Initial setting of these registers is performed Register initial setting...
Page 243 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (2) Interval timer mode operation timing (a) Operation if TPnCCR0 register is set to 0000H If the TPnCCR0 register is set to 0000H, the INTTPnCC0 signal is generated at each count clock subsequent to the first count clock, and the output of the TOPn0 pin is inverted. The value of the 16-bit counter is always 0000H.
Page 244 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (b) Operation if TPnCCR0 register is set to FFFFH If the TPnCCR0 register is set to FFFFH, the 16-bit counter counts up to FFFFH. The counter is cleared to 0000H in synchronization with the next count-up timing. The INTTPnCC0 signal is generated and the output of the TOPn0 pin is inverted.
Page 245 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (c) Notes on rewriting TPnCCR0 register To change the value of the TPnCCR0 register to a smaller value, stop counting once and then change the set value. If the value of the TPnCCR0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow.
Page 246 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (d) Operation of TPnCCR1 register Figure 7-6. Configuration of TPnCCR1 Register TPnCCR1 register Output TOPn1 pin CCR1 buffer register controller Match signal INTTPnCC1 signal Clear Count clock Output 16-bit counter TOPn0 pin selection controller Match signal INTTPnCC0 signal...
Page 247 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) If the set value of the TPnCCR1 register is less than the set value of the TPnCCR0 register, the INTTPnCC1 signal is generated once per cycle. At the same time, the output of the TOPn1 pin is inverted. The TOPn1 pin outputs a square wave with the same cycle as that output by the TOPn0 pin.
Page 248 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) If the set value of the TPnCCR1 register is greater than the set value of the TPnCCR0 register, the count value of the 16-bit counter does not match the value of the TPnCCR1 register. Consequently, the INTTPnCC1 signal is not generated, nor is the output of the TOPn1 pin changed.
Page 249: External Event Count Mode (Tpnmd2 To Tpnmd0 Bits = 001)
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) 7.5.2 External event count mode (TPnMD2 to TPnMD0 bits = 001) In the external event count mode, the valid edge of the external event count input is counted when the TPnCTL0.TPnCE bit is set to 1, and an interrupt request signal (INTTPnCC0) is generated each time the specified number of edges have been counted.
Page 250 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) When the TPnCE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H. The counter counts each time the valid edge of external event count input is detected. Additionally, the set value of the TPnCCR0 register is transferred to the CCR0 buffer register.
Page 251 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-11. Register Setting for Operation in External Event Count Mode (2/2) (e) TMPn counter read buffer register (TPnCNT) The count value of the 16-bit counter can be read by reading the TPnCNT register. (f) TMPn capture/compare register 0 (TPnCCR0) If D is set to the TPnCCR0 register, the counter is cleared and a compare match interrupt request...
Page 252 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (1) External event count mode operation flow Figure 7-12. Flow of Software Processing in External Event Count Mode FFFFH 16-bit counter 0000H TPnCE bit TPnCCR0 register INTTPnCC0 signal <1> <2> <1> Count operation start flow START Register initial setting Initial setting of these registers...
Page 253 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (2) Operation timing in external event count mode Cautions 1. In the external event count mode, do not set the TPnCCR0 register to 0000H. 2. In the external event count mode, use of the timer output is disabled. If performing timer output using external event count input, set the interval timer mode, and select the operation enabled...
Page 254 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (b) Notes on rewriting the TPnCCR0 register To change the value of the TPnCCR0 register to a smaller value, stop counting once and then change the set value. If the value of the TPnCCR0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow.
Page 255 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (c) Operation of TPnCCR1 register Figure 7-13. Configuration of TPnCCR1 Register TPnCCR1 register CCR1 buffer register Match signal INTTPnCC1 signal Clear Edge TIPn0 pin 16-bit counter detector Match signal INTTPnCC0 signal TPnCE bit CCR0 buffer register TPnCCR0 register Remark...
Page 256 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) If the set value of the TPnCCR1 register is greater than the set value of the TPnCCR0 register, the INTTPnCC1 signal is not generated because the count value of the 16-bit counter and the value of the TPnCCR1 register do not match.
Page 257: External Trigger Pulse Output Mode (Tpnmd2 To Tpnmd0 Bits = 010)
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) 7.5.3 External trigger pulse output mode (TPnMD2 to TPnMD0 bits = 010) In the external trigger pulse output mode, 16-bit timer/event counter P waits for a trigger when the TPnCTL0.TPnCE bit is set to 1. When the valid edge of an external trigger input signal is detected, 16-bit timer/event counter P starts counting, and outputs a PWM waveform from the TOPn1 pin.
Page 258 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-17. Basic Timing in External Trigger Pulse Output Mode FFFFH 16-bit counter 0000H TPnCE bit External trigger input (TIPn0 pin input) TPnCCR0 register INTTPnCC0 signal TOPn0 pin output (only when software trigger is used) TPnCCR1 register INTTPnCC1 signal TOPn1 pin output...
Page 259 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-18. Register Setting for Operation in External Trigger Pulse Output Mode (1/2) (a) TMPn control register 0 (TPnCTL0) TPnCE TPnCKS2 TPnCKS1 TPnCKS0 TPnCTL0 Select count clock 0: Stop counting 1: Enable counting (b) TMPn control register 1 (TPnCTL1) TPnEST TPnEEE...
Page 260 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-18. Register Setting for Operation in External Trigger Pulse Output Mode (2/2) (d) TMPn I/O control register 2 (TPnIOC2) <R> TPnEES1 TPnEES0 TPnETS1 TPnETS0 TPnIOC2 Select valid edge of external trigger input (e) TMPn counter read buffer register (TPnCNT) The value of the 16-bit counter can be read by reading the TPnCNT register.
Page 261 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (1) Operation flow in external trigger pulse output mode Figure 7-19. Software Processing Flow in External Trigger Pulse Output Mode (1/2) FFFFH 16-bit counter 0000H TPnCE bit External trigger input (TIPn0 pin input) TPnCCR0 register CCR0 buffer register INTTPnCC0 signal...
Page 262 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-19. Software Processing Flow in External Trigger Pulse Output Mode (2/2) <1> Count operation start flow <3> TPnCCR0, TPnCCR1 register setting change flow Only writing of the TPnCCR1 START register must be performed when the set duty factor is changed.
Page 263 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (2) External trigger pulse output mode operation timing (a) Note on changing pulse width during operation To change the PWM waveform while the counter is operating, write the TPnCCR1 register last. Rewrite the TPnCCRm register after writing the TPnCCR1 register after the INTTPnCC0 signal is detected. FFFFH 16-bit counter 0000H...
Page 264 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) In order to transfer data from the TPnCCRm register to the CCRm buffer register, the TPnCCR1 register must be written. To change both the cycle and active level width of the PWM waveform at this time, first set the cycle to the TPnCCR0 register and then set the active level width to the TPnCCR1 register.
Page 265 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (b) 0%/100% output of PWM waveform To output a 0% waveform, set the TPnCCR1 register to 0000H. If the set value of the TPnCCR0 register is FFFFH, the INTTPnCC1 signal is generated periodically. Count clock −...
Page 266 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (c) Conflict between trigger detection and match with TPnCCR1 register If the trigger is detected immediately after the INTTPnCC1 signal is generated, the 16-bit counter is immediately cleared to 0000H, the output signal of the TOPn1 pin is asserted, and the counter continues counting.
Page 267 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (d) Conflict between trigger detection and match with TPnCCR0 register If the trigger is detected immediately after the INTTPnCC0 signal is generated, the 16-bit counter is cleared to 0000H and continues counting up. Therefore, the active period of the TOPn1 pin is extended by time from generation of the INTTPnCC0 signal to trigger detection.
Page 268 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (e) Generation timing of compare match interrupt request signal (INTTPnCC1) The timing of generation of the INTTPnCC1 signal in the external trigger pulse output mode differs from the timing of other INTTPnCC1 signals; the INTTPnCC1 signal is generated when the count value of the 16-bit counter matches the value of the TPnCCR1 register.
Page 269: One-Shot Pulse Output Mode (Tpnmd2 To Tpnmd0 Bits = 011)
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) 7.5.4 One-shot pulse output mode (TPnMD2 to TPnMD0 bits = 011) In the one-shot pulse output mode, 16-bit timer/event counter P waits for a trigger when the TPnCTL0.TPnCE bit is set to 1. When the valid edge of an external trigger input is detected, 16-bit timer/event counter P starts counting, and outputs a one-shot pulse from the TOPn1 pin.
Page 270 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-21. Basic Timing in One-Shot Pulse Output Mode FFFFH 16-bit counter 0000H TPnCE bit External trigger input (TIPn0 pin input) TPnCCR0 register INTTPnCC0 signal TOPn0 pin output (only when software trigger is used) TPnCCR1 register INTTPnCC1 signal TOPn1 pin output...
Page 271 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-22. Register Setting for Operation in One-Shot Pulse Output Mode (1/2) (a) TMPn control register 0 (TPnCTL0) TPnCE TPnCKS2 TPnCKS1 TPnCKS0 TPnCTL0 Select count clock 0: Stop counting 1: Enable counting (b) TMPn control register 1 (TPnCTL1) TPnEST TPnEEE TPnMD2 TPnMD1 TPnMD0...
Page 272 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-22. Register Setting for Operation in One-Shot Pulse Output Mode (2/2) (d) TMPn I/O control register 2 (TPnIOC2) <R> TPnEES1 TPnEES0 TPnETS1 TPnETS0 TPnIOC2 Select valid edge of external trigger input (e) TMPn counter read buffer register (TPnCNT) The value of the 16-bit counter can be read by reading the TPnCNT register.
Page 273 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (1) Operation flow in one-shot pulse output mode Figure 7-23. Software Processing Flow in One-Shot Pulse Output Mode FFFFH 16-bit counter 0000H TPnCE bit External trigger input (TIPn0 pin input) TPnCCR0 register INTTPnCC0 signal TPnCCR1 register INTTPnCC1 signal TOPn1 pin output...
Page 274 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (2) Operation timing in one-shot pulse output mode (a) Note on rewriting TPnCCRm register To change the set value of the TPnCCRm register to a smaller value, stop counting once, and then change the set value.
Page 275 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (b) Generation timing of compare match interrupt request signal (INTTPnCC1) The generation timing of the INTTPnCC1 signal in the one-shot pulse output mode is different from other INTTPnCC1 signals; the INTTPnCC1 signal is generated when the count value of the 16-bit counter matches the value of the TPnCCR1 register.
Page 276: Pwm Output Mode (Tpnmd2 To Tpnmd0 Bits = 100)
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) 7.5.5 PWM output mode (TPnMD2 to TPnMD0 bits = 100) In the PWM output mode, a PWM waveform is output from the TOPn1 pin when the TPnCTL0.TPnCE bit is set to 1. In addition, a pulse with one cycle of the PWM waveform as half its cycle is output from the TOPn0 pin. Figure 7-24.
Page 277 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-25. Basic Timing in PWM Output Mode FFFFH 16-bit counter 0000H TPnCE bit TPnCCR0 register CCR0 buffer register INTTPnCC0 signal TOPn0 pin output TPnCCR1 register CCR1 buffer register INTTPnCC1 signal TOPn1 pin output Active period Cycle Inactive period...
Page 278 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-26. Register Setting for Operation in PWM Output Mode (1/2) (a) TMPn control register 0 (TPnCTL0) TPnCE TPnCKS2 TPnCKS1 TPnCKS0 TPnCTL0 Note 1 Select count clock 0: Stop counting 1: Enable counting (b) TMPn control register 1 (TPnCTL1) TPnEST TPnEEE...
Page 279 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-26. Register Setting for Operation in PWM Output Mode (2/2) (d) TMPn I/O control register 2 (TPnIOC2) TPnEES1 TPnEES0 TPnETS1 TPnETS0 TPnIOC2 Select valid edge of external event count input. (e) TMPn counter read buffer register (TPnCNT) The value of the 16-bit counter can be read by reading the TPnCNT register.
Page 280 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (1) Operation flow in PWM output mode Figure 7-27. Software Processing Flow in PWM Output Mode (1/2) FFFFH 16-bit counter 0000H TPnCE bit TPnCCR0 register CCR0 buffer register INTTPnCC0 signal TOPn0 pin output TPnCCR1 register CCR1 buffer register INTTPnCC1 signal...
Page 281 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-27. Software Processing Flow in PWM Output Mode (2/2) <1> Count operation start flow <3> TPnCCR0, TPnCCR1 register setting change flow Only writing of the TPnCCR1 START register must be performed when the set duty factor is changed.
Page 282 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (2) PWM output mode operation timing (a) Changing pulse width during operation To change the PWM waveform while the counter is operating, write the TPnCCR1 register last. Rewrite the TPnCCRm register after writing the TPnCCR1 register after the INTTPnCC1 signal is detected. FFFFH 16-bit counter 0000H...
Page 283 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (b) 0%/100% output of PWM waveform To output a 0% waveform, set the TPnCCR1 register to 0000H. If the set value of the TPnCCR0 register is FFFFH, the INTTPnCC1 signal is generated periodically. Count clock −...
Page 284 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (c) Generation timing of compare match interrupt request signal (INTTPnCC1) The timing of generation of the INTTPnCC1 signal in the PWM output mode differs from the timing of other INTTPnCC1 signals; the INTTPnCC1 signal is generated when the count value of the 16-bit counter matches the value of the TPnCCR1 register.
Page 285: Free-Running Timer Mode (Tpnmd2 To Tpnmd0 Bits = 101)
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) 7.5.6 Free-running timer mode (TPnMD2 to TPnMD0 bits = 101) In the free-running timer mode, 16-bit timer/event counter P starts counting when the TPnCTL0.TPnCE bit is set to 1. At this time, the TPnCCRm register can be used as a compare register or a capture register, depending on the setting of the TPnOPT0.TPnCCS0 and TPnOPT0.TPnCCS1 bits.
Page 286 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) When the TPnCE bit is set to 1, 16-bit timer/event counter P starts counting, and the output signals of the TOPn0 and TOPn1 pins are inverted. When the count value of the 16-bit counter later matches the set value of the TPnCCRm register, a compare match interrupt request signal (INTTPnCCm) is generated, and the output signal of the TOPnm pin is inverted.
Page 287 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) When the TPnCE bit is set to 1, the 16-bit counter starts counting. When the valid edge input to the TIPnm pin is detected, the count value of the 16-bit counter is stored in the TPnCCRm register, and a capture interrupt request signal (INTTPnCCm) is generated.
Page 288 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-31. Register Setting in Free-Running Timer Mode (1/2) (a) TMPn control register 0 (TPnCTL0) TPnCE TPnCKS2 TPnCKS1 TPnCKS0 TPnCTL0 Note Select count clock 0: Stop counting 1: Enable counting Note The setting is invalid when the TPnCTL1.TPnEEE bit = 1 (b) TMPn control register 1 (TPnCTL1) TPnEST TPnEEE...
Page 289 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-31. Register Setting in Free-Running Timer Mode (2/2) (d) TMPn I/O control register 1 (TPnIOC1) TPnIS3 TPnIS2 TPnIS1 TPnIS0 TPnIOC1 Select valid edge of TIPn0 pin input Select valid edge of TIPn1 pin input (e) TMPn I/O control register 2 (TPnIOC2) TPnEES1 TPnEES0 TPnETS1 TPnETS0...
Page 290 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (1) Operation flow in free-running timer mode (a) When using capture/compare register as compare register Figure 7-32. Software Processing Flow in Free-Running Timer Mode (Compare Function) (1/2) FFFFH 16-bit counter 0000H TPnCE bit TPnCCR0 register Set value changed INTTPnCC0 signal...
Page 291 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-32. Software Processing Flow in Free-Running Timer Mode (Compare Function) (2/2) <1> Count operation start flow START Register initial setting Initial setting of these registers TPnCTL0 register is performed before setting the (TPnCKS0 to TPnCKS2 bits) TPnCE bit to 1.
Page 292 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (b) When using capture/compare register as capture register Figure 7-33. Software Processing Flow in Free-Running Timer Mode (Capture Function) (1/2) FFFFH 16-bit counter 0000H TPnCE bit TIPn0 pin input TPnCCR0 register 0000 0000 INTTPnCC0 signal TIPn1 pin input 0000...
Page 293 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-33. Software Processing Flow in Free-Running Timer Mode (Capture Function) (2/2) <1> Count operation start flow START Register initial setting Initial setting of these registers TPnCTL0 register is performed before setting the (TPnCKS0 to TPnCKS2 bits) TPnCE bit to 1.
Page 294 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (2) Operation timing in free-running timer mode (a) Interval operation with compare register When 16-bit timer/event counter P is used as an interval timer with the TPnCCRm register used as a compare register, software processing is necessary for setting a comparison value to generate the next interrupt request signal each time the INTTPnCCm signal has been detected.
Page 295 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (b) Pulse width measurement with capture register When pulse width measurement is performed with the TPnCCRm register used as a capture register, software processing is necessary for reading the capture register each time the INTTPnCCm signal has been detected and for calculating an interval.
Page 296 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (c) Processing of overflow when two capture registers are used Care must be exercised in processing the overflow flag when two capture registers are used. First, an example of incorrect processing is shown below. Example of incorrect processing when two capture registers are used FFFFH 16-bit counter...
Page 297 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (1/2) Example when two capture registers are used (using overflow interrupt) FFFFH 16-bit counter 0000H TPnCE bit INTTPnOV signal TPnOVF bit Note TPnOVF0 flag TIPn0 pin input TPnCCR0 register Note TPnOVF1 flag TIPn1 pin input TPnCCR1 register <1>...
Page 298 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (2/2) Example when two capture registers are used (without using overflow interrupt) FFFFH 16-bit counter 0000H TPnCE bit INTTPnOV signal TPnOVF bit Note TPnOVF0 flag TIPn0 pin input TPnCCR0 register Note TPnOVF1 flag TIPn1 pin input TPnCCR1 register <1>...
Page 299 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (d) Processing of overflow if capture trigger interval is long If the pulse width is greater than one cycle of the 16-bit counter, care must be exercised because an overflow may occur more than once from the first capture trigger to the next. First, an example of incorrect processing is shown below.
Page 300 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Example when capture trigger interval is long FFFFH 16-bit counter 0000H TPnCE bit TIPnm pin input TPnCCRm register INTTPnOV signal TPnOVF bit Overflow 2H 0H Note counter 1 cycle of 16-bit counter Pulse width <1>...
Page 301 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (e) Clearing overflow flag The overflow flag can be cleared to 0 by clearing the TPnOVF bit to 0 with the CLR instruction and by writing 8-bit data (bit 0 is 0) to the TPnOPT0 register. To accurately detect an overflow, read the TPnOVF bit when it is 1, and then clear the overflow flag by using a bit manipulation instruction.
Page 302: Pulse Width Measurement Mode (Tpnmd2 To Tpnmd0 Bits = 110)
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) 7.5.7 Pulse width measurement mode (TPnMD2 to TPnMD0 bits = 110) In the pulse width measurement mode, 16-bit timer/event counter P starts counting when the TPnCTL0.TPnCE bit is set to 1. Each time the valid edge input to the TIPnm pin has been detected, the count value of the 16-bit counter is stored in the TPnCCRm register, and the 16-bit counter is cleared to 0000H.
Page 303 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-35. Basic Timing in Pulse Width Measurement Mode FFFFH 16-bit counter 0000H TPnCE bit TIPnm pin input 0000H TPnCCRm register INTTPnCCm signal INTTPnOV signal Cleared to 0 by TPnOVF bit CLR instruction Remark n = 0 to 8 m = 0, 1...
Page 304 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-36. Register Setting in Pulse Width Measurement Mode (1/2) (a) TMPn control register 0 (TPnCTL0) TPnCE TPnCKS2 TPnCKS1 TPnCKS0 TPnCTL0 Select count clock 0: Stop counting 1: Enable counting (b) TMPn control register 1 (TPnCTL1) <R>...
Page 305 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Figure 7-36. Register Setting in Pulse Width Measurement Mode (2/2) (e) TMPn counter read buffer register (TPnCNT) The value of the 16-bit counter can be read by reading the TPnCNT register. (f) TMPn capture/compare registers 0 and 1 (TPnCCR0 and TPnCCR1) These registers store the count value of the 16-bit counter when the valid edge input to the TIPnm pin is detected.
Page 306 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (1) Operation flow in pulse width measurement mode Figure 7-37. Software Processing Flow in Pulse Width Measurement Mode FFFFH 16-bit counter 0000H TPnCE bit TIPn0 pin input 0000H 0000H TPnCCR0 register INTTPnCC0 signal <1>...
Page 307 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (2) Operation timing in pulse width measurement mode (a) Clearing overflow flag The overflow flag can be cleared to 0 by clearing the TPnOVF bit to 0 with the CLR instruction and by writing 8-bit data (bit 0 is 0) to the TPnOPT0 register.
Page 308: Timer Output Operations
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) 7.5.8 Timer output operations The following table shows the operations and output levels of the TOPn0 and TOPn1 pins. Table 7-4. Timer Output Control in Each Mode Operation Mode TOPn1 Pin TOPn0 Pin Interval timer mode Square wave output −...
Page 309: Selector Function
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Selector Function In the V850ES/JJ3, the capture trigger input for TMP can be selected from the input signal via the port/timer alternate-function pin and the peripheral I/O (TMP/UARTA) input signal. This function makes the following possible.
Page 310 CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) (1) Selector operation control register 0 (SELCNT0) The SELCNT0 register is an 8-bit register that selects the capture trigger for TMP1 and TMP3. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
Page 311: Cautions
CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP) Cautions (1) Capture operation When the capture operation is used and a slow clock is selected as the count clock, FFFFH, not 0000H, may be captured in the TPnCCR0 and TPnCCR1 registers if the capture trigger is input immediately after the TPnCE bit is set to 1.
Page 312: Chapter 8 16-Bit Timer/Event Counter Q (Tmq)
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Timer Q (TMQ) is a 16-bit timer/event counter. The V850ES/JJ3 incorporates TMQ0. Overview An outline of TMQ0 is shown below. • Clock selection: 8 ways • Capture/trigger input pins: 4 • External event count input pins: 1 •...
Page 313: Configuration
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Configuration TMQ0 includes the following hardware. Table 8-1. Configuration of TMQ0 Item Configuration Timer register 16-bit counter Registers TMQ0 capture/compare registers 0 to 3 (TQ0CCR0 to TQ0CCR3) TMQ0 counter read buffer register (TQ0CNT) CCR0 to CCR3 buffer registers Note 1 Timer inputs...
Page 314 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (1) 16-bit counter This 16-bit counter can count internal clocks or external events. The count value of this counter can be read by using the TQ0CNT register. When the TQ0CTL0.TQ0CE bit = 0, the value of the 16-bit counter is FFFFH. If the TQ0CNT register is read at this time, 0000H is read.
Page 315: Registers
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Registers The registers that control TMQ0 are as follows. • TMQ0 control register 0 (TQ0CTL0) • TMQ0 control register 1 (TQ0CTL1) • TMQ0 I/O control register 0 (TQ0IOC0) • TMQ0 I/O control register 1 (TQ0IOC1) •...
Page 316 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (1) TMQ0 control register 0 (TQ0CTL0) The TQ0CTL0 register is an 8-bit register that controls the operation of TMQ0. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. The same value can always be written to the TQ0CTL0 register by software.
Page 317 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (2) TMQ0 control register 1 (TQ0CTL1) The TQ0CTL1 register is an 8-bit register that controls the operation of TMQ0. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H Address: FFFFF541H...
Page 318 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (3) TMQ0 I/O control register 0 (TQ0IOC0) The TQ0IOC0 register is an 8-bit register that controls the timer output (TOQ00 to TOQ03 pins). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
Page 319 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (4) TMQ0 I/O control register 1 (TQ0IOC1) The TQ0IOC1 register is an 8-bit register that controls the valid edge of the capture trigger input signals (TIQ00 to TIQ03 pins). This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
Page 320 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (5) TMQ0 I/O control register 2 (TQ0IOC2) The TQ0IOC2 register is an 8-bit register that controls the valid edge of the external event count input signal (TIQ00 pin) and external trigger input signal (TIQ00 pin). This register can be read or written in 8-bit or 1-bit units.
Page 321 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (6) TMQ0 option register 0 (TQ0OPT0) The TQ0OPT0 register is an 8-bit register used to set the capture/compare operation and detect an overflow. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
Page 322 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (7) TMQ0 capture/compare register 0 (TQ0CCR0) The TQ0CCR0 register can be used as a capture register or a compare register depending on the mode. This register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the TQ0OPT0.TQ0CCS0 bit.
Page 323 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (a) Function as compare register The TQ0CCR0 register can be rewritten even when the TQ0CTL0.TQ0CE bit = 1. The set value of the TQ0CCR0 register is transferred to the CCR0 buffer register. When the value of the 16-bit counter matches the value of the CCR0 buffer register, a compare match interrupt request signal (INTTQ0CC0) is generated.
Page 324 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (8) TMQ0 capture/compare register 1 (TQ0CCR1) The TQ0CCR1 register can be used as a capture register or a compare register depending on the mode. This register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the TQ0OPT0.TQ0CCS1 bit.
Page 325 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (a) Function as compare register The TQ0CCR1 register can be rewritten even when the TQ0CTL0.TQ0CE bit = 1. The set value of the TQ0CCR1 register is transferred to the CCR1 buffer register. When the value of the 16-bit counter matches the value of the CCR1 buffer register, a compare match interrupt request signal (INTTQ0CC1) is generated.
Page 326 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (9) TMQ0 capture/compare register 2 (TQ0CCR2) The TQ0CCR2 register can be used as a capture register or a compare register depending on the mode. This register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the TQ0OPT0.TQ0CCS2 bit.
Page 327 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (a) Function as compare register The TQ0CCR2 register can be rewritten even when the TQ0CTL0.TQ0CE bit = 1. The set value of the TQ0CCR2 register is transferred to the CCR2 buffer register. When the value of the 16-bit counter matches the value of the CCR2 buffer register, a compare match interrupt request signal (INTTQ0CC2) is generated.
Page 328 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (10) TMQ0 capture/compare register 3 (TQ0CCR3) The TQ0CCR3 register can be used as a capture register or a compare register depending on the mode. This register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the TQ0OPT0.TQ0CCS3 bit.
Page 329 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (a) Function as compare register The TQ0CCR3 register can be rewritten even when the TQ0CTL0.TQ0CE bit = 1. The set value of the TQ0CCR3 register is transferred to the CCR3 buffer register. When the value of the 16-bit counter matches the value of the CCR3 buffer register, a compare match interrupt request signal (INTTQ0CC3) is generated.
Page 330 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (11) TMQ0 counter read buffer register (TQ0CNT) The TQ0CNT register is a read buffer register that can read the count value of the 16-bit counter. If this register is read when the TQ0CTL0.TQ0CE bit = 1, the count value of the 16-bit timer can be read. This register is read-only, in 16-bit units.
Page 331: Operation
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Operation TMQ0 can perform the following operations. TQ0CTL1.TQ0EST Bit TIQ00 Pin Capture/Compare Compare Register Operation (Software Trigger Bit) (External Trigger Input) Register Setting Write Interval timer mode Invalid Invalid Compare only Anytime write Note 1 External event count mode Invalid...
Page 332: Interval Timer Mode (Tq0Md2 To Tq0Md0 Bits = 000)
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) 8.5.1 Interval timer mode (TQ0MD2 to TQ0MD0 bits = 000) In the interval timer mode, an interrupt request signal (INTTQ0CC0) is generated at the specified interval if the TQ0CTL0.TQ0CE bit is set to 1. A square wave whose half cycle is equal to the interval can be output from the TOQ00 pin.
Page 333 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) When the TQ0CE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H in synchronization with the count clock, and the counter starts counting. At this time, the output of the TOQ00 pin is inverted. Additionally, the set value of the TQ0CCR0 register is transferred to the CCR0 buffer register.
Page 334 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-4. Register Setting for Interval Timer Mode Operation (2/2) (c) TMQ0 I/O control register 0 (TQ0IOC0) TQ0OL1 TQ0OE1 TQ0OL0 TQ0OE0 TQ0OL3 TQ0OE3 TQ0OL2 TQ0OE2 TQ0IOC0 0: Disable TOQ00 pin output 1: Enable TOQ00 pin output Setting of output level with operation of TOQ00 pin disabled 0: Low level...
Page 335 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (1) Interval timer mode operation flow Figure 8-5. Software Processing Flow in Interval Timer Mode FFFFH 16-bit counter 0000H TQ0CE bit TQ0CCR0 register TOQ00 pin output INTTQ0CC0 signal <1> <2> <1> Count operation start flow START Initial setting of these registers is performed Register initial setting...
Page 336 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (2) Interval timer mode operation timing (a) Operation if TQ0CCR0 register is set to 0000H If the TQ0CCR0 register is set to 0000H, the INTTQ0CC0 signal is generated at each count clock subsequent to the first count clock, and the output of the TOQ00 pin is inverted. The value of the 16-bit counter is always 0000H.
Page 337 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (c) Notes on rewriting TQ0CCR0 register To change the value of the TQ0CCR0 register to a smaller value, stop counting once and then change the set value. If the value of the TQ0CCR0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow.
Page 338 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (d) Operation of TQ0CCR1 to TQ0CCR3 registers Figure 8-6. Configuration of TQ0CCR1 to TQ0CCR3 Registers TQ0CCR1 register CCR1 buffer Output TOQ01 pin register controller Match signal INTTQ0CC1 signal TQ0CCR2 register Output CCR2 buffer TOQ02 pin controller register...
Page 339 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) If the set value of the TQ0CCRk register is less than the set value of the TQ0CCR0 register, the INTTQ0CCk signal is generated once per cycle. At the same time, the output of the TOPQ0k pin is inverted.
Page 340 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) If the set value of the TQ0CCRk register is greater than the set value of the TQ0CCR0 register, the count value of the 16-bit counter does not match the value of the TQ0CCRk register. Consequently, the INTTQ0CCk signal is not generated, nor is the output of the TOQ0k pin changed.
Page 341: External Event Count Mode (Tq0Md2 To Tq0Md0 Bits = 001)
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) 8.5.2 External event count mode (TQ0MD2 to TQ0MD0 bits = 001) In the external event count mode, the valid edge of the external event count input is counted when the TQ0CTL0.TQ0CE bit is set to 1, and an interrupt request signal (INTTQ0CC0) is generated each time the specified number of edges have been counted.
Page 342 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) When the TQ0CE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H. The counter counts each time the valid edge of external event count input is detected. Additionally, the set value of the TQ0CCR0 register is transferred to the CCR0 buffer register.
Page 343 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-11. Register Setting for Operation in External Event Count Mode (2/2) (f) TMQ0 capture/compare register 0 (TQ0CCR0) If D is set to the TQ0CCR0 register, the counter is cleared and a compare match interrupt request signal (INTTQ0CC0) is generated when the number of external event counts reaches (D + 1).
Page 344 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (1) External event count mode operation flow Figure 8-12. Flow of Software Processing in External Event Count Mode FFFFH 16-bit counter 0000H TQ0CE bit TQ0CCR0 register INTTQ0CC0 signal <1> <2> <1> Count operation start flow START Register initial setting Initial setting of these registers...
Page 345 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (2) Operation timing in external event count mode Cautions 1. In the external event count mode, do not set the TQ0CCR0 register to 0000H. 2. In the external event count mode, use of the timer output is disabled. If performing timer output using external event count input, set the interval timer mode, and select the operation enabled...
Page 346 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (b) Notes on rewriting the TQ0CCR0 register To change the value of the TQ0CCR0 register to a smaller value, stop counting once and then change the set value. If the value of the TQ0CCR0 register is rewritten to a smaller value during counting, the 16-bit counter may overflow.
Page 347 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (c) Operation of TQ0CCR1 to TQ0CCR3 registers Figure 8-13. Configuration of TQ0CCR1 to TQ0CCR3 Registers TQ0CCR1 register CCR1 buffer register Match signal INTTQ0CC1 signal TQ0CCR2 register CCR2 buffer register Match signal INTTQ0CC2 signal TQ0CCR3 register CCR3 buffer...
Page 348 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) If the set value of the TQ0CCRk register is smaller than the set value of the TQ0CCR0 register, the INTTQ0CCk signal is generated once per cycle. Remark k = 1 to 3 ≥ D Figure 8-14.
Page 349 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) If the set value of the TQ0CCRk register is greater than the set value of the TQ0CCR0 register, the INTTQ0CCk signal is not generated because the count value of the 16-bit counter and the value of the TQ0CCRk register do not match.
Page 350: External Trigger Pulse Output Mode (Tq0Md2 To Tq0Md0 Bits = 010)
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) 8.5.3 External trigger pulse output mode (TQ0MD2 to TQ0MD0 bits = 010) In the external trigger pulse output mode, 16-bit timer/event counter Q waits for a trigger when the TQ0CTL0.TQ0CE bit is set to 1. When the valid edge of an external trigger input signal is detected, 16-bit timer/event counter Q starts counting, and outputs a PWM waveform from the TOQ01 to TOQ03 pins.
Page 351 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-17. Basic Timing in External Trigger Pulse Output Mode FFFFH 16-bit counter 0000H TQ0CE External trigger input (TIQ00 pin input) TQ0CCR0 register INTTQ0CC0 signal TOQ00 pin output (only when software trigger is used) TQ0CCR1 register INTTQ0CC1...
Page 352 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) 16-bit timer/event counter Q waits for a trigger when the TQ0CE bit is set to 1. When the trigger is generated, the 16-bit counter is cleared from FFFFH to 0000H, starts counting at the same time, and outputs a PWM waveform from the TOQ0k pin.
Page 353 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-18. Register Setting for Operation in External Trigger Pulse Output Mode (2/3) (b) TMQ0 control register 1 (TQ0CTL1) <R> TQ0EST TQ0EEE TQ0MD2 TQ0MD1 TQ0MD0 TQ0CTL1 0, 1, 0: External trigger pulse output mode Generate software trigger when 1 is written (c) TMQ0 I/O control register 0 (TQ0IOC0)
Page 354 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-18. Register Setting for Operation in External Trigger Pulse Output Mode (3/3) <R> (d) TMQ0 I/O control register 2 (TQ0IOC2) TQ0EES1 TQ0EES0 TQ0ETS1 TQ0ETS0 TQ0IOC2 Select valid edge of external trigger input (e) TMQ0 counter read buffer register (TQ0CNT) The value of the 16-bit counter can be read by reading the TQ0CNT register.
Page 355 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (1) Operation flow in external trigger pulse output mode Figure 8-19. Software Processing Flow in External Trigger Pulse Output Mode (1/2) FFFFH 16-bit counter 0000H TQ0CE bit External trigger input (TIQ00 pin input) TQ0CCR0 register CCR0 buffer register INTTQ0CC0 signal...
Page 356 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-19. Software Processing Flow in External Trigger Pulse Output Mode (2/2) <1> Count operation start flow <4> TQ0CCR1 to TQ0CCR3 register setting change flow Writing of the TQ0CCR1 START Setting of TQ0CCR2, register must be performed TQ0CCR3 registers when the set duty factor is only...
Page 357 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (2) External trigger pulse output mode operation timing (a) Note on changing pulse width during operation To change the PWM waveform while the counter is operating, write the TQ0CCR1 register last. Rewrite the TQ0CCRk register after writing the TQ0CCR1 register after the INTTQ0CC0 signal is detected. FFFFH 16-bit counter 0000H...
Page 358 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) In order to transfer data from the TQ0CCRm register to the CCRm buffer register, the TQ0CCR1 register must be written. To change both the cycle and active level width of the PWM waveform at this time, first set the cycle to the TQ0CCR0 register, set the active level width to the TQ0CCR2 and TQ0CCR3 registers, and then set an active level to the TQ0CCR1 register.
Page 359 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (b) 0%/100% output of PWM waveform To output a 0% waveform, set the TQ0CCRk register to 0000H. If the set value of the TQ0CCR0 register is FFFFH, the INTTQ0CCk signal is generated periodically. Count clock −...
Page 360 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (c) Conflict between trigger detection and match with CCRk buffer register If the trigger is detected immediately after the INTTQ0CCk signal is generated, the 16-bit counter is immediately cleared to 0000H, the output signal of the TOQ0k pin is asserted, and the counter continues counting.
Page 361 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (d) Conflict between trigger detection and match with CCR0 buffer register If the trigger is detected immediately after the INTTQ0CC0 signal is generated, the 16-bit counter is cleared to 0000H and continues counting up. Therefore, the active period of the TOQ0k pin is extended by time from generation of the INTTQ0CC0 signal to trigger detection.
Page 362 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (e) Generation timing of compare match interrupt request signal (INTTQ0CCk) The timing of generation of the INTTQ0CCk signal in the external trigger pulse output mode differs from the timing of other INTTQ0CCk signals; the INTTQ0CCk signal is generated when the count value of the 16-bit counter matches the value of the CCRk buffer register.
Page 363: One-Shot Pulse Output Mode (Tq0Md2 To Tq0Md0 Bits = 011)
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) 8.5.4 One-shot pulse output mode (TQ0MD2 to TQ0MD0 bits = 011) In the one-shot pulse output mode, 16-bit timer/event counter Q waits for a trigger when the TQ0CTL0.TQ0CE bit is set to 1. When the valid edge of an external trigger input is detected, 16-bit timer/event counter Q starts counting, and outputs a one-shot pulse from the TOQ01 to TOQ03 pins.
Page 364 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-21. Basic Timing in One-Shot Pulse Output Mode FFFFH 16-bit counter 0000H TQ0CE bit External trigger input (TIQ00 pin input) TQ0CCR0 register INTTQ0CC0 signal TOQ00 pin output (only when software trigger is used) TQ0CCR1 register INTTQ0CC1 signal TOQ01 pin output...
Page 365 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) When the TQ0CE bit is set to 1, 16-bit timer/event counter Q waits for a trigger. When the trigger is generated, the 16-bit counter is cleared from FFFFH to 0000H, starts counting, and outputs a one-shot pulse from the TOQ0k pin. After the one-shot pulse is output, the 16-bit counter is set to FFFFH, stops counting, and waits for a trigger.
Page 366 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-22. Register Setting for Operation in One-Shot Pulse Output Mode (2/3) (c) TMQ0 I/O control register 0 (TQ0IOC0) TQ0OL3 TQ0OE3 TQ0OL2 TQ0OE2 TQ0OL1 TQ0OE1 TQ0OL0 TQ0OE0 Note Note TQ0IOC0 0: Disable TOQ00 pin output 1: Enable TOQ00 pin output Setting of output level while operation of TOQ00 pin is disabled...
Page 367 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-22. Register Setting for Operation in One-Shot Pulse Output Mode (3/3) (f) TMQ0 capture/compare registers 0 to 3 (TQ0CCR0 to TQ0CCR3) If D is set to the TQ0CCR0 register and D to the TQ0CCRk register, the active level width and output delay period of the one-shot pulse are as follows.
Page 368 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (1) Operation flow in one-shot pulse output mode Figure 8-23. Software Processing Flow in One-Shot Pulse Output Mode (1/2) FFFFH 16-bit counter 0000H TQ0CE bit External trigger input (TIQ00 pin input) TQ0CCR0 register INTTQ0CC0 signal TOQ00 pin output (only when software...
Page 369 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-23. Software Processing Flow in One-Shot Pulse Output Mode (2/2) <1> Count operation start flow <2> TQ0CCR0 to TQ0CCR3 register setting change flow As rewriting the TQ0CCRm register START immediately forwards to the CCRm buffer Setting of TQ0CCR0 to TQ0CCR3 register, rewriting registers...
Page 370 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (2) Operation timing in one-shot pulse output mode (a) Note on rewriting TQ0CCRm register To change the set value of the TQ0CCRm register to a smaller value, stop counting once, and then change the set value.
Page 371 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (b) Generation timing of compare match interrupt request signal (INTTQ0CCk) The generation timing of the INTTQ0CCk signal in the one-shot pulse output mode is different from other INTTQ0CCk signals; the INTTQ0CCk signal is generated when the count value of the 16-bit counter matches the value of the TQ0CCRk register.
Page 372: Pwm Output Mode (Tq0Md2 To Tq0Md0 Bits = 100)
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) 8.5.5 PWM output mode (TQ0MD2 to TQ0MD0 bits = 100) In the PWM output mode, a PWM waveform is output from the TOQ01 to TOQ03 pins when the TQ0CTL0.TQ0CE bit is set to 1. In addition, a pulse with one cycle of the PWM waveform as half its cycle is output from the TOQ00 pin.
Page 373 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-25. Basic Timing in PWM Output Mode FFFFH 16-bit counter 0000H TQ0CE bit TQ0CCR0 register INTTQ0CC0 signal TOQ00 pin output TQ0CCR1 register INTTQ0CC1 signal TOQ01 pin output Active Active Active Active level width level width level width level width...
Page 374 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) When the TQ0CE bit is set to 1, the 16-bit counter is cleared from FFFFH to 0000H, starts counting, and outputs PWM waveform from the TOQ0k pin. The active level width, cycle, and duty factor of the PWM waveform can be calculated as follows. Active level width = (Set value of TQ0CCRk register ) ×...
Page 375 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-26. Register Setting for Operation in PWM Output Mode (2/3) (c) TMQ0 I/O control register 0 (TQ0IOC0) TQ0OL1 TQ0OE1 TQ0OL0 TQ0OE0 TQ0OL3 TQ0OE3 TQ0OL2 TQ0OE2 Note Note TQ0IOC0 0: Disable TOQ00 pin output 1: Enable TOQ00 pin output Setting of output level while operation of TOQ00 pin is disabled...
Page 376 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-26. Register Setting for Operation in PWM Output Mode (3/3) (f) TMQ0 capture/compare registers 0 to 3 (TQ0CCR0 to TQ0CCR3) If D is set to the TQ0CCR0 register and D to the TQ0CCR1 register, the cycle and active level of the PWM waveform are as follows.
Page 377 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (1) Operation flow in PWM output mode Figure 8-27. Software Processing Flow in PWM Output Mode (1/2) FFFFH 16-bit counter 0000H TQ0CE bit TQ0CCR0 register CCR0 buffer register INTTQ0CC0 signal TOQ00 pin output TQ0CCR1 register CCR1 buffer register INTTQ0CC1 signal...
Page 378 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-27. Software Processing Flow in PWM Output Mode (2/2) <1> Count operation start flow <4> TQ0CCR1 to TQ0CCR3 register setting change flow Only writing of the TQ0CCR1 START Setting of TQ0CCR2, register must be performed TQ0CCR3 registers when the set duty factor is only changed after writing the...
Page 379 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (2) PWM output mode operation timing (a) Changing pulse width during operation To change the PWM waveform while the counter is operating, write the TQ0CCR1 register last. Rewrite the TQ0CCRk register after writing the TQ0CCR1 register after the INTTQ0CC1 signal is detected. FFFFH 16-bit counter 0000H...
Page 380 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) To transfer data from the TQ0CCRm register to the CCRm buffer register, the TQ0CCR1 register must be written. To change both the cycle and active level of the PWM waveform at this time, first set the cycle to the TQ0CCR0 register, set the active level width to the TQ0CCR2 and TQ0CCR3 registers, and then set an active level width to the TQ0CCR1 register.
Page 381 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (b) 0%/100% output of PWM waveform To output a 0% waveform, set the TQ0CCRk register to 0000H. If the set value of the TQ0CCR0 register is FFFFH, the INTTQ0CCk signal is generated periodically. Count clock −...
Page 382 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (c) Generation timing of compare match interrupt request signal (INTTQ0CCk) The timing of generation of the INTTQ0CCk signal in the PWM output mode differs from the timing of other INTTQ0CCk signals; the INTTQ0CCk signal is generated when the count value of the 16-bit counter matches the value of the TQ0CCRk register.
Page 383: Free-Running Timer Mode (Tq0Md2 To Tq0Md0 Bits = 101)
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) 8.5.6 Free-running timer mode (TQ0MD2 to TQ0MD0 bits = 101) In the free-running timer mode, 16-bit timer/event counter Q starts counting when the TQ0CTL0.TQ0CE bit is set to 1. At this time, the TQ0CCRm register can be used as a compare register or a capture register, depending on the setting of the TQ0OPT0.TQ0CCS0 and TQ0OPT0.TQ0CCS1 bits.
Page 384 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) When the TQ0CE bit is set to 1, 16-bit timer/event counter Q starts counting, and the output signals of the TOQ00 to TOQ03 pins are inverted. When the count value of the 16-bit counter later matches the set value of the TQ0CCRm register, a compare match interrupt request signal (INTTQ0CCm) is generated, and the output signal of the TOQ0m pin is inverted.
Page 385 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) When the TQ0CE bit is set to 1, the 16-bit counter starts counting. When the valid edge input to the TIQ0m pin is detected, the count value of the 16-bit counter is stored in the TQ0CCRm register, and a capture interrupt request signal (INTTQ0CCm) is generated.
Page 386 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-31. Register Setting in Free-Running Timer Mode (1/3) (a) TMQ0 control register 0 (TQ0CTL0) TQ0CE TQ0CKS2 TQ0CKS1 TQ0CKS0 TQ0CTL0 Note Select count clock 0: Stop counting 1: Enable counting Note The setting is invalid when the TQ0CTL1.TQ0EEE bit = 1 (b) TMQ0 control register 1 (TQ0CTL1) TQ0EST TQ0EEE...
Page 387 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-31. Register Setting in Free-Running Timer Mode (2/3) (c) TMQ0 I/O control register 0 (TQ0IOC0) TQ0OL1 TQ0OE1 TQ0OL0 TQ0OE0 TQ0OL3 TQ0OE3 TQ0OL2 TQ0OE2 TQ0IOC0 0: Disable TOQ00 pin output 1: Enable TOQ00 pin output Setting of output level with operation of TOQ00 pin disabled 0: Low level...
Page 388 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-31. Register Setting in Free-Running Timer Mode (3/3) (e) TMQ0 I/O control register 2 (TQ0IOC2) TQ0EES1 TQ0EES0 TQ0ETS1 TQ0ETS0 TQ0IOC2 Select valid edge of external event count input (f) TMQ0 option register 0 (TQ0OPT0) TQ0CCS1 TQ0CCS0 TQ0OVF...
Page 389 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (1) Operation flow in free-running timer mode (a) When using capture/compare register as compare register Figure 8-32. Software Processing Flow in Free-Running Timer Mode (Compare Function) (1/2) FFFFH 16-bit counter 0000H TQ0CE bit TQ0CCR0 register Set value changed INTTQ0CC0 signal...
Page 390 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-32. Software Processing Flow in Free-Running Timer Mode (Compare Function) (2/2) <1> Count operation start flow START Initial setting of these registers Register initial setting is performed before setting the TQ0CTL0 register TQ0CE bit to 1.
Page 391 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (b) When using capture/compare register as capture register Figure 8-33. Software Processing Flow in Free-Running Timer Mode (Capture Function) (1/2) FFFFH 16-bit counter 0000H TQ0CE bit TIQ00 pin input TQ0CCR0 register 0000 0000 INTTQ0CC0 signal TIQ01 pin input TQ0CCR1 register...
Page 392 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-33. Software Processing Flow in Free-Running Timer Mode (Capture Function) (2/2) <1> Count operation start flow START Register initial setting Initial setting of these registers TQ0CTL0 register is performed before setting the (TQ0CKS0 to TQ0CKS2 bits) TQ0CE bit to 1.
Page 393 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (2) Operation timing in free-running timer mode (a) Interval operation with compare register When 16-bit timer/event counter Q is used as an interval timer with the TQ0CCRm register used as a compare register, software processing is necessary for setting a comparison value to generate the next interrupt request signal each time the INTTQ0CCm signal has been detected.
Page 394 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) When performing an interval operation in the free-running timer mode, two intervals can be set with one channel. To perform the interval operation, the value of the corresponding TQ0CCRm register must be re-set in the interrupt servicing that is executed when the INTTQ0CCm signal is detected.
Page 395 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (b) Pulse width measurement with capture register When pulse width measurement is performed with the TQ0CCRm register used as a capture register, software processing is necessary for reading the capture register each time the INTTQ0CCm signal has been detected and for calculating an interval.
Page 396 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) When executing pulse width measurement in the free-running timer mode, four pulse widths can be measured with one channel. To measure a pulse width, the pulse width can be calculated by reading the value of the TQ0CCRm register in synchronization with the INTTQ0CCm signal, and calculating the difference between the read value and the previously read value.
Page 397 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (c) Processing of overflow when two or more capture registers are used Care must be exercised in processing the overflow flag when two capture registers are used. First, an example of incorrect processing is shown below. Example of incorrect processing when two or more capture registers are used FFFFH 16-bit counter...
Page 398 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (1/2) Example when two capture registers are used (using overflow interrupt) FFFFH 16-bit counter 0000H TQ0CE bit INTTQ0OV signal TQ0OVF bit Note TQ0OVF0 flag TIQ00 pin input TQ0CCR0 register Note TQ0OVF1 flag TIQ01 pin input TQ0CCR1 register <1>...
Page 399 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (2/2) Example when two capture registers are used (without using overflow interrupt) FFFFH 16-bit counter 0000H TQ0CE bit INTTQ0OV signal TQ0OVF bit Note TQ0OVF0 flag TIQ00 pin input TQ0CCR0 register Note TQ0OVF1 flag TIQ01 pin input TQ0CCR1 register <1>...
Page 400 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (d) Processing of overflow if capture trigger interval is long If the pulse width is greater than one cycle of the 16-bit counter, care must be exercised because an overflow may occur more than once from the first capture trigger to the next. First, an example of incorrect processing is shown below.
Page 401 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Example when capture trigger interval is long FFFFH 16-bit counter 0000H TQ0CE bit TIQ0m pin input TQ0CCRm register INTTQ0OV signal TQ0OVF bit Overflow 2H 0H Note counter 1 cycle of 16-bit counter Pulse width <1>...
Page 402 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (e) Clearing overflow flag The overflow flag can be cleared to 0 by clearing the TQ0OVF bit to 0 with the CLR instruction and by writing 8-bit data (bit 0 is 0) to the TQ0OPT0 register. To accurately detect an overflow, read the TQ0OVF bit when it is 1, and then clear the overflow flag by using a bit manipulation instruction.
Page 403: Pulse Width Measurement Mode (Tq0Md2 To Tq0Md0 Bits = 110)
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) 8.5.7 Pulse width measurement mode (TQ0MD2 to TQ0MD0 bits = 110) In the pulse width measurement mode, 16-bit timer/event counter Q starts counting when the TQ0CTL0.TQ0CE bit is set to 1. Each time the valid edge input to the TIQ0m pin has been detected, the count value of the 16-bit counter is stored in the TQ0CCRm register, and the 16-bit counter is cleared to 0000H.
Page 404 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-35. Basic Timing in Pulse Width Measurement Mode FFFFH 16-bit counter 0000H TQ0CE bit TIQ0m pin input TQ0CCRm register 0000H INTTQ0CCm signal INTTQ0OV signal Cleared to 0 by CLR instruction TQ0OVF bit Remark m = 0 to 3 When the TQ0CE bit is set to 1, the 16-bit counter starts counting.
Page 405 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-36. Register Setting in Pulse Width Measurement Mode (1/2) (a) TMQ0 control register 0 (TQ0CTL0) TQ0CE TQ0CKS2 TQ0CKS1 TQ0CKS0 TQ0CTL0 Select count clock 0: Stop counting 1: Enable counting <R> (b) TMQ0 control register 1 (TQ0CTL1) TQ0EST TQ0EEE TQ0MD2 TQ0MD1 TQ0MD0...
Page 406 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Figure 8-36. Register Setting in Pulse Width Measurement Mode (2/2) (e) TMQ0 counter read buffer register (TQ0CNT) The value of the 16-bit counter can be read by reading the TQ0CNT register. (f) TMQ0 capture/compare registers 0 to 3 (TQ0CCR0 to TQ0CCR3) These registers store the count value of the 16-bit counter when the valid edge input to the TIQ0m pin is detected.
Page 407 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (1) Operation flow in pulse width measurement mode Figure 8-37. Software Processing Flow in Pulse Width Measurement Mode FFFFH 16-bit counter 0000H TQ0CE bit TIQ00 pin input 0000H 0000H TQ0CCR0 register INTTQ0CC0 signal <1>...
Page 408 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) (2) Operation timing in pulse width measurement mode (a) Clearing overflow flag The overflow flag can be cleared to 0 by clearing the TQ0OVF bit to 0 with the CLR instruction and by writing 8-bit data (bit 0 is 0) to the TQ0OPT0 register.
Page 409: Timer Output Operations
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) 8.5.8 Timer output operations The following table shows the operations and output levels of the TOQ00 to TOQ03 pins. Table 8-6. Timer Output Control in Each Mode Operation Mode TOQ00 Pin TOQ01 Pin TOQ02 Pin TOQ03 Pin Interval timer mode...
Page 410: Cautions
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Q (TMQ) Cautions (1) Capture operation When the capture operation is used and a slow clock is selected as the count clock, FFFFH, not 0000H, may be captured in the TQ0CCR0, TQ0CCR1, TQ0CCR2, and TQ0CCR3 registers if the capture trigger is input immediately after the TQ0CE bit is set to 1.
Page 411: Chapter 9 16-Bit Interval Timer M (Tmm)
CHAPTER 9 16-BIT INTERVAL TIMER M (TMM) Overview • Interval function • 8 clocks selectable • 16-bit counter × 1 (The 16-bit counter cannot be read during timer count operation.) • Compare register × 1 (The compare register cannot be written during timer counter operation.) •...
Page 412: Configuration
CHAPTER 9 16-BIT INTERVAL TIMER M (TMM) Configuration TMM0 includes the following hardware. Table 9-1. Configuration of TMM0 Item Configuration Timer register 16-bit counter Register TMM0 compare register 0 (TM0CMP0) Control register TMM0 control register 0 (TM0CTL0) Figure 9-1. Block Diagram of TMM0 Internal bus TM0CTL0 TM0CE TM0CKS2 TM0CKS1TM0CKS0...
Page 413: Register
CHAPTER 9 16-BIT INTERVAL TIMER M (TMM) Register (1) TMM0 control register (TM0CTL0) The TM0CTL0 register is an 8-bit register that controls the TMM0 operation. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. The same value can always be written to the TM0CTL0 register by software.
Page 414: Operation
CHAPTER 9 16-BIT INTERVAL TIMER M (TMM) Operation Caution Do not set the TM0CMP0 register to FFFFH. 9.4.1 Interval timer mode In the interval timer mode, an interrupt request signal (INTTM0EQ0) is generated at the specified interval if the TM0CTL0.TM0CE bit is set to 1. Figure 9-2.
Page 415 CHAPTER 9 16-BIT INTERVAL TIMER M (TMM) Figure 9-4. Register Setting for Interval Timer Mode Operation (a) TMM0 control register 0 (TM0CTL0) TM0CE TM0CKS2 TM0CKS1 TM0CKS0 TM0CTL0 Select count clock 0: Stop counting 1: Enable counting (b) TMM0 compare register 0 (TM0CMP0) If the TM0CMP0 register is set to D, the interval is as follows.
Page 416 CHAPTER 9 16-BIT INTERVAL TIMER M (TMM) (1) Interval timer mode operation flow Figure 9-5. Software Processing Flow in Interval Timer Mode FFFFH 16-bit counter 0000H TM0CE bit TM0CMP0 register INTTM0EQ0 signal <1> <2> <1> Count operation start flow START Initial setting of these registers is performed before setting the TM0CE bit to 1.
Page 417 CHAPTER 9 16-BIT INTERVAL TIMER M (TMM) (2) Interval timer mode operation timing Caution Do not set the TM0CMP0 register to FFFFH. (a) Operation if TM0CMP0 register is set to 0000H If the TM0CMP0 register is set to 0000H, the INTTM0EQ0 signal is generated at each count clock. The value of the 16-bit counter is always 0000H.
Page 418: Cautions
CHAPTER 9 16-BIT INTERVAL TIMER M (TMM) 9.4.2 Cautions (1) It takes the 16-bit counter up to the following time to start counting after the TM0CTL0.TM0CE bit is set to 1, depending on the count clock selected. Selected Count Clock Maximum Time Before Counting Start 24/f 128/f...
Page 419: Chapter 10 Watch Timer Functions
CHAPTER 10 WATCH TIMER FUNCTIONS 10.1 Functions The watch timer has the following functions. • Watch timer: An interrupt request signal (INTWT) is generated at intervals of 0.5 or 0.25 seconds by using the main clock or subclock. • Interval timer: An interrupt request signal (INTWTI) is generated at set intervals. The watch timer and interval timer functions can be used at the same time.
Page 420: Configuration
CHAPTER 10 WATCH TIMER FUNCTIONS 10.2 Configuration The block diagram of the watch timer is shown below. Figure 10-1. Block Diagram of Watch Timer Internal bus PRSM0 register BGCE0 BGCS01 BGCS00 Clear PRSCM0 register 3-bit Clock prescaler control Match BGCS 8-bit counter 5-bit counter Clear...
Page 421 CHAPTER 10 WATCH TIMER FUNCTIONS (1) Clock control This block controls supplying and stopping the operating clock (f ) when the watch timer operates on the main clock. (2) 3-bit prescaler This prescaler divides f to generate f /2, f /4, or f (3) 8-bit counter This 8-bit counter counts the source clock (f...
Page 422: Control Registers
CHAPTER 10 WATCH TIMER FUNCTIONS 10.3 Control Registers The following registers are provided for the watch timer. • Prescaler mode register 0 (PRSM0) • Prescaler compare register 0 (PRSCM0) • Watch timer operation mode register (WTM) (1) Prescaler mode register 0 (PRSM0) The PRSM0 register controls the generation of the watch timer count clock.
Page 423 CHAPTER 10 WATCH TIMER FUNCTIONS (2) Prescaler compare register 0 (PRSCM0) The PRSCM0 register is an 8-bit compare register. This register can be read or written in 8-bit units. Reset sets this register to 00H. After reset: 00H Address: FFFFF8B1H PRSCM0 PRSCM07 PRSCM06 PRSCM05 PRSCM04 PRSCM03 PRSCM02 PRSCM01 PRSCM00...
Page 424 CHAPTER 10 WATCH TIMER FUNCTIONS (3) Watch timer operation mode register (WTM) The WTM register enables or disables the count clock and operation of the watch timer, sets the interval time of the prescaler, controls the operation of the 5-bit counter, and sets the set time of the watch flag. Set the PRSM0 register before setting the WTM register.
Page 425 CHAPTER 10 WATCH TIMER FUNCTIONS (2/2) WTM7 WTM3 WTM2 Selection of set time of watch flag (0.5 s: f (0.25 s: f μ (977 s: f μ (488 s: f (0.5 s: f (0.25 s: f μ (977 s: f μ...
Page 426: Operation
CHAPTER 10 WATCH TIMER FUNCTIONS 10.4 Operation 10.4.1 Operation as watch timer The watch timer generates an interrupt request signal (INTWT) at fixed time intervals. The watch timer operates using time intervals of 0.25 or 0.5 seconds with the subclock (32.768 kHz) or main clock. The count operation starts when the WTM.WTM1 and WTM.WTM0 bits are set to 11.
Page 427: Operation As Interval Timer
CHAPTER 10 WATCH TIMER FUNCTIONS 10.4.2 Operation as interval timer The watch timer can also be used as an interval timer that repeatedly generates an interrupt request signal (INTWTI) at intervals specified by a preset count value. The interval time can be selected by the WTM4 to WTM7 bits of the WTM register. Table 10-1.
Page 428: Cautions
CHAPTER 10 WATCH TIMER FUNCTIONS Figure 10-2. Operation Timing of Watch Timer/Interval Timer 5-bit counter Overflow Overflow Start Count clock or f Watch timer interrupt INTWT Interrupt time of watch timer (0.5 s) Interrupt time of watch timer (0.5 s) Interval timer interrupt INTWTI Interval time (T)
Page 429: Chapter 11 Functions Of Watchdog Timer 2
CHAPTER 11 FUNCTIONS OF WATCHDOG TIMER 2 11.1 Functions Watchdog timer 2 has the following functions. • Default-start watchdog timer Note 1 → Reset mode: Reset operation upon overflow of watchdog timer 2 (generation of WDT2RES signal) → Non-maskable interrupt request mode: NMI operation upon overflow of watchdog timer 2 (generation of Note 2 INTWDT2 signal) •...
Page 430: Configuration
CHAPTER 11 FUNCTIONS OF WATCHDOG TIMER 2 11.2 Configuration The following shows the block diagram of watchdog timer 2. Figure 11-1. Block Diagram of Watchdog Timer 2 to f to f INTWDT2 Clock to f Output 16-bit input Selector controller counter WDT2RES controller...
Page 431: Registers
CHAPTER 11 FUNCTIONS OF WATCHDOG TIMER 2 11.3 Registers (1) Watchdog timer mode register 2 (WDTM2) The WDTM2 register sets the overflow time and operation clock of watchdog timer 2. This register can be read or written in 8-bit units. This register can be read any number of times, but it can be written only once following reset release.
Page 432 CHAPTER 11 FUNCTIONS OF WATCHDOG TIMER 2 Table 11-2. Watchdog Timer 2 Clock Selection WDCS24 WDCS23 WDCS22 WDCS21 WDCS20 Selected Clock 100 kHz (MIN.) 220 kHz (TYP.) 400 kHz (MAX.) 41.0 ms 18.6 ms 10.2 ms 81.9 ms 37.2 ms 20.5 ms 163.8 ms 74.5 ms...
Page 433: Operation
CHAPTER 11 FUNCTIONS OF WATCHDOG TIMER 2 11.4 Operation Watchdog timer 2 automatically starts in the reset mode following reset release. The WDTM2 register can be written to only once following reset using byte access. To use watchdog timer 2, write the operation mode and the interval time to the WDTM2 register using an 8-bit memory manipulation instruction.
Page 434: Chapter 12 Real-Time Output Function (Rto)
Because RTO can output signals without jitter, it is suitable for controlling a stepper motor. In the V850ES/JJ3, two 6-bit real-time output port channels are provided. The real-time output port can be set to the port mode or real-time output port mode in 1-bit units.
Page 435: Configuration
CHAPTER 12 REAL-TIME OUTPUT FUNCTION (RTO) 12.2 Configuration The block diagram of RTO is shown below. Figure 12-1. Block Diagram of RTO Real-time output Real-time output buffer register nH RTPn4, latch nH (RTBHn) RTPn5 Real-time output Real-time output buffer register nL RTPn0 to latch nL (RTBLn)
Page 436 CHAPTER 12 REAL-TIME OUTPUT FUNCTION (RTO) (1) Real-time output buffer registers nL, nH (RTBLn, RTBHn) The RTBLn and RTBHn registers are 4-bit registers that hold preset output data. These registers are mapped to independent addresses in the peripheral I/O register area. These registers can be read or written in 8-bit or 1-bit units.
Page 437: Registers
CHAPTER 12 REAL-TIME OUTPUT FUNCTION (RTO) 12.3 Registers RTO is controlled using the following two registers. • Real-time output port mode register n (RTPMn) • Real-time output port control register n (RTPCn) (1) Real-time output port mode register n (RTPMn) The RTPMn register selects the real-time output port mode or port mode in 1-bit units.
Page 438 CHAPTER 12 REAL-TIME OUTPUT FUNCTION (RTO) (2) Real-time output port control register n (RTPCn) The RTPCn register is a register that sets the operation mode and output trigger of the real-time output port. The relationship between the operation mode and output trigger of the real-time output port is as shown in Tables 12-3 and 12-4.
Page 439: Operation
CHAPTER 12 REAL-TIME OUTPUT FUNCTION (RTO) 12.4 Operation If the real-time output operation is enabled by setting the RTPCn.RTPOEn bit to 1, the data of the RTBHn and RTBLn registers is transferred to the real-time output latch in synchronization with the generation of the selected transfer trigger (set by the RTPCn.EXTRn and RTPCn.BYTEn bits).
Page 440: Usage
CHAPTER 12 REAL-TIME OUTPUT FUNCTION (RTO) 12.5 Usage (1) Disable real-time output. Clear the RTPCn.RTPOEn bit to 0. (2) Perform initialization as follows. • Set the alternate-function pins of port 5 Set the PFC5.PFC5m bit and PFCE5.PFCE5m bit to 1, and then set the PMC5.PMC5m bit to 1 (m = 0 to 5). •...
Page 441: Chapter 13 A/D Converter
CHAPTER 13 A/D CONVERTER 13.1 Overview The A/D converter converts analog input signals into digital values, has a resolution of 10 bits, and can handle 16 analog input signal channels (ANI0 to ANI15). The A/D converter has the following features. 10-bit resolution 16 channels Successive approximation method...
Page 442: Configuration
CHAPTER 13 A/D CONVERTER 13.3 Configuration The block diagram of the A/D converter is shown below. Figure 13-1. Block Diagram of A/D Converter REF0 ANI0 Sample & hold circuit ADA0CE bit ANI1 ANI2 Voltage comparator & Compare voltage ADA0CE bit ANI13 generation DAC ANI14...
Page 443 CHAPTER 13 A/D CONVERTER (1) Successive approximation register (SAR) The SAR register compares the voltage value of the analog input signal with the output voltage (compare voltage) value of the compare voltage generation DAC, and holds the comparison result starting from the most significant bit (MSB).
Page 444 CHAPTER 13 A/D CONVERTER (12) Compare voltage generation DAC This compare voltage generation DAC is connected between AV and AV and generates a voltage for REF0 comparison with the analog input signal. (13) ANI0 to ANI15 pins These are analog input pins for the 16 A/D converter channels and are used to input analog signals to be converted into digital signals.
Page 445: Registers
CHAPTER 13 A/D CONVERTER 13.4 Registers The A/D converter is controlled by the following registers. • A/D converter mode registers 0, 1, 2 (ADA0M0, ADA0M1, ADA0M2) • A/D converter channel specification register 0 (ADA0S) • Power-fail compare mode register (ADA0PFM) The following registers are also used.
Page 446 CHAPTER 13 A/D CONVERTER (2/2) Trigger mode specification ADA0TMD Software trigger mode External trigger mode/timer trigger mode ADA0EF A/D converter status display A/D conversion stopped A/D conversion in progress Cautions 1. Accessing the ADA0M0 register is prohibited in the following statuses. For details, see 3.4.8 (2) Accessing specific on-chip peripheral I/O registers.
Page 447 CHAPTER 13 A/D CONVERTER (2) A/D converter mode register 1 (ADA0M1) The ADA0M1 register is an 8-bit register that specifies the conversion time. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H Address: FFFFF201H ADA0M1...
Page 448 CHAPTER 13 A/D CONVERTER Table 13-2. Conversion Time Selection in Normal Conversion Mode (ADA0HS1 Bit = 0) <R> A/D Conversion Time ADA0FR3 to ADA0FR0 Stabilization Time + Conversion = 32 MHz = 20 MHz = 16 MHz = 4 MHz Trigger Response Bits Time + Wait Time...
Page 449 CHAPTER 13 A/D CONVERTER <R> Table 13-3. Conversion Time Selection in High-Speed Conversion Mode (ADA0HS1 Bit = 1) ADA0FR3 to A/D Conversion Time ADA0FR0 Bits Conversion Time = 32 MHz = 20 MHz = 16 MHz = 4 MHz Trigger (+ Stabilization Time) Response Time...
Page 450 CHAPTER 13 A/D CONVERTER (3) A/D converter mode register 2 (ADA0M2) The ADA0M2 register specifies the hardware trigger mode. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: Address: FFFFF203H ADA0M2 ADA0TMD1 ADA0TMD0...
Page 451 CHAPTER 13 A/D CONVERTER (4) A/D converter channel specification register 0 (ADA0S) The ADA0S register specifies the pin that inputs the analog voltage to be converted into a digital signal. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
Page 452 CHAPTER 13 A/D CONVERTER (5) A/D conversion result registers n, nH (ADA0CRn, ADA0CRnH) The ADA0CRn and ADA0CRnH registers store the A/D conversion results. These registers are read-only, in 16-bit or 8-bit units. However, specify the ADA0CRn register for 16-bit access and the ADA0CRnH register for 8-bit access.
Page 453 CHAPTER 13 A/D CONVERTER The relationship between the analog voltage input to the analog input pins (ANI0 to ANI15) and the A/D conversion result (ADA0CRn register) is as follows. × 1,024 + 0.5) SAR = INT ( REF0 = SAR × 64 Note ADA0CR REF0...
Page 454 CHAPTER 13 A/D CONVERTER (6) Power-fail compare mode register (ADA0PFM) The ADA0PFM register is an 8-bit register that sets the power-fail compare mode. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: Address: FFFFF204H...
Page 455 CHAPTER 13 A/D CONVERTER (7) Power-fail compare threshold value register (ADA0PFT) The ADA0PFT register sets the compare value in the power-fail compare mode. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. After reset: 00H Address: FFFFF205H ADA0PFT...
Page 456: Operation
CHAPTER 13 A/D CONVERTER 13.5 Operation 13.5.1 Basic operation <1> Set the operation mode, trigger mode, and conversion time for executing A/D conversion by using the ADA0M0, ADA0M1, ADA0M2, and ADA0S registers. When the ADA0CE bit of the ADA0M0 register is set, conversion is started in the software trigger mode and the A/D converter waits for a trigger in the external or timer trigger mode.
Page 457: Conversion Operation Timing
CHAPTER 13 A/D CONVERTER 13.5.2 Conversion operation timing Figure 13-3. Conversion Operation Timing (Continuous Conversion) (1) Operation in normal conversion mode (ADA0HS1 bit = 0) ADA0M0.ADA0CE bit First conversion Second conversion Setup Sampling A/D conversion Wait Setup Sampling Processing state INTAD signal Stabilization Conversion time...
Page 458: Trigger Mode
CHAPTER 13 A/D CONVERTER 13.5.3 Trigger mode The timing of starting the conversion operation is specified by setting a trigger mode. The trigger mode includes a software trigger mode and hardware trigger modes. The hardware trigger modes include timer trigger modes 0 and 1, and external trigger mode.
Page 459 CHAPTER 13 A/D CONVERTER (3) Timer trigger mode In this mode, converting the signal of the analog input pin (ANI0 to ANI15) specified by the ADA0S register is started by the compare match interrupt request signal (INTTP2CC0 or INTTP2CC1) of the capture/compare register connected to the timer.
Page 460: Operation Mode
CHAPTER 13 A/D CONVERTER 13.5.4 Operation mode Four operation modes are available as the modes in which to set the ANI0 to ANI15 pins: continuous select mode, continuous scan mode, one-shot select mode, and one-shot scan mode. The operation mode is selected by the ADA0M0.ADA0MD1 and ADA0M0.ADA0MD0 bits. (1) Continuous select mode In this mode, the voltage of one analog input pin selected by the ADA0S register is continuously converted into a digital value.
Page 461 CHAPTER 13 A/D CONVERTER Figure 13-5. Timing Example of Continuous Scan Mode Operation (ADA0S Register = 03H) (a) Timing example ANI0 Data 1 Data ANI1 Data Data Data Data ANI2 ANI3 Data Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7...
Page 462 CHAPTER 13 A/D CONVERTER (3) One-shot select mode In this mode, the voltage on the analog input pin specified by the ADA0S register is converted into a digital value only once. The conversion result is stored in the ADA0CRn register corresponding to the analog input pin. In this mode, an analog input pin and an ADA0CRn register correspond on a one-to-one basis.
Page 463 CHAPTER 13 A/D CONVERTER Figure 13-7. Timing Example of One-Shot Scan Mode Operation (ADA0S Register = 03H) (a) Timing example ANI0 Data 1 ANI1 Data Data ANI2 ANI3 Data Data 1 Data 2 Data 3 Data 4 conversion (ANI0) (ANI1) (ANI2) (ANI3) Data 1...
Page 464: Power-Fail Compare Mode
CHAPTER 13 A/D CONVERTER 13.5.5 Power-fail compare mode The A/D conversion end interrupt request signal (INTAD) can be controlled as follows by the ADA0PFM and ADA0PFT registers. • When the ADA0PFM.ADA0PFE bit = 0, the INTAD signal is generated each time conversion is completed (normal use of the A/D converter).
Page 465 CHAPTER 13 A/D CONVERTER (1) Continuous select mode In this mode, the result of converting the voltage of the analog input pin specified by the ADA0S register is compared with the set value of the ADA0PFT register. If the result of power-fail comparison matches the condition set by the ADA0PFC bit, the conversion result is stored in the ADA0CRn register, and the INTAD signal is generated.
Page 466 CHAPTER 13 A/D CONVERTER Figure 13-9. Timing Example of Continuous Scan Mode Operation (When Power-Fail Comparison Is Made: ADA0S Register = 03H) (a) Timing example ANI0 Data Data ANI1 Data Data Data Data ANI2 ANI3 Data Data 1 Data 2 Data 3 Data 4 Data 5...
Page 467 CHAPTER 13 A/D CONVERTER (3) One-shot select mode In this mode, the result of converting the voltage of the analog input pin specified by the ADA0S register is compared with the set value of the ADA0PFT register. If the result of power-fail comparison matches the condition set by the ADA0PFC bit, the conversion result is stored in the ADA0CRn register, and the INTAD signal is generated.
Page 468 CHAPTER 13 A/D CONVERTER Figure 13-11. Timing Example of One-Shot Scan Mode Operation (When Power-Fail Comparison Is Made: ADA0S Register = 03H) (a) Timing example ANI0 Data ANI1 Data Data ANI2 ANI3 Data Data 1 Data 2 Data 3 Data 4 conversion (ANI0) (ANI1)
Page 469: Cautions
CHAPTER 13 A/D CONVERTER 13.6 Cautions (1) When A/D converter is not used When the A/D converter is not used, the power consumption can be reduced by clearing the ADA0M0.ADA0CE bit to 0. (2) Input range of ANI0 to ANI15 pins Input the voltage within the specified range to the ANI0 to ANI15 pins.
Page 470 CHAPTER 13 A/D CONVERTER (5) Interrupt request flag (ADIF) The interrupt request flag (ADIF) is not cleared even if the contents of the ADA0S register are changed. If the analog input pin is changed during A/D conversion, therefore, the result of converting the previously selected analog input signal may be stored and the conversion end interrupt request flag may be set immediately before the ADA0S register is rewritten.
Page 471 CHAPTER 13 A/D CONVERTER (7) AV REF0 (a) The AV pin is used as the power supply pin of the A/D converter and also supplies power to the REF0 alternate-function ports. In an application where a backup power supply is used, be sure to supply the same voltage as V to the AV pin as shown in Figure 13-15.
Page 472 CHAPTER 13 A/D CONVERTER (10) High-speed conversion mode In the high-speed conversion mode, rewriting of the ADA0M0, ADA0M2, ADA0S, ADA0PFM, and ADA0PFT registers and trigger input during the stabilization time are prohibited. (11) A/D conversion time A/D conversion time is the total time of stabilization time, conversion time, wait time, and trigger response time (for details of these times, refer to Table 13-2 Conversion Time Selection in Normal Conversion Mode (ADA0HS1 Bit = 0) and Table 13-3 Conversion Time Selection in High-Speed Conversion Mode (ADA0HS1 Bit = 1)).
Page 473: How To Read A/D Converter Characteristics Table
CHAPTER 13 A/D CONVERTER 13.7 How to Read A/D Converter Characteristics Table This section describes the terms related to the A/D converter. (1) Resolution The minimum analog input voltage that can be recognized, i.e., the ratio of an analog input voltage to 1 bit of digital output is called 1 LSB (least significant bit).
Page 474 CHAPTER 13 A/D CONVERTER (3) Quantization error This is an error of ±1/2 LSB that inevitably occurs when an analog value is converted into a digital value. Because the A/D converter converts analog input voltages in a range of ±1/2 LSB into the same digital codes, a quantization error is unavoidable.
Page 475 CHAPTER 13 A/D CONVERTER (5) Full-scale error This is the difference between the actually measured analog input voltage and its theoretical value when the digital output changes from 1…110 to 1…111 (full scale − 3/2 LSB). Figure 13-19. Full-Scale Error Full-scale error 2 AV REF0 −...
Page 476 CHAPTER 13 A/D CONVERTER (7) Integral linearity error This error indicates the extent to which the conversion characteristics differ from the ideal linear relationship. It indicates the maximum value of the difference between the actually measured value and its theoretical value where the zero-scale error and full-scale error are 0.
Page 477: Chapter 14 D/A Converter
CHAPTER 14 D/A CONVERTER 14.1 Functions The D/A converter has the following functions. 8-bit resolution × 2 channels (DA0CS0, DA0CS1) R-2R ladder method μ Settling time: 3 s max. (when AV is 3.0 to 3.6 V and external load is 20 pF) REF1 ×...
Page 478: Registers
CHAPTER 14 D/A CONVERTER The D/A converter includes the following hardware. Table 14-1. Configuration of D/A Converter Item Configuration Control registers D/A converter mode register (DA0M) D/A conversion value setting registers 0, 1 (DA0CS0, DA0CS1) 14.3 Registers The registers that control the D/A converter are as follows. •...
Page 479 CHAPTER 14 D/A CONVERTER (2) D/A conversion value setting registers 0, 1 (DA0CS0, DA0CS1) The DA0CS0 and DA0CS1 registers set the analog voltage value output to the ANO0 and ANO1 pins. These registers can be read or written in 8-bit units. Reset sets these registers to 00H.
Page 480: Operation
CHAPTER 14 D/A CONVERTER 14.4 Operation 14.4.1 Operation in normal mode D/A conversion is performed using a write operation to the DA0CSn register as the trigger. The setting method is described below. <1> Set the DA0M.DA0MDn bit to 0 (normal mode). <2>...
Page 481: Cautions
CHAPTER 14 D/A CONVERTER 14.4.3 Cautions Observe the following cautions when using the D/A converter of the V850ES/JJ3. (1) Do not change the set value of the DA0CSn register while the trigger signal is being issued in the real-time output mode.
Page 482: Chapter 15 Asynchronous Serial Interface A (Uarta)
15.1 Mode Switching of UARTA and Other Serial Interfaces 15.1.1 CSIB4 and UARTA0 mode switching In the V850ES/JJ3, CSIB4 and UARTA0 are alternate functions of the same pin and therefore cannot be used simultaneously. Set UARTA0 in advance, using the PMC3 and PFC3 registers, before use.
Page 483: Uarta2 And I 2 C00 Mode Switching
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.1.2 UARTA2 and I C00 mode switching In the V850ES/JJ3, UARTA2 and I C00 are alternate functions of the same pin and therefore cannot be used simultaneously. Set UARTA2 in advance, using the PMC3 and PFC3 registers, before use.
Page 484: Uarta1 And I 2 C02 Mode Switching
15.1.3 UARTA1 and I C02 mode switching In the V850ES/JJ3, UARTA1 and I C02 are alternate functions of the same pin and therefore cannot be used simultaneously. Set UARTA1 in advance, using the PMC9, PFC9, and PMCE9 registers, before use.
Page 485: Features
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.2 Features Transfer rate: 300 bps to 625 kbps (using internal system clock of 32 MHz and dedicated baud rate generator) Full-duplex communication: Internal UARTAn receive data register (UAnRX) Internal UARTAn transmit data register (UAnTX) 2-pin configuration: TXDAn: Transmit data output pin RXDAn: Receive data input pin...
Page 486: Configuration
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.3 Configuration The block diagram of the UARTAn is shown below. <R> Figure 15-4. Block Diagram of Asynchronous Serial Interface An Internal bus INTUAnT INTUAnR Transmission Reception unit UAnTX UAnRX unit Receive Transmit Transmission Reception shift register...
Page 487 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) UARTAn control register 0 (UAnCTL0) The UAnCTL0 register is an 8-bit register used to specify the UARTAn operation. (2) UARTAn control register 1 (UAnCTL1) The UAnCTL1 register is an 8-bit register used to select the input clock for the UARTAn. (3) UARTAn control register 2 (UAnCTL2) The UAnCTL2 register is an 8-bit register used to control the baud rate for the UARTAn.
Page 488: Registers
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.4 Registers (1) UARTAn control register 0 (UAnCTL0) The UAnCTL0 register is an 8-bit register that controls the UARTAn serial transfer operation. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 10H.
Page 489 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (2/2) UAnDIR Transfer direction selection MSB-first transfer LSB-first transfer • This register can be rewritten only when the UAnPWR bit = 0 or the UAnTXE bit = the UAnRXE bit = 0. • When transmission and reception are performed in the LIN format, set the UAnDIR bit to 1.
Page 490 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (2) UARTAn control register 1 (UAnCTL1) For details, see 15.7 (2) UARTAn control register 1 (UAnCTL1). (3) UARTAn control register 2 (UAnCTL2) For details, see 15.7 (3) UARTAn control register 2 (UAnCTL2). (4) UARTAn option control register 0 (UAnOPT0) The UAnOPT0 register is an 8-bit register that controls the serial transfer operation of the UARTAn register.
Page 491 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (2/2) UAnSLS2 UAnSLS1 UAnSLS0 SBF transmit length selection 13-bit output (reset value) 14-bit output 15-bit output 16-bit output 17-bit output 18-bit output 19-bit output 20-bit output This register can be set when the UAnPWR bit = 0 or when the UAnTXE bit = 0. UAnTDL Transmit data level bit Normal output of transfer data...
Page 492 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) After reset: 00H Address: UA0STR FFFFFA04H, UA1STR FFFFFA14H, UA2STR FFFFFA24H, UA3STR FFFFFA34H <2> <1> <7> <0> UAnTSF UAnSTR UAnPE UAnFE UAnOVE (n = 0 to 3) UAnTSF Transfer status flag • When the UAnPWR bit = 0 or the UAnTXE bit = 0 has been set. •...
Page 493 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (6) UARTAn receive data register (UAnRX) The UAnRX register is an 8-bit buffer register that stores parallel data converted by the receive shift register. The data stored in the receive shift register is transferred to the UAnRX register upon completion of reception of 1 byte of data.
Page 494: Interrupt Request Signals
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.5 Interrupt Request Signals The following two interrupt request signals are generated from UARTAn. • Reception complete interrupt request signal (INTUAnR) • Transmission enable interrupt request signal (INTUAnT) The default priority for these two interrupt request signals is reception complete interrupt request signal then transmission enable interrupt request signal.
Page 495: Operation
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.6 Operation 15.6.1 Data format Full-duplex serial data reception and transmission is performed. As shown in Figure 15-5, one data frame of transmit/receive data consists of a start bit, character bits, parity bit, and stop bit(s).
Page 496 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) Figure 15-5. UARTA Transmit/Receive Data Format (a) 8-bit data length, LSB first, even parity, 1 stop bit, transfer data: 55H 1 data frame Start Parity Stop (b) 8-bit data length, MSB first, even parity, 1 stop bit, transfer data: 55H 1 data frame Start Parity...
Page 497: Sbf Transmission/Reception Format
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.6.2 SBF transmission/reception format The V850ES/JJ3 has an SBF (Sync Break Field) transmission/reception control function to enable use of the LIN function. Remark LIN stands for Local Interconnect Network and is a low-speed (1 to 20 kbps) serial communication protocol intended to aid the cost reduction of an automotive network.
Page 498 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) Figure 15-7. LIN Reception Manipulation Outline Wake-up Sync Check signal break Sync Identifier DATA DATA frame field field field field field field Note 2 Data Data Note 5 SF reception 13 bits ID reception transmission transmission Data transmission...
Page 499: Sbf Transmission
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.6.3 SBF transmission When the UAnCTL0.UAnPWR bit = UAnCTL0.UAnTXE bit = 1, the transmission enabled status is entered, and SBF transmission is started by setting (to 1) the SBF transmission trigger (UAnOPT0.UAnSTT bit). Thereafter, a low level the width of bits 13 to 20 specified by the UAnOPT0.UAnSLS2 to UAnOPT0.UAnSLS0 bits is output.
Page 500: Sbf Reception
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.6.4 SBF reception The reception enabled status is achieved by setting the UAnCTL0.UAnPWR bit to 1 and then setting the UAnCTL0.UAnRXE bit to 1. The SBF reception wait status is set by setting the SBF reception trigger (UAnOPT0.UAnSTR bit) to 1. In the SBF reception wait status, similarly to the UART reception wait status, the RXDAn pin is monitored and start bit detection is performed.
Page 501 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) Figure 15-9. SBF Reception (2/2) (b) SBF reception error (detection of stop bit in 10.5 or fewer bits) RXDAn 10.5 UAnSRF INTUAnR interrupt User’s Manual U18376EJ3V0UD...
Page 502: Uart Transmission
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.6.5 UART transmission A high level is output to the TXDAn pin by setting the UAnCTL0.UAnPWR bit to 1. Next, the transmission enabled status is set by setting the UAnCTL0.UAnTXE bit to 1, and transmission is started by writing transmit data to the UAnTX register.
Page 503: Continuous Transmission Procedure
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.6.6 Continuous transmission procedure UARTAn can write the next transmit data to the UAnTX register when the UARTAn transmit shift register starts the shift operation. The transmit timing of the UARTAn transmit shift register can be judged from the transmission enable interrupt request signal (INTUAnT).
Page 504 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) Figure 15-12. Continuous Transmission Operation Timing (a) Transmission start Start Data (1) Parity Stop Start Data (2) Parity Stop Start TXDAn UAnTX Data (1) Data (2) Data (3) Transmission Data (2) Data (1) shift register INTUAnT UAnTSF...
Page 505: Uart Reception
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.6.7 UART reception The reception wait status is set by setting the UAnCTL0.UAnPWR bit to 1 and then setting the UAnCTL0.UAnRXE bit to 1. In the reception wait status, the RXDAn pin is monitored and start bit detection is performed. Start bit detection is performed using a two-step detection routine.
Page 506: Reception Errors
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.6.8 Reception errors Errors during a receive operation are of three types: parity errors, framing errors, and overrun errors. Data reception result error flags are set in the UAnSTR register and a reception complete interrupt request signal (INTUAnR) is output when an error occurs.
Page 507 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) When reception errors occur, perform the following procedures depending upon the kind of error. • Parity error If false data is received due to problems such as noise in the reception line, discard the received data and retransmit.
Page 508: Parity Types And Operations
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.6.9 Parity types and operations Caution When using the LIN function, fix the UAnPS1 and UAnPS0 bits of the UAnCTL0 register to 00. The parity bit is used to detect bit errors in the communication data. Normally the same parity is used on the transmission side and the reception side.
Page 509: Receive Data Noise Filter
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.6.10 Receive data noise filter This filter samples the RXDAn pin using the base clock of the prescaler output. When the same sampling value is read twice, the match detector output changes and the RXDAn signal is sampled as the input data.
Page 510: Dedicated Baud Rate Generator
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.7 Dedicated Baud Rate Generator The dedicated baud rate generator consists of a source clock selector block and an 8-bit programmable counter, and generates a serial clock during transmission and reception with UARTAn. Regarding the serial clock, a dedicated baud rate generator output can be selected for each channel.
Page 511 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (2) UARTAn control register 1 (UAnCTL1) The UAnCTL1 register is an 8-bit register that selects the UARTAn base clock. This register can be read or written in 8-bit units. Reset sets this register to 00H. Caution Clear the UAnCTL0.UAnPWR bit to 0 before rewriting the UAnCTL1 register.
Page 512 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (3) UARTAn control register 2 (UAnCTL2) The UAnCTL2 register is an 8-bit register that selects the baud rate (serial transfer speed) clock of UARTAn. This register can be read or written in 8-bit units. Reset sets this register to FFH.
Page 513 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (4) Baud rate The baud rate is obtained by the following equation. UCLK Baud rate = [bps] 2 × k When using the internal clock, the equation will be as follows (when using the ASCKA0 pin as clock at UARTA0, calculate using the above equation).
Page 514 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) To set the baud rate, perform the following calculation for setting the UAnCTL1 and UAnCTL2 registers (when using internal clock). <1> Set k to fxx/(2 × target baud rate) and m to 0. <2>...
Page 515 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (5) Allowable baud rate range during reception The baud rate error range at the destination that is allowable during reception is shown below. Caution The baud rate error during reception must be set within the allowable error range using the following equation.
Page 516 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) Therefore, the maximum baud rate that can be received by the destination is as follows. − BRmax = (FLmin/11) Brate 21k + 2 Similarly, obtaining the following maximum allowable transfer rate yields the following. 21k −...
Page 517 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) (6) Baud rate during continuous transmission During continuous transmission, the transfer rate from the stop bit to the next start bit is usually 2 base clocks longer. However, timing initialization is performed via start bit detection by the receiving side, so this has no influence on the transfer result.
Page 518: Cautions
CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) 15.8 Cautions (1) When the clock supply to UARTAn is stopped (for example, in IDLE1, IDLE2, or STOP mode), the operation stops with each register retaining the value it had immediately before the clock supply was stopped. The TXDAn pin output also holds and outputs the value it had immediately before the clock supply was stopped.
Page 519: Chapter 16 3-Wire Variable-Length Serial I/O (Csib)
16.1 Mode Switching of CSIB and Other Serial Interfaces 16.1.1 CSIB4 and UARTA0 mode switching In the V850ES/JJ3, CSIB4 and UARTA0 are alternate functions of the same pin and therefore cannot be used simultaneously. Set CSIB4, in advance, using the PMC3 and PFC3 registers, before use.
Page 520: Csib0 And I C01 Mode Switching
CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 16.1.2 CSIB0 and I C01 mode switching In the V850ES/JJ3, CSIB0 and I C01 are alternate functions of the same pin and therefore cannot be used simultaneously. Set CSIB0 in advance, using the PMC4 and PFC4 registers, before use.
Page 521: Configuration
CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 16.3 Configuration The following shows the block diagram of CSIBn. Figure 16-3. Block Diagram of CSIBn Internal bus CBnCTL1 CBnCTL0 CBnCTL2 CBnSTR INTCBnT Controller INTCBnR Phase control CCLK BRGm CBnTX SCKBn Phase SO latch SOBn control SIBn...
Page 522 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (1) CSIBn receive data register (CBnRX) The CBnRX register is a 16-bit buffer register that holds receive data. This register is read-only, in 16-bit units. The receive operation is started by reading the CBnRX register in the reception enabled status. If the transfer data length is 8 bits, the lower 8 bits of this register are read-only in 8-bit units as the CBnRXL register.
Page 523: Registers
CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 16.4 Registers The following registers are used to control CSIBn. • CSIBn control register 0 (CBnCTL0) • CSIBn control register 1 (CBnCTL1) • CSIBn control register 2 (CBnCTL2) • CSIBn status register (CBnSTR) (1) CSIBn control register 0 (CBnCTL0) CBnCTL0 is a register that controls the CSIBn serial transfer operation.
Page 524 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2/3) Note CBnDIR Specification of transfer direction mode (MSB/LSB) MSB-first transfer LSB-first transfer Note CBnTMS Transfer mode specification Single transfer mode Continuous transfer mode [In single transfer mode] The reception complete interrupt request signal (INTCBnR) is generated. Even if transmission is enabled (CBnTXE bit = 1), the transmission enable interrupt request signal (INTCBnT) is not generated.
Page 525 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (3/3) CBnSCE Specification of start transfer disable/enable Communication start trigger invalid Communication start trigger valid • In master mode This bit enables or disables the communication start trigger. (a) In single transmission or transmission/reception mode, or continuous transmission or continuous transmission/reception mode The setting of the CBnSCE bit has no influence on communication operation.
Page 526 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2) CSIBn control register 1 (CBnCTL1) CBnCTL1 is an 8-bit register that controls the CSIBn serial transfer operation. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H. Caution The CBnCTL1 register can be rewritten only when the CBnCTL0.CBnPWR bit = 0.
Page 527 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (3) CSIBn control register 2 (CBnCTL2) CBnCTL2 is an 8-bit register that controls the number of CSIBn serial transfer bits. This register can be read or written in 8-bit units. Reset sets this register to 00H. Caution The CBnCTL2 register can be rewritten only when the CBnCTL0.CBnPWR bit = 0 or when both the CBnTXE and CBnRXE bits = 0.
Page 528 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (a) Transfer data length change function The CSIBn transfer data length can be set in 1-bit units between 8 and 16 bits using the CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits. When the transfer bit length is set to a value other than 16 bits, set the data to the CBnTX or CBnRX register starting from the LSB, regardless of whether the transfer start bit is the MSB or LSB.
Page 529 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (4) CSIBn status register (CBnSTR) CBnSTR is an 8-bit register that displays the CSIBn status. This register can be read or written in 8-bit or 1-bit units, but the CBnTSF flag is read-only. Reset sets this register to 00H.
Page 530: Interrupt Request Signals
CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 16.5 Interrupt Request Signals CSIBn can generate the following two types of interrupt request signals. • Reception complete interrupt request signal (INTCBnR) • Transmission enable interrupt request signal (INTCBnT) Of these two interrupt request signals, the reception complete interrupt request signal has the higher priority by default, and the priority of the transmission enable interrupt request signal is lower.
Page 531: Operation
CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 16.6 Operation 16.6.1 Single transfer mode (master mode, transmission mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (CBnCTL1.CBnCKP and CBnCTL1.CBnDAP bits = 00), communication clock (f ) = f /2 (CBnCTL1.CBnCKS2 to CBnCTL1.CBnCKS0 bits = 000), transfer data length CCLK = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0000) (1) Operation flow...
Page 532 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2) Operation timing CBnTSF bit INTCBnR signal SCKBn pin SOBn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1...
Page 533: Single Transfer Mode (Master Mode, Reception Mode)
CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 16.6.2 Single transfer mode (master mode, reception mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (CBnCTL1.CBnCKP and CBnCTL1.CBnDAP bits = 00), communication clock (f ) = f /2 (CBnCTL1.CBnCKS2 to CBnCTL1.CBnCKS0 bits = 000), transfer data length CCLK = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0000) (1) Operation flow...
Page 534 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2) Operation timing CBnTSF bit INTCBnR signal SCKBn pin SIBn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2...
Page 535: Single Transfer Mode (Master Mode, Transmission/Reception Mode)
CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 16.6.3 Single transfer mode (master mode, transmission/reception mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (CBnCTL1.CBnCKP and CBnCTL1.CBnDAP bits = 00), communication clock (f ) = f /2 (CBnCTL1.CBnCKS2 to CBnCTL1.CBnCKS0 bits = 000), transfer data length CCLK = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0000) (1) Operation flow...
Page 536 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2) Operation timing CBnTSF bit INTCBnR signal SCKBn pin SOBn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1...
Page 537: Single Transfer Mode (Slave Mode, Transmission Mode)
CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 16.6.4 Single transfer mode (slave mode, transmission mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (CBnCTL1.CBnCKP and CBnCTL1.CBnDAP bits = 00), communication clock (f ) = external clock (SCKBn) (CBnCTL1.CBnCKS2 to CBnCTL1.CBnCKS0 bits = 111), CCLK transfer data length = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0000) (1) Operation flow...
Page 538 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2) Operation timing CBnTSF bit INTCBnR signal SCKBn pin SOBn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1...
Page 539: Single Transfer Mode (Slave Mode, Reception Mode)
CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 16.6.5 Single transfer mode (slave mode, reception mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (CBnCTL1.CBnCKP and CBnCTL1.CBnDAP bits = 00), communication clock (f ) = external clock (SCKBn) (CBnCTL1.CBnCKS2 to CBnCTL1.CBnCKS0 bits = 111), CCLK transfer data length = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0000) (1) Operation flow...
Page 540 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2) Operation timing CBnTSF bit INTCBnR signal SCKBn pin SIBn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0...
Page 541: Single Transfer Mode (Slave Mode, Transmission/Reception Mode)
CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 16.6.6 Single transfer mode (slave mode, transmission/reception mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (CBnCTL1.CBnCKP and CBnCTL1.CBnDAP bits = 00), communication clock (f ) = external clock (SCKBn) (CBnCTL1.CBnCKS2 to CBnCTL1.CBnCKS0 bits = 111), CCLK transfer data length = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0000) (1) Operation flow...
Page 542 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2) Operation timing CBnTSF bit INTCBnR signal SCKBn pin SOBn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0...
Page 543: Continuous Transfer Mode (Master Mode, Transmission Mode)
CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 16.6.7 Continuous transfer mode (master mode, transmission mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (CBnCTL1.CBnCKP and CBnCTL1.CBnDAP bits = 00), communication clock (f ) = f /2 (CBnCTL1.CBnCKS2 to CBnCTL1.CBnCKS0 bits = 000), transfer data length CCLK = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0000) (1) Operation flow...
Page 544 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2) Operation timing CBnTSF bit INTCBnT signal INTCBnR signal SCKBn pin SOBn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2...
Page 545: Continuous Transfer Mode (Master Mode, Reception Mode)
CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 16.6.8 Continuous transfer mode (master mode, reception mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (CBnCTL1.CBnCKP and CBnCTL1.CBnDAP bits = 00), communication clock (f ) = f /2 (CBnCTL1.CBnCKS2 to CBnCTL1.CBnCKS0 bits = 000), transfer data length CCLK = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0000) User’s Manual U18376EJ3V0UD...
Page 546 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (1) Operation flow START CBnCTL1 register ← 00H CBnCTL2 register ← 00H (1), (2), (3) CBnCTL0 register ← A3H CBnRX register dummy read Start reception INTCBnR interrupt generated? CBnOVE bit = 1? (CBnSTR) Is data being received CBnSCE bit = 0 last data?
Page 547 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2) Operation timing CBnTSF bit INTCBnR signal CBnSCE bit SCKBn pin SOBn pin SIBn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1...
Page 548: Continuous Transfer Mode (Master Mode, Transmission/Reception Mode)
CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 16.6.9 Continuous transfer mode (master mode, transmission/reception mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (CBnCTL1.CBnCKP and CBnCTL1.CBnDAP bits = 00), communication clock (f ) = f /2 (CBnCTL1.CBnCKS2 to CBnCTL1.CBnCKS0 bits = 000), transfer data length CCLK = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0000) User’s Manual U18376EJ3V0UD...
Page 549 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (1) Operation flow START CBnCTL1 register ← 00H CBnCTL2 register ← 00H (1), (2), (3) CBnCTL0 register ← E3H Write CBnTX register Start transmission/reception INTCBnT interrupt (6), (11) generated? (11) Is data being transmitted last data? Write CBnTX register INTCBnR interrupt...
Page 550 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2) Operation timing (1/2) CBnTSF bit INTCBnT signal INTCBnR signal SCKBn pin SOBn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1...
Page 551 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2/2) (11) The transfer of the transmit data from the CBnTX register to the shift register is completed and the INTCBnT signal is generated. To end continuous transmission/reception with the current transmission/reception, do not write to the CBnTX register. (12) When the next transmit data is not written to the CBnTX register before transfer completion, stop the serial clock output to the SCKBn pin after transfer completion, and clear the CBnTSF bit to 0.
Page 552: Continuous Transfer Mode (Slave Mode, Transmission Mode)
CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 16.6.10 Continuous transfer mode (slave mode, transmission mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (CBnCTL1.CBnCKP and CBnCTL1.CBnDAP bits = 00), communication clock (f ) = external clock (SCKBn) (CBnCTL1.CBnCKS2 to CBnCTL1.CBnCKS0 bits = 111), CCLK transfer data length = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0000) (1) Operation flow...
Page 553 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2) Operation timing CBnTSF bit INTCBnT signal SCKBn pin SOBn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1...
Page 554: Continuous Transfer Mode (Slave Mode, Reception Mode)
CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 16.6.11 Continuous transfer mode (slave mode, reception mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (CBnCTL1.CBnCKP and CBnCTL1.CBnDAP bits = 00), communication clock (f ) = external clock (SCKBn) (CBnCTL1.CBnCKS2 to CBnCTL1.CBnCKS0 bits = 111), CCLK transfer data length = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0000) User’s Manual U18376EJ3V0UD...
Page 555 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (1) Operation flow START CBnCTL1 register ← 07H CBnCTL2 register ← 00H (1), (2), (3) CBnCTL0 register ← A3H CBnRX register dummy read SCKBn pin input started? Reception start INTCBnR interrupt generated? CBnOVE bit = 1? (CBnSTR) CBnSCE bit = 0 (CBnCTL0)
Page 556 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2) Operation timing CBnTSF bit INTCBnR signal CBnSCE bit SCKBn pin SIBn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2...
Page 557: Continuous Transfer Mode (Slave Mode, Transmission/Reception Mode)
CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 16.6.12 Continuous transfer mode (slave mode, transmission/reception mode) MSB first (CBnCTL0.CBnDIR bit = 0), communication type 1 (CBnCTL1.CBnCKP and CBnCTL1.CBnDAP bits = 00), communication clock (f ) = external clock (SCKBn) (CBnCTL1.CBnCKS2 to CBnCTL1.CBnCKS0 bits = 111), CCLK transfer data length = 8 bits (CBnCTL2.CBnCL3 to CBnCTL2.CBnCL0 bits = 0000) User’s Manual U18376EJ3V0UD...
Page 558 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (1) Operation flow START CBnCTL1 register ← 07H CBnCTL2 register ← 00H (1), (2), (3) CBnCTL0 register ← E3H Write CBnTX register SCKBn pin input started? Start transmission/reception INTCBnT interrupt (6), (11) generated? (11) Is data being transmitted last data?
Page 559 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2) Operation timing (1/2) CBnTSF bit INTCBnT signal INTCBnR signal SCKBn pin SOBn pin Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2...
Page 560 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2/2) (12) When the clock of the transfer data length set with the CBnCTL2 register is input without writing to the CBnTX register, the INTCBnR signal is generated. Clear the CBnTSF bit to 0 to end transmission/reception.
Page 561: Reception Error
CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 16.6.13 Reception error When transfer is performed with reception enabled (CBnCTL0.CBnRXE bit = 1) in the continuous transfer mode, the reception completion interrupt request signal (INTCBnR) is generated again when the next receive operation is completed before the CBnRX register is read after the INTCBnR signal is generated, and the overrun error flag (CBnSTR.CBnOVE) is set to 1.
Page 562: Clock Timing
CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 16.6.14 Clock timing (1/2) (i) Communication type 1 (CBnCKP and CBnDAP bits = 00) SCKBn pin SIBn capture SOBn pin Reg-R/W INTCBnT Note 1 interrupt INTCBnR Note 2 interrupt CBnTSF bit (ii) Communication type 3 (CBnCKP and CBnDAP bits = 10) SCKBn pin SIBn capture SOBn pin...
Page 563 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2/2) (iii) Communication type 2 (CBnCKP and CBnDAP bits = 01) SCKBn pin SIBn capture SOBn pin Reg-R/W INTCBnT Note 1 interrupt INTCBnR Note 2 interrupt CBnTSF bit (iv) Communication type 4 (CBnCKP and CBnDAP bits = 11) SCKBn pin SIBn capture SOBn pin...
Page 564: Output Pins
CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 16.7 Output Pins (1) SCKBn pin When CSIBn operation is disabled (CBnCTL0.CBnPWR bit = 0), the SCKBn pin output status is as follows. CBnCKP CBnCKS2 CBnCKS1 CBnCKS0 SCKBn Pin Output High impedance Other than above Fixed to high level High impedance Other than above...
Page 565: Baud Rate Generator
CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 16.8 Baud Rate Generator The BRG1 to BRG3 and CSIB0 to CSIB5 baud rate generators are connected as shown in the following block diagram. BRG1 BRG1 CSIB0 CSIB1 BRG2 BRG2 CSIB2 CSIB3 BRG3 BRG3 CSIB4 CSIB5...
Page 566: Baud Rate Generation
CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) (2) Prescaler compare registers 1 to 3 (PRSCM1 to PRSCM3) The PRSCM1 to PRSCM3 registers are 8-bit compare registers. These registers can be read or written in 8-bit units. Reset sets these registers to 00H. After reset: 00H Address: PRSCM1 FFFFF321H, PRSCM2 FFFFF325H, PRSCM3 FFFFF329H...
Page 567: Cautions
CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB) 16.9 Cautions (1) When transferring transmit data and receive data using DMA transfer, error processing cannot be performed even if an overrun error occurs during serial transfer. Check that the no overrun error has occurred by reading the CBnSTR.CBnOVE bit after DMA transfer has been completed.
Page 568: Chapter 17 I C Bus
C Bus and Other Serial Interfaces 17.1.1 UARTA2 and I C00 mode switching In the V850ES/JJ3, UARTA2 and I C00 are alternate functions of the same pin and therefore cannot be used simultaneously. Set I C00 in advance, using the PMC3 and PFC3 registers, before use.
Page 569: Csib0 And I 2 C01 Mode Switching
C BUS 17.1.2 CSIB0 and I C01 mode switching In the V850ES/JJ3, CSIB0 and I C01 are alternate functions of the same pin and therefore cannot be used simultaneously. Set I C01 in advance, using the PMC4 and PFC4 registers, before use.
Page 570: Uarta1 And I 2 C02 Mode Switching
C BUS 17.1.3 UARTA1 and I C02 mode switching In the V850ES/JJ3, UARTA1 and I C02 are alternate functions of the same pin and therefore cannot be used simultaneously. Set I C02 in advance, using the PMC9, PFC9, and PMCE9 registers, before use.
Page 571: Features
CHAPTER 17 I C BUS 17.2 Features C00 to I C02 have the following two modes. • Operation stopped mode • I C (Inter IC) bus mode (multimasters supported) (1) Operation stopped mode In this mode, serial transfers are not performed, thus enabling a reduction in power consumption. (2) I C bus mode (multimaster support) This mode is used for 8-bit data transfers with several devices via two lines: a serial clock pin (SCL0n) and a...
Page 572: Configuration
CHAPTER 17 I C BUS 17.3 Configuration The block diagram of the I C0n is shown below. Figure 17-4. Block Diagram of I Internal bus IIC status register n (IICSn) MSTSn ALDn EXCn COIn TRCn ACKDn STDn SPDn IIC control register n (IICCn) IICEn LRELn WRELn SPIEn WTIMn ACKEn STTn SPTn...
Page 573 CHAPTER 17 I C BUS A serial bus configuration example is shown below. Figure 17-5. Serial Bus Configuration Example Using I C Bus Master CPU1 Master CPU2 Serial data bus Slave CPU2 Slave CPU1 Serial clock Address 1 Address 2 Slave CPU3 Address 3 Slave IC...
Page 574 CHAPTER 17 I C BUS C0n includes the following hardware (n = 0 to 2). Table 17-1. Configuration of I Item Configuration Registers IIC shift register n (IICn) Slave address register n (SVAn) Control registers IIC control register n (IICCn) IIC status register n (IICSn) IIC flag register n (IICFn) IIC clock select register n (IICCLn)
Page 575 CHAPTER 17 I C BUS (7) Interrupt request signal generator This circuit controls the generation of interrupt request signals (INTIICn). An I C interrupt is generated following either of two triggers. • Falling edge of eighth or ninth clock of the serial clock (set by IICCn.WTIMn bit) •...
Page 576: Registers
CHAPTER 17 I C BUS 17.4 Registers C00 to I C02 are controlled by the following registers. • IIC control registers 0 to 2 (IICC0 to IICC2) • IIC status registers 0 to 2 (IICS0 to IICS2) • IIC flag registers 0 to 2 (IICF0 to IICF2) •...
Page 577 CHAPTER 17 I C BUS (1/4) After reset: 00H Address: IICC0 FFFFFD82H, IICC1 FFFFFD92H, IICC2 FFFFFDA2H <7> <6> <5> <4> <3> <2> <1> <0> IICCn IICEn LRELn WRELn SPIEn WTIMn ACKEn STTn SPTn (n = 0 to 2) IICEn Specification of I Cn operation enable/disable Note 1 Operation stopped.
Page 578 CHAPTER 17 I C BUS (2/4) Note SPIEn Enable/disable generation of interrupt request when stop condition is detected Disabled Enabled Condition for clearing (SPIEn bit = 0) Condition for setting (SPIEn bit = 1) • Cleared by instruction • Set by instruction •...
Page 579 CHAPTER 17 I C BUS (3/4) STTn Start condition trigger Start condition is not generated. When bus is released (in STOP mode): A start condition is generated (for starting as master). The SDA0n line is changed from high level to low level while the SCL0n line is high level and then the start condition is generated.
Page 580 CHAPTER 17 I C BUS (4/4) SPTn Stop condition trigger Stop condition is not generated. Stop condition is generated (termination of master device's transfer). After the SDA0n line goes to low level, either set the SCL0n line to high level or wait until the SCL0n pin goes to high level.
Page 581 CHAPTER 17 I C BUS (2) IIC status registers 0 to 2 (IICS0 to IICS2) The IICSn register indicates the status of the I C0n (n = 0 to 2). This register is read-only, in 8-bit or 1-bit units. However, the IICSn register can only be read when the IICCn.STTn bit is 1 or during the wait period.
Page 582 CHAPTER 17 I C BUS (2/3) COIn Matching address detection Addresses do not match. Addresses match. Condition for clearing (COIn bit = 0) Condition for setting (COIn bit = 1) • When a start condition is detected • When the received address matches the local •...
Page 583 CHAPTER 17 I C BUS (3/3) STDn Start condition detection Start condition was not detected. Start condition was detected. This indicates that the address transfer period is in effect Condition for clearing (STDn bit = 0) Condition for setting (STDn bit = 1) •...
Page 584 CHAPTER 17 I C BUS (3) IIC flag registers 0 to 2 (IICF0 to IICF2) The IICFn register sets the I C0n operation mode and indicates the I C bus status. This register can be read or written in 8-bit or 1-bit units. However, the STCFn and IICBSYn bits are read-only. IICRSVn enables/disables the communication reservation function (see 17.14 Communication Reservation).
Page 585 CHAPTER 17 I C BUS Note After reset: 00H Address: IICF0 FFFFFD8AH, IICF1 FFFFFD9AH, IICF2 FFFFFDAAH <7> <6> <1> <0> IICFn STCFn IICBSYn STCENn IICRSVn (n = 0 to 2) STCFn STTn bit clear Start condition issued Start condition cannot be issued, STTn bit cleared Condition for clearing (STCFn bit = 0) Condition for setting (STCFn bit = 1) •...
Page 586 CHAPTER 17 I C BUS (4) IIC clock select registers 0 to 2 (IICCL0 to IICCL2) The IICCLn register sets the transfer clock for the I C0n. This register can be read or written in 8-bit or 1-bit units. However, the CLDn and DADn bits are read-only. Set the IICCLn register when the IICCn.IICEn bit = 0.
Page 587 CHAPTER 17 I C BUS (5) IIC function expansion registers 0 to 2 (IICX0 to IICX2) The IICXn register sets I C0n function expansion (valid only in the high-speed mode). This register can be read or written in 8-bit or 1-bit units. Setting of the CLXn bit is performed in combination with the SMCn, CLn1, and CLn0 bits of the IICCLn register and the OCKSTHm, OCKSm1, and OCKSm0 bits of the OCKSm register (see 17.4 (6) I C0n transfer clock...
Page 588 CHAPTER 17 I C BUS Table 17-2. Clock Settings (1/2) IICX0 IICCL0 Selection Clock Transfer Settable Main Clock Operating Clock Frequency (f ) Range Mode Bit 0 Bit 3 Bit 1 Bit 0 CLX0 SMC0 CL01 CL00 2.00 MHz ≤ f ≤...
Page 589 CHAPTER 17 I C BUS Table 17-2. Clock Settings (2/2) IICXm IICCLm Selection Clock Transfer Settable Main Clock Operating Clock Frequency (f ) Range Mode Bit 0 Bit 3 Bit 1 Bit 0 CLXm SMCm CLm1 CLm0 2.00 MHz ≤ f ≤...
Page 590 CHAPTER 17 I C BUS (7) IIC division clock select registers 0, 1 (OCKS0, OCKS1) The OCKSm register controls the I C0n division clock (n = 0 to 2, m = 0, 1). This register controls the I C00 division clock via the OCKS0 register and the I C01 and I C02 division clocks via the OCKS1 register.
Page 591 CHAPTER 17 I C BUS (9) Slave address registers 0 to 2 (SVA0 to SVA2) The SVAn register holds the I C bus's slave addresses (n = 0 to 2). This register can be read or written in 8-bit units, but bit 0 should be fixed to 0. However, rewriting this register is prohibited when the IICSn.STDn bit = 1 (start condition detection).
Page 592: I C Bus Mode Functions
CHAPTER 17 I C BUS 17.5 I C Bus Mode Functions 17.5.1 Pin configuration The serial clock pin (SCL0n) and serial data bus pin (SDA0n) are configured as follows (n = 0 to 2). SCL0n ....This pin is used for serial clock input and output. This pin is an N-ch open-drain output for both master and slave devices.
Page 593: I C Bus Definitions And Control Methods
= 1). When a start condition is detected, the IICSn.STDn bit is set (1) (n = 0 to 2). Caution When the IICCn.IICEn bit of the V850ES/JJ3 is set to 1 while communications with other devices are in progress, the start condition may be detected depending on the status of the communication line.
Page 594: Addresses
CHAPTER 17 I C BUS 17.6.2 Addresses The 7 bits of data that follow the start condition are defined as an address. An address is a 7-bit data segment that is output in order to select one of the slave devices that are connected to the master device via the bus lines.
Page 595: Transfer Direction Specification
CHAPTER 17 I C BUS 17.6.3 Transfer direction specification In addition to the 7-bit address data, the master device sends 1 bit that specifies the transfer direction. When this transfer direction specification bit has a value of 0, it indicates that the master device is transmitting data to a slave device.
Page 596: Ack
CHAPTER 17 I C BUS 17.6.4 ACK ACK is used to confirm the serial data status of the transmitting and receiving devices. The receiving device returns ACK for every 8 bits of data it receives. The transmitting device normally receives ACK after transmitting 8 bits of data. When ACK is returned from the receiving device, the reception is judged as normal and processing continues.
Page 597: Stop Condition
CHAPTER 17 I C BUS 17.6.5 Stop condition When the SCL0n pin is high level, changing the SDA0n pin from low level to high level generates a stop condition (n = 0 to 2). A stop condition is generated when serial transfer from the master device to the slave device has been completed. When used as the slave device, the start condition can be detected.
Page 598: Wait State
CHAPTER 17 I C BUS 17.6.6 Wait state A wait state is used to notify the communication partner that a device (master or slave) is preparing to transmit or receive data (i.e., is in a wait state). Setting the SCL0n pin to low level notifies the communication partner of the wait state. When the wait state has been canceled for both the master and slave devices, the next data transfer can begin (n = 0 to 2).
Page 599 CHAPTER 17 I C BUS Figure 17-13. Wait State (2/2) (b) When master and slave devices both have a nine-clock wait (master: transmission, slave: reception, and ACKEn bit = 1) Master and slave both wait Master after output of ninth clock. IICn data write (cancel wait state) IICn SCL0n...
Page 600: Wait State Cancellation Method
CHAPTER 17 I C BUS 17.6.7 Wait state cancellation method In the case of I C0n, wait state can be canceled normally in the following ways (n = 0 to 2). • By writing data to the IICn register • By setting the IICCn.WRELn bit to 1 (wait state cancellation) •...
Page 601: I C Interrupt Request Signals (Intiicn)
CHAPTER 17 I C BUS 17.7 I C Interrupt Request Signals (INTIICn) The following shows the value of the IICSn register at the INTIICn interrupt request signal generation timing and at the INTIICn signal timing (n = 0 to 2). 17.7.1 Master device operation (1) Start ~ Address ~ Data ~ Data ~ Stop (normal transmission/reception) <1>...
Page 602 CHAPTER 17 I C BUS (2) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (restart) <1> When WTIMn bit = 0 STTn bit = 1 SPTn bit = 1 ↓ ↓ AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 Δ7...
Page 603 CHAPTER 17 I C BUS (3) Start ~ Code ~ Data ~ Data ~ Stop (extension code transmission) <1> When WTIMn bit = 0 SPTn bit = 1 ↓ AD6 to AD0 D7 to D0 D7 to D0 Δ5 1: IICSn register = 1010X110B 2: IICSn register = 1010X000B 3: IICSn register = 1010X000B (WTIMn bit = 1) 4: IICSn register = 1010XX00B...
Page 604: Slave Device Operation (When Receiving Slave Address Data (Address Match))
CHAPTER 17 I C BUS 17.7.2 Slave device operation (when receiving slave address data (address match)) (1) Start ~ Address ~ Data ~ Data ~ Stop <1> When IICCn.WTIMn bit = 0 AD6 to AD0 D7 to D0 D7 to D0 Δ4 1: IICSn register = 0001X110B 2: IICSn register = 0001X000B...
Page 605 CHAPTER 17 I C BUS (2) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIMn bit = 0 (after restart, address match) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 Δ5 1: IICSn register = 0001X110B 2: IICSn register = 0001X000B...
Page 606 CHAPTER 17 I C BUS (3) Start ~ Address ~ Data ~ Start ~ Code ~ Data ~ Stop <1> When WTIMn bit = 0 (after restart, extension code reception) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 Δ5 1: IICSn register = 0001X110B 2: IICSn register = 0001X000B...
Page 607 CHAPTER 17 I C BUS (4) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIMn bit = 0 (after restart, address mismatch (= not extension code)) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 Δ4 1: IICSn register = 0001X110B...
Page 608: Slave Device Operation (When Receiving Extension Code)
CHAPTER 17 I C BUS 17.7.3 Slave device operation (when receiving extension code) (1) Start ~ Code ~ Data ~ Data ~ Stop <1> When IICCn.WTIMn bit = 0 AD6 to AD0 D7 to D0 D7 to D0 Δ4 1: IICSn register = 0010X010B 2: IICSn register = 0010X000B 3: IICSn register = 0010X000B Δ...
Page 609 CHAPTER 17 I C BUS (2) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIMn bit = 0 (after restart, address match) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 Δ5 1: IICSn register = 0010X010B 2: IICSn register = 0010X000B...
Page 610 CHAPTER 17 I C BUS (3) Start ~ Code ~ Data ~ Start ~ Code ~ Data ~ Stop <1> When WTIMn bit = 0 (after restart, extension code reception) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 Δ5 1: IICSn register = 0010X010B 2: IICSn register = 0010X000B...
Page 611 CHAPTER 17 I C BUS (4) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop <1> When WTIMn bit = 0 (after restart, address mismatch (= not extension code)) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 Δ4 1: IICSn register = 0010X010B...
Page 612: Operation Without Communication
CHAPTER 17 I C BUS 17.7.4 Operation without communication (1) Start ~ Code ~ Data ~ Data ~ Stop AD6 to AD0 D7 to D0 D7 to D0 Δ1 Δ 1: IICSn register = 00000001B Remarks 1. Δ: Generated only when SPIEn bit = 1 2.
Page 613 CHAPTER 17 I C BUS (2) When arbitration loss occurs during transmission of extension code <1> When WTIMn bit = 0 AD6 to AD0 D7 to D0 D7 to D0 Δ4 1: IICSn register = 0110X010B (Example: When ALDn bit is read during interrupt servicing) 2: IICSn register = 0010X000B 3: IICSn register = 0010X000B Δ...
Page 614: Operation When Arbitration Loss Occurs (No Communication After Arbitration Loss)
CHAPTER 17 I C BUS 17.7.6 Operation when arbitration loss occurs (no communication after arbitration loss) (1) When arbitration loss occurs during transmission of slave address data AD6 to AD0 D7 to D0 D7 to D0 Δ2 1: IICSn register = 01000110B (Example: When IICSn.ALDn bit is read during interrupt servicing) Δ...
Page 615 CHAPTER 17 I C BUS (3) When arbitration loss occurs during data transfer <1> When IICCn.WTIMn bit = 0 AD6 to AD0 D7 to D0 D7 to D0 Δ3 1: IICSn register = 10001110B 2: IICSn register = 01000000B (Example: When ALDn bit is read during interrupt servicing) Δ...
Page 616 CHAPTER 17 I C BUS (4) When arbitration loss occurs due to restart condition during data transfer <1> Not extension code (Example: Address mismatch) AD6 to AD0 D7 to Dn AD6 to AD0 D7 to D0 Δ3 1: IICSn register = 1000X110B 2: IICSn register = 01000110B (Example: When ALDn bit is read during interrupt servicing) Δ...
Page 617 CHAPTER 17 I C BUS (5) When arbitration loss occurs due to stop condition during data transfer AD6 to AD0 D7 to Dn Δ2 1: IICSn register = 1000X110B Δ 2: IICSn register = 01000001B Remarks 1. : Always generated Δ: Generated only when SPIEn bit = 1 X: don't care 2.
Page 618 CHAPTER 17 I C BUS (6) When arbitration loss occurs due to low level of SDA0n pin when attempting to generate a restart condition <1> When WTIMn bit = 0 IICCn.STTn bit = 1 ↓ AD6 to AD0 D7 to D0 D7 to D0 D7 to D0 Δ5...
Page 619 CHAPTER 17 I C BUS (7) When arbitration loss occurs due to a stop condition when attempting to generate a restart condition <1> When WTIMn bit = 0 STTn bit = 1 ↓ AD6 to AD0 D7 to D0 Δ4 1: IICSn register = 1000X110B 2: IICSn register = 1000X000B (WTIMn bit = 1) 3: IICSn register = 1000XX00B...
Page 620 CHAPTER 17 I C BUS (8) When arbitration loss occurs due to low level of SDA0n pin when attempting to generate a stop condition <1> When WTIMn bit = 0 IICCn.SPTn bit = 1 ↓ AD6 to AD0 D7 to D0 D7 to D0 D7 to D0 Δ5...
Page 621: Interrupt Request Signal (Intiicn) Generation Timing And Wait Control
CHAPTER 17 I C BUS 17.8 Interrupt Request Signal (INTIICn) Generation Timing and Wait Control The setting of the IICCn.WTIMn bit determines the timing by which the INTIICn register is generated and the corresponding wait control, as shown below (n = 0 to 2). Table 17-3.
Page 622 CHAPTER 17 I C BUS (4) Wait state cancellation method The four wait state cancellation methods are as follows. • By setting the IICCn.WRELn bit to 1 • By writing to the IICn register • By start condition setting (IICCn.STTn bit = 1) Note •...
Page 623: Address Match Detection Method
CHAPTER 17 I C BUS 17.9 Address Match Detection Method In I C bus mode, the master device can select a particular slave device by transmitting the corresponding slave address. Address match detection is performed automatically by hardware. The INTIICn signal occurs when a local address has been set to the SVAn register and when the address set to the SVAn register matches the slave address sent by the master device, or when an extension code has been received (n = 0 to 2).
Page 624: Arbitration
CHAPTER 17 I C BUS 17.12 Arbitration When several master devices simultaneously generate a start condition (when the IICCn.STTn bit is set to 1 before the IICSn.STDn bit is set to 1), communication between the master devices is performed while the number of clocks is adjusted until the data differs.
Page 625: Wakeup Function
CHAPTER 17 I C BUS Table 17-5. Status During Arbitration and Interrupt Request Signal Generation Timing Status During Arbitration Interrupt Request Generation Timing Note 1 Transmitting address transmission At falling edge of eighth or ninth clock following byte transfer Read/write data after address transmission Transmitting extension code Read/write data after extension code transmission Transmitting data...
Page 626: Communication Reservation
CHAPTER 17 I C BUS 17.14 Communication Reservation 17.14.1 When communication reservation function is enabled (IICFn.IICRSVn bit = 0) To start master device communications when not currently using the bus, a communication reservation can be made to enable transmission of a start condition when the bus is released. There are two modes in which the bus is not used.
Page 627 CHAPTER 17 I C BUS Table 17-6. Wait Periods Clock Selection CLXn SMCn CLn1 CLn0 Wait Period (when OCKSm = 18H set) 26 clocks /2 (when OCKSm = 10H set) 52 clocks /3 (when OCKSm = 11H set) 78 clocks /4 (when OCKSm = 12H set) 104 clocks /5 (when OCKSm = 13H set)
Page 628 CHAPTER 17 I C BUS Figure 17-15. Communication Reservation Timing STTn Write to Program processing IICn Set SPDn Communication Hardware processing reservation and INTIICn STDn SCL0n SDA0n Generated by master with bus access Remark n = 0 to 2 STTn: Bit of IICCn register STDn: Bit of IICSn register...
Page 629 CHAPTER 17 I C BUS The communication reservation flowchart is illustrated below. Figure 17-17. Communication Reservation Flowchart Sets STTn bit (communication reservation). SET1 STTn Define communication Defines that communication reservation is in effect reservation (defines and sets user flag to any part of RAM). Secures wait period set by software (see Table 17-6).
Page 630: When Communication Reservation Function Is Disabled (Iicfn.iicrsvn Bit = 1)
CHAPTER 17 I C BUS 17.14.2 When communication reservation function is disabled (IICFn.IICRSVn bit = 1) When the IICCn.STTn bit is set when the bus is not used in a communication during bus communication, this request is rejected and a start condition is not generated. There are two modes in which the bus is not used. •...
Page 631: Cautions
(3) When the IICCn.IICEn bit of the V850ES/JJ3 is set to 1 while communications among other devices are in progress, the start condition may be detected depending on the status of the communication line. Be sure to set the IICCn.IICEn bit to 1 when the SCL0n and SDA0n lines are high level.
Page 632: Communication Operations
This flowchart is broadly divided into the initial settings, communication waiting, and communication processing. The processing when the V850ES/JJ3 loses in arbitration and is specified as the slave is omitted here, and only the processing as the master is shown.
Page 633: Master Operation In Single Master System
CHAPTER 17 I C BUS 17.16.1 Master operation in single master system Figure 17-18. Master Operation in Single Master System START Note Initialize I C bus Refer to Table 4-19 Settings When Port Pins Are Used for Alternate Functions Set ports to set the I C mode before this function is used.
Page 634: Master Operation In Multimaster System
CHAPTER 17 I C BUS 17.16.2 Master operation in multimaster system Figure 17-19. Master Operation in Multimaster System (1/3) START Refer to Table 4-19 Settings When Port Pins Are Used for Alternate Functions Set ports to set the I C mode before this function is used. IICXn ←...
Page 635 CHAPTER 17 I C BUS Figure 17-19. Master Operation in Multimaster System (2/3) Communication reservation enabled Communication start preparation STTn = 1 (start condition generation) Securing wait time by software Wait (refer to Table 17-6) MSTSn = 1? INTIICn interrupt occurred? Waiting for bus release (communication reserved) EXCn = 1 or COIn =1?
Page 636 INTIICn interrupt occurrence to confirm the arbitration result. 3. When using the V850ES/JJ3 as the slave in the multimaster system, confirm the status using the IICSn and IICFn registers for each INTIICn interrupt occurrence to determine the next processing.
Page 637: Slave Operation
CHAPTER 17 I C BUS 17.16.3 Slave operation The following shows the processing procedure of the slave operation. Basically, the operation of the slave device is event-driven. Therefore, processing by an INTIICn interrupt (processing requiring a significant change of the operation status, such as stop condition detection during communication) is necessary.
Page 638 CHAPTER 17 I C BUS For reception, receive the required number of data and do not return ACK for the next data immediately after transfer is complete. After that, the master device generates the stop condition or restart condition. This causes exit from communications.
Page 639 CHAPTER 17 I C BUS The following shows an example of the processing of the slave device by an INTIICn interrupt (it is assumed that no extension codes are used here). During an INTIICn interrupt, the status is confirmed and the following steps are executed.
Page 640: Timing Of Data Communication
CHAPTER 17 I C BUS 17.17 Timing of Data Communication When using I C bus mode, the master device outputs an address via the serial bus to select one of several slave devices as its communication partner. After outputting the slave address, the master device transmits the IICSn.TRCn bit, which specifies the data transfer direction, and then starts serial communication with the slave device.
Page 641 CHAPTER 17 I C BUS Figure 17-23. Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (1/3) (a) Start condition ~ address Processing by master device ← ← IICn IICn address IICn data ACKDn STDn SPDn...
Page 642 CHAPTER 17 I C BUS Figure 17-23. Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (2/3) (b) Data Processing by master device ← ← IICn IICn data IICn data ACKDn STDn SPDn WTIMn ACKEn MSTSn...
Page 643 CHAPTER 17 I C BUS Figure 17-23. Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (3/3) (c) Stop condition Processing by master device ← ← IICn IICn data IICn address ACKDn STDn SPDn WTIMn ACKEn...
Page 644 CHAPTER 17 I C BUS Figure 17-24. Example of Slave to Master Communication (When 8-Clock Wait for Master and 9-Clock Wait for Slave Are Selected) (1/3) (a) Start condition ~ address Processing by master device ← ← IICn IICn address IICn FFH Note ACKDn...
Page 645 CHAPTER 17 I C BUS Figure 17-24. Example of Slave to Master Communication (When 8-Clock Wait for Master and 9-Clock Wait for Slave Are Selected) (2/3) (b) Data Processing by master device ← ← IICn IICn FFH Note IICn FFH Note ACKDn STDn SPDn...
Page 646 CHAPTER 17 I C BUS Figure 17-24. Example of Slave to Master Communication (When 8-Clock Wait for Master and 9-Clock Wait for Slave Are Selected) (3/3) (c) Stop condition Processing by master device ← IICn address ← IICn IICn FFH Note ACKDn STDn SPDn...
Page 647: Chapter 18 Dma Function (Dma Controller)
CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) The V850ES/JJ3 includes a direct memory access (DMA) controller (DMAC) that executes and controls DMA transfer. The DMAC controls data transfer between memory and I/O, between memories, or between I/Os based on DMA requests issued by the on-chip peripheral I/O (serial interface, timer/counter, and A/D converter), interrupts from external input pins, or software triggers (memory refers to internal RAM or external memory).
Page 648: Configuration
DMA channel control register n (DCHCn) DMA addressing control register n (DADCn) DMA trigger factor Channel register n (DTFRn) control DMAC Bus interface External bus V850ES/JJ3 External External External I/O Remark n = 0 to 3 User’s Manual U18376EJ3V0UD...
Page 649: Registers
CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) 18.3 Registers (1) DMA source address registers 0 to 3 (DSA0 to DSA3) The DSA0 to DSA3 registers set the DMA source addresses (26 bits each) for DMA channel n (n = 0 to 3). These registers are divided into two 16-bit registers, DSAnH and DSAnL.
Page 650 CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) (2) DMA destination address registers 0 to 3 (DDA0 to DDA3) The DDA0 to DDA3 registers set the DMA destination address (26 bits each) for DMA channel n (n = 0 to 3). These registers are divided into two 16-bit registers, DDAnH and DDAnL. These registers can be read or written in 16-bit units.
Page 651 CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) (3) DMA transfer count registers 0 to 3 (DBC0 to DBC3) The DBC0 to DBC3 registers are 16-bit registers that set the byte transfer count for DMA channel n (n = 0 to 3). These registers hold the remaining transfer count during DMA transfer.
Page 652 CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) (4) DMA addressing control registers 0 to 3 (DADC0 to DADC3) The DADC0 to DADC3 registers are 16-bit registers that control the DMA transfer mode for DMA channel n (n = 0 to 3). These registers can be read or written in 16-bit units.
Page 653 CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) (5) DMA channel control registers 0 to 3 (DCHC0 to DCHC3) The DCHC0 to DCHC3 registers are 8-bit registers that control the DMA transfer operating mode for DMA channel n. These registers can be read or written in 8-bit or 1-bit units. (However, bit 7 is read-only and bits 1 and 2 are write-only.
Page 654 CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) (6) DMA trigger factor registers 0 to 3 (DTFR0 to DTFR3) The DTFR0 to DTFR3 registers are 8-bit registers that control the DMA transfer start trigger via interrupt request signals from on-chip peripheral I/O. The interrupt request signals set by these registers serve as DMA transfer start factors.
Page 655 CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) Table 18-1. DMA Start Factors (1/2) IFCn5 IFCn4 IFCn3 IFCn2 IFCn1 IFCn0 Interrupt Source DMA request by interrupt disabled INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTP6 INTP7 INTTQ0OV INTTQ0CC0 INTTQ0CC1 INTTQ0CC2 INTTQ0CC3 INTTP0OV INTTP0CC0 INTTP0CC1 INTTP1OV INTTP1CC0...
Page 656: Transfer Targets
CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) Table 18-1. DMA Start Factors (2/2) IFCn5 IFCn4 IFCn3 IFCn2 IFCn1 IFCn0 Interrupt Source INTUA2T INTAD INTKR INTP8 INTTP6CC0 INTTP6CC1 INTTP7CC0 INTTP7CC1 INTTP8CC0 INTTP8CC1 INTCB5R INTCB5T INTUA3R INTUA3T Other than above Setting prohibited Remark n = 0 to 3 18.4 Transfer Targets Table 18-2 shows the relationship between the transfer targets (√: Transfer enabled, ×: Transfer disabled).
Page 657: Transfer Modes
CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) 18.5 Transfer Modes Single transfer is supported as the transfer mode. In single transfer mode, the bus is released at each byte/halfword transfer. If there is a subsequent DMA transfer request, transfer is performed again once. This operation continues until a terminal count occurs. When the DMAC has released the bus, if another higher priority DMA transfer request is issued, the higher priority DMA request always takes precedence.
Page 658: Dma Channel Priorities
CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) 18.7 DMA Channel Priorities The DMA channel priorities are fixed as follows. DMA channel 0 > DMA channel 1 > DMA channel 2 > DMA channel 3 The priorities are checked for every transfer cycle. 18.8 Time Related to DMA Transfer The time required to respond to a DMA request, and the minimum number of clocks required for DMA transfer are shown below.
Page 659: Dma Transfer Start Factors
CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) 18.9 DMA Transfer Start Factors There are two types of DMA transfer start factors, as shown below. (1) Request by software If the STGn bit is set to 1 while the DCHCn.TCn bit = 1 and Enn bit = 1 (DMA transfer enabled), DMA transfer is started.
Page 660: Dma Abort Factors
0 and TCn bit is set to 1, a DMA transfer end interrupt request signal (INTDMAn) is generated for the interrupt controller (INTC) (n = 0 to 3). The V850ES/JJ3 does not output a terminal count signal to an external device. Therefore, confirm completion of DMA transfer by using the DMA transfer end interrupt or polling the TCn bit.
Page 661 Figure 18-1. Priority of DMA (1) System clock DMA0 transfer request DMA1 transfer request DMA2 transfer request DF0 bit DF1 bit DF2 bit Preparation Preparation Preparation Read Write Read Write Read DMA transfer processing for transfer for transfer processing for transfer Idle Idle DMA2...
Page 662 Figure 18-2. Priority of DMA (2) System clock DMA0 transfer request DMA1 transfer request DMA2 transfer request DF0 bit DF1 bit DF2 bit Preparation Preparation Preparation Read Write Read Write DMA transfer Read processing processing for transfer for transfer for transfer Idle Idle DMA0...
Page 663 CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) Figure 18-3. Period in Which DMA Transfer Request Is Ignored (1) System clock DMAn transfer Note 1 request DFn bit Note 2 Note 2 Note 2 Mode of processing CPU processing DMA0 processing CPU processing Preparation Read cycle Write cycle...
Page 664 Figure 18-4. Period in Which DMA Transfer Request Is Ignored (2) System clock DMA0 transfer request DMA1 transfer request DMA2 transfer request DF0 bit DF1 bit DF2 bit Preparation Preparation Preparation DMA transfer Read Write Read Write Read processing processing for transfer for transfer for transfer...
Page 665: Cautions
CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) 18.13 Cautions (1) Caution for VSWC register When using the DMAC, be sure to set an appropriate value, in accordance with the operating frequency, to the VSWC register. When the default value (77H) of the VSWC register is used, or if an inappropriate value is set to the VSWC register, the operation is not correctly performed (for details of the VSWC register, see 3.4.8 (1) (a) System wait control register (VSWC)).
Page 666 CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) (4) DMA transfer initialization procedure (setting DCHCn.INITn bit to 1) Even if the INITn bit is set to 1 when the channel executing DMA transfer is to be initialized, the channel may not be initialized. To accurately initialize the channel, execute either of the following two procedures. (a) Temporarily stop transfer of all DMA channels <R>...
Page 667 CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) (b) Repeatedly execute setting INITn bit until transfer is forcibly terminated correctly <1> Suppress a request from the DMA request source of the channel to be forcibly terminated (stop operation of the on-chip peripheral I/O). <2>...
Page 668 CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) (8) Bus arbitration for CPU <R> Because the DMA controller has a higher priority bus mastership than the CPU, a CPU access that takes place during DMA transfer is held pending until the DMA transfer cycle is completed and the bus is released to the CPU.
Page 669 CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) (12) Read values of DSAn and DDAn registers Values in the middle of updating may be read from the DSAn and DDAn registers during DMA transfer (n = 0 to 3). For example, if the DSAnH register and then the DSAnL register are read when the DMA transfer source address (DSAn register) is 0000FFFFH and the count direction is incremental (DADCn.SAD1 and DADCn.SAD0 bits = 00), the value of the DSAn register differs as follows, depending on whether DMA transfer is executed immediately after the DSAnH register is read.
Page 670: Chapter 19 Interrupt/Exception Processing Function
CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION The V850ES/JJ3 is provided with a dedicated interrupt controller (INTC) for interrupt servicing and can process a total of 71 interrupt requests. An interrupt is an event that occurs independently of program execution, and an exception is an event whose occurrence is dependent on program execution.
Page 671 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 19-1. Interrupt Source List (1/3) Type Classification Default Name Trigger Generating Exception Handler Restored Interrupt Priority Unit Code Address Control Register − − Reset Interrupt RESET RESET pin input RESET 0000H 00000000H Undefined Reset by internal source −...
Page 672 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 19-1. Interrupt Source List (2/3) Type Classification Default Name Trigger Generating Exception Handler Restored Interrupt Priority Unit Code Address Control Register Maskable Interrupt INTTP4OV TMP4 overflow TMP4 0220H 00000220H nextPC TP4OVIC INTTP4CC0 TMP4 capture 0/compare 0 match TMP4 0230H 00000230H nextPC...
Page 673 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 19-1. Interrupt Source List (3/3) Type Classification Default Name Trigger Generating Exception Handler Restored Interrupt Priority Unit Code Address Control Register Maskable Interrupt INTP8 External interrupt pin input edge 0470H 00000470H nextPC PIC8 detection (INTP8) INTTP6OV TMP6 overflow TMP6...
Page 674: Non-Maskable Interrupts
CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION 19.2 Non-Maskable Interrupts A non-maskable interrupt request signal is acknowledged unconditionally, even when interrupts are in the interrupt disabled (DI) status. An NMI is not subject to priority control and takes precedence over all the other interrupt request signals.
Page 675 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 19-1. Non-Maskable Interrupt Request Signal Acknowledgment Operation (2/2) (b) Non-maskable interrupt request signal generated during non-maskable interrupt servicing Non-maskable Non-maskable interrupt request signal generated during non-maskable interrupt servicing interrupt being INTWDT2 serviced • NMI request generated during NMI servicing •...
Page 676: Operation
CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION 19.2.1 Operation If a non-maskable interrupt request signal is generated, the CPU performs the following processing, and transfers control to the handler routine. <1> Saves the restored PC to FEPC. <2> Saves the current PSW to FEPSW. <3>...
Page 677: Restore
CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION 19.2.2 Restore (1) From NMI pin input Execution is restored from the NMI servicing by the RETI instruction. When the RETI instruction is executed, the CPU performs the following processing, and transfers control to the address of the restored PC.
Page 678: Np Flag
CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION (2) From INTWDT2 signal Restoring from non-maskable interrupt servicing executed by the non-maskable interrupt request (INTWDT2) by using the RETI instruction is disabled. Execute the following software reset processing. Figure 19-4. Software Reset Processing INTWDT2 occurs. FEPC ←...
Page 679: Maskable Interrupts
CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION 19.3 Maskable Interrupts Maskable interrupt request signals can be masked by interrupt control registers. The V850ES/JJ3 has 69 maskable interrupt sources. If two or more maskable interrupt request signals are generated at the same time, they are acknowledged according to the default priority.
Page 680 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 19-5. Maskable Interrupt Servicing INT input INTC acknowledged xxIF = 1 Interrupt requested? xxMK = 0 Is the interrupt mask released? Priority higher than that of interrupt currently being serviced? Priority higher than that of other interrupt request? Highest default priority of interrupt requests...
Page 681: Restore
CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION 19.3.2 Restore Recovery from maskable interrupt servicing is carried out by the RETI instruction. When the RETI instruction is executed, the CPU performs the following processing, and transfers control to the address of the restored PC. <1>...
Page 682: Priorities Of Maskable Interrupts
CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION 19.3.3 Priorities of maskable interrupts The INTC performs multiple interrupt servicing in which an interrupt is acknowledged while another interrupt is being serviced. Multiple interrupts can be controlled by priority levels. There are two types of priority level control: control based on the default priority levels, and control based on the programmable priority levels that are specified by the interrupt priority level specification bit (xxPRn) of the interrupt control register (xxICn).
Page 683 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 19-7. Example of Processing in Which Another Interrupt Request Signal Is Issued While an Interrupt Is Being Serviced (1/2) Main routine Servicing of a Servicing of b Interrupt Interrupt request a request b (level 3) Interrupt request b is acknowledged because the (level 2) priority of b is higher than that of a and interrupts are...
Page 684 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 19-7. Example of Processing in Which Another Interrupt Request Signal Is Issued While an Interrupt Is Being Serviced (2/2) Main routine Servicing of i Servicing of k Interrupt request j Interrupt request i (level 3) (level 2) Interrupt request j is held pending because its Interrupt request k...
Page 685 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION Figure 19-8. Example of Servicing Interrupt Request Signals Simultaneously Generated Main routine Interrupt request a (level 2) Interrupt request b (level 1) Servicing of interrupt request b Interrupt request b and c are Interrupt request c (level 1) acknowledged first according to their priorities.
Page 686: Interrupt Control Register (Xxicn)
CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION 19.3.4 Interrupt control register (xxICn) The xxICn register is assigned to each interrupt request signal (maskable interrupt) and sets the control conditions for each maskable interrupt request. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 47H.
Page 687 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 19-2. Interrupt Control Register (xxICn) (1/2) Address Register <7> <6> FFFFF110H LVIIC LVIIF LVIMK LVIPR2 LVIPR1 LVIPR0 FFFFF112H PIC0 PIF0 PMK0 PPR02 PPR01 PPR00 FFFFF114H PIC1 PIF1 PMK1 PPR12 PPR11 PPR10 FFFFF116H PIC2 PIF2 PMK2 PPR22 PPR21...
Page 688: Interrupt Mask Registers 0 To 4 (Imr0 To Imr4)
CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION Table 19-2. Interrupt Control Register (xxICn) (2/2) Address Register <7> <6> FFFFF162H UA0RIC/ UA0RIF/ UA0RMK/ UA0RPR2/ UA0RPR1/ UA0RPR0/ CB4RIC CB4RIF CB4RMK CB4RPR2 CB4RPR1 CB4RPR0 FFFFF164H UA0TIC/ UA0TIF/ UA0TMK/ UA0TPR2/ UA0TPR1/ UA0TPR0/ CB4TIC CB4TIF CB4TMK CB4TPR2 CB4TPR1 CB4TPR0 FFFFF166H...
Page 689 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION After reset: FFFFH Address: IMR4 FFFFF108H, IMR4L FFFFF108H, IMR4H FFFFF109H Note CB5TMK CB5RMK IMR4 (IMR4H UA3TMK UA3RMK TP8CCMK1 IMR4L TP8CCMK0 TP8OVMK TP7CCMK1 TP7CCMK0 TP7OVMK TP6CCMK1 TP6CCMK0 TP6OVMK After reset: FFFFH Address: IMR3 FFFFF106H, IMR3L FFFFF106H, IMR3H FFFFF107H Note IMR3 (IMR3H PMK8...
Page 690: In-Service Priority Register (Ispr)
CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION 19.3.6 In-service priority register (ISPR) The ISPR register holds the priority level of the maskable interrupt currently acknowledged. When an interrupt request signal is acknowledged, the bit of this register corresponding to the priority level of that interrupt request signal is set to 1 and remains set while the interrupt is serviced.
Page 691: Id Flag
CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION 19.3.7 ID flag This flag controls the maskable interrupt's operating state, and stores control information regarding enabling or disabling of interrupt request signals. An interrupt disable flag (ID) is assigned to the PSW. Reset sets this flag to 00000020H. After reset: 00000020H NP EP...
Page 692: Software Exception
CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION 19.4 Software Exception A software exception is generated when the CPU executes the TRAP instruction, and can always be acknowledged. 19.4.1 Operation If a software exception occurs, the CPU performs the following processing, and transfers control to the handler routine.
Page 693: Restore
CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION 19.4.2 Restore Restoration from software exception processing is carried out by the RETI instruction. By executing the RETI instruction, the CPU carries out the following processing and shifts control to the restored PC's address. <1> Loads the restored PC and PSW from EIPC and EIPSW because the PSW.EP bit is 1. <2>...
Page 694: Ep Flag
CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION 19.4.3 EP flag The EP flag is a status flag used to indicate that exception processing is in progress. It is set when an exception occurs. After reset: 00000020H NP EP ID SAT CY OV Exception processing status Exception processing not in progress.
Page 695: Exception Trap
19.5 Exception Trap An exception trap is an interrupt that is requested when the illegal execution of an instruction takes place. In the V850ES/JJ3, an illegal opcode exception (ILGOP: Illegal Opcode Trap) is considered as an exception trap. 19.5.1 Illegal opcode definition The illegal instruction has an opcode (bits 10 to 5) of 111111B, a sub-opcode (bits 26 to 23) of 0111B to 1111B, and a sub-opcode (bit 16) of 0B.
Page 696 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION (2) Restoration Restoration from an exception trap is carried out by the DBRET instruction. By executing the DBRET instruction, the CPU carries out the following processing and controls the address of the restored PC. <1> Loads the restored PC and PSW from DBPC and DBPSW. <2>...
Page 697: Debug Trap
CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION 19.5.2 Debug trap A debug trap is an exception that is generated when the DBTRAP instruction is executed and is always acknowledged. (1) Operation Upon occurrence of a debug trap, the CPU performs the following processing. <1>...
Page 698 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION (2) Restoration Restoration from a debug trap is executed with the DBRET instruction. With the DBRET instruction, the CPU performs the following steps and transfers control to the address of the restored PC. <1> The restored PC and PSW are read from DBPC and DBPSW. <2>...
Page 699: External Interrupt Request Input Pins (Nmi And Intp0 To Intp8)
CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION 19.6 External Interrupt Request Input Pins (NMI and INTP0 to INTP8) 19.6.1 Noise elimination (1) Eliminating noise on NMI pin The NMI pin has an internal noise elimination circuit that uses analog delay. Therefore, the input level of the NMI pin is not detected as an edge unless it is maintained for a specific time or longer.
Page 700 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION (1) External interrupt falling, rising edge specification register 0 (INTF0, INTR0) The INTF0 and INTR0 registers are 8-bit registers that specify detection of the falling and rising edges of the NMI pin via bit 2 and the external interrupt pins (INTP0 to INTP3) via bits 3 to 6. These registers can be read or written in 8-bit or 1-bit units.
Page 701 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION (2) External interrupt falling, rising edge specification register 3 (INTF3, INTR3) The INTF3 and INTR3 registers are 8-bit registers that specify detection of the falling and rising edges of the external interrupt pin (INTP7). These registers can be read or written in 8-bit or 1-bit units. Reset sets these registers to 00H.
Page 702 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION (3) External interrupt falling, rising edge specification register 8 (INTF8, INTR8) The INTF8 and INTR8 registers are 8-bit registers that specify detection of the falling and rising edges of the external interrupt pin (INTP8). These registers can be read or written in 8-bit or 1-bit units. Reset sets these registers to 00H.
Page 703 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION (4) External interrupt falling, rising edge specification register 9H (INTF9H, INTR9H) The INTF9H and INTR9H registers are 8-bit registers that specify detection of the falling and rising edges of the external interrupt pins (INTP4 to INTP6). These registers can be read or written in 8-bit or 1-bit units.
Page 704 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION (5) Noise elimination control register (NFC) Digital noise elimination can be selected for the INTP3 pin. The noise elimination settings are performed using the NFC register. When digital noise elimination is selected, the sampling clock for digital sampling can be selected from among /64, f /128, f /256, f...
Page 705: Interrupt Acknowledge Time Of Cpu
CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION 19.7 Interrupt Acknowledge Time of CPU Except the following cases, the interrupt acknowledge time of the CPU is 4 clocks minimum. To input interrupt request signals successively, input the next interrupt request signal at least 5 clocks after the preceding interrupt. •...
Page 706: Periods In Which Interrupts Are Not Acknowledged By Cpu
CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION 19.8 Periods in Which Interrupts Are Not Acknowledged by CPU An interrupt is acknowledged by the CPU while an instruction is being executed. However, no interrupt will be acknowledged between an interrupt request non-sample instruction and the next instruction (interrupt is held pending). The interrupt request non-sample instructions are as follows.
Page 707: Chapter 20 Key Interrupt Function
CHAPTER 20 KEY INTERRUPT FUNCTION 20.1 Function A key interrupt request signal (INTKR) can be generated by inputting a falling edge to the eight key input pins (KR0 to KR7) by setting the KRM register. Table 20-1. Assignment of Key Return Detection Pins Flag Pin Description KRM0...
Page 708: Register
CHAPTER 20 KEY INTERRUPT FUNCTION 20.2 Register (1) Key return mode register (KRM) The KRM register controls the KRM0 to KRM7 bits using the KR0 to KR7 signals. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
Page 709: Chapter 21 Standby Function
CHAPTER 21 STANDBY FUNCTION 21.1 Overview The power consumption of the system can be effectively reduced by using the standby modes in combination and selecting the appropriate mode for the application. The available standby modes are listed in Table 21-1. Table 21-1.
Page 710 CHAPTER 21 STANDBY FUNCTION Figure 21-1. Status Transition Reset Internal oscillation clock operation Sub-IDLE mode WDT overflow (fx operates, PLL operates) Oscillation stabilization wait Normal operation mode Subclock operation mode Clock through mode (fx operates, PLL operates) (PLL operates) PLL lockup HALT mode time wait (fx operates, PLL operates)
Page 711: Registers
CHAPTER 21 STANDBY FUNCTION 21.2 Registers (1) Power save control register (PSC) The PSC register is an 8-bit register that controls the standby function. The STP bit of this register is used to specify the STOP mode. This register is a special register that can be written only by the special sequence combinations (see 3.4.7 Special registers).
Page 712 CHAPTER 21 STANDBY FUNCTION (2) Power save mode register (PSMR) The PSMR register is an 8-bit register that controls the operation status in the power save mode and the clock operation. This register can be read or written in 8-bit or 1-bit units. Reset sets this register to 00H.
Page 713 CHAPTER 21 STANDBY FUNCTION (3) Oscillation stabilization time select register (OSTS) The wait time until the oscillation stabilizes after the STOP mode is released or the wait time until the on-chip flash memory stabilizes after the IDLE2 mode is released is controlled by the OSTS register. The OSTS register can be read or written 8-bit units.
Page 714: Halt Mode
CHAPTER 21 STANDBY FUNCTION 21.3 HALT Mode 21.3.1 Setting and operation status The HALT mode is set when a dedicated instruction (HALT) is executed in the normal operation mode. In the HALT mode, the clock oscillator continues operating. Only clock supply to the CPU is stopped; clock supply to the other on-chip peripheral functions continues.
Page 715 CHAPTER 21 STANDBY FUNCTION (2) Releasing HALT mode by reset The same operation as the normal reset operation is performed. Table 21-3. Operating Status in HALT Mode Setting of HALT Mode Operating Status Item When Subclock Is Not Used When Subclock Is Used Main clock oscillator Oscillation enabled −...
Page 716: Idle1 Mode
CHAPTER 21 STANDBY FUNCTION 21.4 IDLE1 Mode 21.4.1 Setting and operation status The IDLE1 mode is set by clearing the PSMR.PSM1 and PSMR.PSM0 bits to 00 and setting the PSC.STP bit to 1 in the normal operation mode. In the IDLE1 mode, the clock oscillator, PLL, and flash memory continue operating but clock supply to the CPU and other on-chip peripheral functions stops.
Page 717 CHAPTER 21 STANDBY FUNCTION Table 21-4. Operation After Releasing IDLE1 Mode by Interrupt Request Signal Release Source Interrupt Enabled (EI) Status Interrupt Disabled (DI) Status Non-maskable interrupt request Execution branches to the handler address. signal Maskable interrupt request signal Execution branches to the handler address The next instruction is executed.
Page 718: Idle2 Mode
CHAPTER 21 STANDBY FUNCTION 21.5 IDLE2 Mode 21.5.1 Setting and operation status The IDLE2 mode is set by setting the PSMR.PSM1 and PSMR.PSM0 bits to 10 and setting the PSC.STP bit to 1 in the normal operation mode. In the IDLE2 mode, the clock oscillator continues operation but clock supply to the CPU, PLL, flash memory, and other on-chip peripheral functions stops.
Page 719 CHAPTER 21 STANDBY FUNCTION Table 21-6. Operation After Releasing IDLE2 Mode by Interrupt Request Signal Release Source Interrupt Enabled (EI) Status Interrupt Disabled (DI) Status Non-maskable interrupt request Execution branches to the handler address after securing the prescribed setup time. signal Maskable interrupt request signal Execution branches to the handler address...
Page 720: Securing Setup Time When Releasing Idle2 Mode
CHAPTER 21 STANDBY FUNCTION 21.5.3 Securing setup time when releasing IDLE2 mode Secure the setup time for the flash memory after releasing the IDLE2 mode because the operation of the blocks other than the main clock oscillator stops after the IDLE2 mode is set. (1) Releasing IDLE2 mode by non-maskable interrupt request signal or unmasked maskable interrupt request signal Secure the specified setup time by setting the OSTS register.
Page 721: Stop Mode
CHAPTER 21 STANDBY FUNCTION 21.6 STOP Mode 21.6.1 Setting and operation status The STOP mode is set by setting the PSMR.PSM1 and PSMR.PSM0 bits to 01 or 11 and setting the PSC.STP bit to 1 in the normal operation mode. In the STOP mode, the subclock oscillator continues operating but the main clock oscillator stops.
Page 722 CHAPTER 21 STANDBY FUNCTION Table 21-8. Operation After Releasing STOP Mode by Interrupt Request Signal Release Source Interrupt Enabled (EI) Status Interrupt Disabled (DI) Status Non-maskable interrupt request Execution branches to the handler address after securing the oscillation stabilization time. signal Maskable interrupt request signal Execution branches to the handler address...
Page 723 CHAPTER 21 STANDBY FUNCTION (2) Releasing STOP mode by reset The same operation as the normal reset operation is performed. Table 21-9. Operating Status in STOP Mode Setting of STOP Mode Operating Status Item When Subclock Is Not Used When Subclock Is Used Main clock oscillator Stops oscillation −...
Page 724: Securing Oscillation Stabilization Time When Releasing Stop Mode
CHAPTER 21 STANDBY FUNCTION 21.6.3 Securing oscillation stabilization time when releasing STOP mode Secure the oscillation stabilization time for the main clock oscillator after releasing the STOP mode because the operation of the main clock oscillator stops after STOP mode is set. (1) Releasing STOP mode by non-maskable interrupt request signal or unmasked maskable interrupt request signal Secure the oscillation stabilization time by setting the OSTS register.
Page 725: Subclock Operation Mode
CHAPTER 21 STANDBY FUNCTION 21.7 Subclock Operation Mode 21.7.1 Setting and operation status The subclock operation mode is set by setting the PCC.CK3 bit to 1 in the normal operation mode. When the subclock operation mode is set, the internal system clock is changed from the main clock to the subclock. Check whether the clock has been switched by using the PCC.CLS bit.
Page 726 CHAPTER 21 STANDBY FUNCTION Table 21-10. Operating Status in Subclock Operation Mode Setting of Subclock Operation Mode Operating Status Item When Main Clock Is Oscillating When Main Clock Is Stopped Subclock oscillator Oscillation enabled Internal oscillator Oscillation enabled Note Operable Stops operation Operable Operable...
Page 727: Sub-Idle Mode
CHAPTER 21 STANDBY FUNCTION 21.8 Sub-IDLE Mode 21.8.1 Setting and operation status The sub-IDLE mode is set by setting the PSMR.PSM1 and PSMR.PSM0 bits to 00 or 10 and setting the PSC.STP bit to 1 in the subclock operation mode. In this mode, the clock oscillator continues operating but clock supply to the CPU, flash memory, and the other on- chip peripheral functions is stopped.
Page 728 CHAPTER 21 STANDBY FUNCTION Table 21-11. Operation After Releasing Sub-IDLE Mode by Interrupt Request Signal Release Source Interrupt Enabled (EI) Status Interrupt Disabled (DI) Status Non-maskable interrupt request Execution branches to the handler address. signal Maskable interrupt request signal Execution branches to the handler address The next instruction is executed.
Page 729: Chapter 22 Reset Functions
CHAPTER 22 RESET FUNCTIONS 22.1 Overview The following reset functions are available. (1) Four kinds of reset sources • External reset input via the RESET pin • Reset via the watchdog timer 2 (WDT2) overflow (WDT2RES) • System reset via the comparison of the low-voltage detector (LVI) supply voltage and detected voltage •...
Page 730: Registers To Check Reset Source
CHAPTER 22 RESET FUNCTIONS 22.2 Registers to Check Reset Source The V850ES/JJ3 has four kinds of reset sources. After a reset has been released, the source of the reset that occurred can be checked with the reset source flag register (RESF).
Page 731: Operation
CHAPTER 22 RESET FUNCTIONS 22.3 Operation 22.3.1 Reset operation via RESET pin When a low level is input to the RESET pin, the system is reset, and each hardware unit is initialized. When the level of the RESET pin is changed from low to high, the reset status is released. Table 22-1.
Page 732 CHAPTER 22 RESET FUNCTIONS Figure 22-2. Timing of Reset Operation by RESET Pin Input Initialized to f /8 operation RESET Analog delay Analog delay Analog delay Analog delay (eliminated as noise) (eliminated as noise) Internal system reset signal Counting of oscillation stabilization time Oscillation stabilization timer overflows Figure 22-3.
Page 733: Reset Operation By Watchdog Timer 2
CHAPTER 22 RESET FUNCTIONS 22.3.2 Reset operation by watchdog timer 2 When watchdog timer 2 is set to the reset operation mode due to overflow, upon watchdog timer 2 overflow (WDT2RES signal generation), a system reset is executed and the hardware is initialized to the initial status. Following watchdog timer 2 overflow, the reset status is entered and lasts the predetermined time (analog delay), and the reset status is then automatically released.
Page 734 CHAPTER 22 RESET FUNCTIONS Figure 22-4. Timing of Reset Operation by WDT2RES Signal Generation Initialized to f /8 operation WDT2RES Analog delay Internal system reset signal Counting of oscillation stabilization time Oscillation stabilization timer overflow User’s Manual U18376EJ3V0UD...
Page 735: Reset Operation By Low-Voltage Detector
CHAPTER 22 RESET FUNCTIONS 22.3.3 Reset operation by low-voltage detector If the supply voltage falls below the voltage detected by the low-voltage detector when LVI operation is enabled, a system reset is executed (when the LVIM.LVIMD bit is set to 1), and the hardware is initialized to the initial status. The reset status lasts from when a supply voltage drop has been detected until the supply voltage rises above the LVI detection voltage.
Page 736: Operation After Reset Release
Figure 22-5. Operation After Reset Release Main clock Internal oscillation clock Counting of oscillation stabilization time Normal operation (f = Main clock) Reset V850ES/JJ3 Operation Operation in progress stops WDT2 Operation stops Operation in progress Clock monitor (1) Emergent operation mode If an anomaly occurs in the main clock before oscillation stabilization time is secured, WDT2 overflows before executing the CPU program.
Page 737: Reset Function Operation Flow
CHAPTER 22 RESET FUNCTIONS 22.3.5 Reset function operation flow Start (reset source occurs) Note 1 Set RESF register → Reset occurs reset release Internal oscillation and main clock oscillation start, WDT2 count up starts (reset mode) Main clock oscillation stabilization time secured? (in normal operation mode)
Page 738: Chapter 23 Clock Monitor
CHAPTER 23 CLOCK MONITOR 23.1 Functions The clock monitor samples the main clock by using the internal oscillation clock and generates a reset request signal when oscillation of the main clock is stopped. Once the operation of the clock monitor has been enabled by an operation enable flag, it cannot be cleared to 0 by any means other than reset.
Page 739: Register
CHAPTER 23 CLOCK MONITOR 23.3 Register The clock monitor is controlled by the clock monitor mode register (CLM). (1) Clock monitor mode register (CLM) The CLM register is a special register. This can be written only in a special combination of sequences (see 3.4.7 Special registers).
Page 740: Operation
CHAPTER 23 CLOCK MONITOR 23.4 Operation This section explains the functions of the clock monitor. The start and stop conditions are as follows. <Start condition> Enabling operation by setting the CLM.CLME bit to 1 <Stop conditions> • While oscillation stabilization time is being counted after STOP mode is released •...
Page 741 CHAPTER 23 CLOCK MONITOR (1) Operation when main clock oscillation is stopped (CLME bit = 1) If oscillation of the main clock is stopped when the CLME bit = 1, an internal reset signal is generated as shown in Figure 23-2. Figure 23-2.
Page 742 CHAPTER 23 CLOCK MONITOR (3) Operation in STOP mode or after STOP mode is released If the STOP mode is set with the CLM.CLME bit = 1, the monitor operation is stopped in the STOP mode and while the oscillation stabilization time is being counted. After the oscillation stabilization time, the monitor operation is automatically started.
Page 743: Chapter 24 Low-Voltage Detector (Lvi)
CHAPTER 24 LOW-VOLTAGE DETECTOR (LVI) 24.1 Functions The low-voltage detector (LVI) has the following functions. • If the interrupt occurrence at low voltage detection is selected, the low-voltage detector continuously compares the supply voltage (V ) and the detected voltage (V ), and generates an internal interrupt signal when the supply voltage drops or rises across the detected voltage.
Page 744: Registers
CHAPTER 24 LOW-VOLTAGE DETECTOR (LVI) 24.3 Registers The low-voltage detector is controlled by the following registers. • Low-voltage detection register (LVIM) • Low-voltage detection level select register (LVIS) • Internal RAM data status register (RAMS) (1) Low-voltage detection register (LVIM) The LVIM register is a special register.
Page 745 CHAPTER 24 LOW-VOLTAGE DETECTOR (LVI) (2) Low-voltage detection level select register (LVIS) The LVIS register is used to select the level of low voltage to be detected. This register can be read or written in 8-bit or 1-bit units. After reset: Note Address: FFFFF891H LVIS LVIS0...
Page 746: Operation
CHAPTER 24 LOW-VOLTAGE DETECTOR (LVI) 24.4 Operation Depending on the setting of the LVIM.VIMD bit, an interrupt signal (INTLVI) or an internal reset signal is generated. How to specify each operation is described below, together with timing charts. 24.4.1 To use for internal reset signal <To start operation>...
Page 747: To Use For Interrupt
CHAPTER 24 LOW-VOLTAGE DETECTOR (LVI) 24.4.2 To use for interrupt <To start operation> <1> Mask the interrupt of LVI. <2> Select the voltage to be detected by using the LVIS.LVIS0 bit. <3> Set the LVIM.LVION bit to 1 (to enable operation). <4>...
Page 748: Ram Retention Voltage Detection Operation
CHAPTER 24 LOW-VOLTAGE DETECTOR (LVI) 24.5 RAM Retention Voltage Detection Operation The supply voltage and detected voltage are compared. When the supply voltage drops below the detected voltage (including on power application), the RAMS.RAMF bit is set to 1. Figure 24-4. Operation Timing of RAM Retention Voltage Detection Function Initialize RAM Initialize RAM <...
Page 749: Emulation Function
CHAPTER 24 LOW-VOLTAGE DETECTOR (LVI) 24.6 Emulation Function When an in-circuit emulator is used, the operation of the RAM retention flag (RAMS.RAMF bit) can be pseudo- controlled and emulated by manipulating the PEMU1 register on the debugger. This register is valid only in the emulation mode. It is invalid in the normal mode. (1) Peripheral emulation register 1 (PEMU1) After reset: 00H Address: FFFFF9FEH...
Page 750: Chapter 25 Crc Function
CHAPTER 25 CRC FUNCTION 25.1 Functions • CRC operation circuit for detection of data block errors • Generation of 16-bit CRC code using a CRC-CCITT (X + 1) generation polynomial for blocks of data of any length in 8-bit units •...
Page 751: Registers
CHAPTER 25 CRC FUNCTION 25.3 Registers (1) CRC input register (CRCIN) The CRCIN register is an 8-bit register for setting data. This register can be read or written in 8-bit units. Reset sets this register to 00H. After reset: 00H Address: FFFFF310H CRCIN (2) CRC data register (CRCD)
Page 752: Operation
CHAPTER 25 CRC FUNCTION 25.4 Operation An example of the CRC operation circuit is shown below. Figure 25-2. CRC Operation Circuit Operation Example (LSB First) (1) Setting of CRCIN = 01H (2) CRCD register read 1189H CRC code is stored The code when 01H is sent LSB first is (1000 0000).
Page 753: Usage Method
CHAPTER 25 CRC FUNCTION 25.5 Usage Method How to use the CRC logic circuit is described below. Figure 25-3. CRC Operation Flow Start Write of 0000H to CRCD register Input data exists? CRCD register read CRCIN register write [Basic usage method] <1>...
Page 754 CHAPTER 25 CRC FUNCTION Communication errors can easily be detected if the CRC code is transmitted/received along with transmit/receive data when transmitting/receiving data consisting of several bytes. The following is an illustration using the transmission of 12345678H (0001 0010 0011 0100 0101 0110 0111 1000B) LSB-first as an example.
Page 755: Chapter 26 Regulator
CHAPTER 26 REGULATOR 26.1 Overview The V850ES/JJ3 includes a regulator to reduce power consumption and noise. This regulator supplies a stepped-down V power supply voltage to the oscillator block and internal logic circuits (except the A/D converter, D/A converter, and output buffers). The regulator output voltage is set to 2.5 V (TYP.).
Page 756: Operation
CHAPTER 26 REGULATOR 26.2 Operation The regulator of this product always operates in any mode (normal operation mode, HALT mode, IDLE1 mode, IDLE2 mode, STOP mode, or during reset). μ Be sure to connect a capacitor (4.7 F (recommended value)) to the REGC pin to stabilize the regulator output. A diagram of the regulator pin connection method is shown below.
Page 757: Chapter 27 Flash Memory
Flash memory versions offer the following advantages for development environments and mass production applications. For altering software after the V850ES/JJ3 is soldered onto the target system. For data adjustment when starting mass production. For differentiating software according to the specification in small scale production of various models.
Page 758: Memory Configuration
CHAPTER 27 FLASH MEMORY 27.2 Memory Configuration The V850ES/JJ3 internal flash memory area is divided into 4 KB blocks and can be programmed/erased in block units. All or some of the blocks can also be erased at once. When the boot swap function is used, the physical memory allocated at the addresses of blocks 0 to 15 is replaced by the physical memory allocated at the addresses of blocks 16 to 31.
Page 759 CHAPTER 27 FLASH MEMORY Figure 27-1. Flash Memory Mapping 000FFFFFH Block 255 (4 KB) 0 0 0 F F 0 0 0 H 000FEFFFH 000C1000H 000C0FFFH Block 192 (4 KB) 000C0000H 000BFFFFH Block 191 (4 KB) Block 191 (4 KB) 000BF000H 000BEFFFH 0 0 0 A 1 0 0 0 H...
Page 760: Functional Outline
CHAPTER 27 FLASH MEMORY 27.3 Functional Outline The internal flash memory of the V850ES/JJ3 can be rewritten by using the rewrite function of the dedicated flash programmer, regardless of whether the V850ES/JJ3 has already been mounted on the target system or not (off- board/on-board programming).
Page 761 CHAPTER 27 FLASH MEMORY <R> Table 27-2. Basic Functions Support ( √ : Supported, ×: Not supported) Function Functional Outline On-Board/Off-Board Self Programming Programming √ √ Blank check The erasure status of the entire memory is checked. √ × Note Chip erasure The contents of the entire memory area are erased all at once.
Page 762 CHAPTER 27 FLASH MEMORY Table 27-4. Security Setting <R> Function Erase, Write, Read Operations When Each Security Is Set Notes on Security Setting (√: Executable, ×: Not Executable, −: Not Supported) On-Board/ Self Programming On-Board/ Self Off-Board Programming Programming Off-Board Programming Chip erase command: ×...
Page 763: Rewriting By Dedicated Flash Programmer
27.4 Rewriting by Dedicated Flash Programmer The flash memory can be rewritten by using a dedicated flash programmer after the V850ES/JJ3 is mounted on the target system (on-board programming). The flash memory can also be rewritten before the device is mounted on the target system (off-board programming) by using a dedicated program adapter (FA series).
Page 764: Communication Mode
CHAPTER 27 FLASH MEMORY 27.4.2 Communication mode Communication between the dedicated flash programmer and the V850ES/JJ3 is performed by serial communication using the UARTA0, CSIB0, or CSIB3 interfaces of the V850ES/JJ3. (1) UARTA0 Transfer rate: 9,600 to 153,600 bps Figure 27-3. Communication with Dedicated Flash Programmer (UARTA0)
Page 765 The dedicated flash programmer outputs the transfer clock, and the V850ES/JJ3 operates as a slave. When the PG-FP4 is used as the dedicated flash programmer, it generates the following signals to the V850ES/JJ3. For details, refer to the PG-FP4 User's Manual (U15260E).
Page 766 CHAPTER 27 FLASH MEMORY Table 27-6. Wiring of Flash Writing Adapter for V850ES/JJ3 (FA-144GJ-UEN-A) (1/2) Flash Programmer (PG-FP4) Pin Name When CSIB0 + HS Is When CSIB0 Is Used When UARTA0 Is Used Connection Pins Used on FA Board Signal...
Page 767 CHAPTER 27 FLASH MEMORY Table 27-6. Wiring of Flash Writing Adapter for V850ES/JJ3 (FA-144GJ-UEN-A) (2/2) Flash Programmer (PG-FP4) Pin Name on When CSIB3 + HS Is Used When CSIB3 Is Used Connection Pins FA Board Signal Pin Function Pin Name...
Page 768 CHAPTER 27 FLASH MEMORY Figure 27-6. Example of Wiring of V850ES/JJ3 Flash Writing Adapter (FA-144GJ-UEN-A) (in CSIB0 + HS Mode) (1/2) Note 2 Note 2 Note 1 V850ES/JJ3 Connect to GND Connect to VDD μ 4.7 F (recommended value) Note 4...
Page 769 CHAPTER 27 FLASH MEMORY Figure 27-6. Example of Wiring of V850ES/JJ3 Flash Writing Adapter (FA-144GJ-UEN-A) (in CSIB0 + HS Mode) (2/2) Notes 1. Wire the FLMD1 pin as shown below, or connect it to GND on board via a pull-down resistor.
Page 770: Flash Memory Control
CHAPTER 27 FLASH MEMORY 27.4.3 Flash memory control The following shows the procedure for manipulating the flash memory. Figure 27-7. Procedure for Manipulating Flash Memory <R> Start Switch to flash memory programming mode Supplies FLMD0 pulse Select communication system Manipulate flash memory End? User’s Manual U18376EJ3V0UD...
Page 771: Selection Of Communication Mode
27.4.4 Selection of communication mode In the V850ES/JJ3, the communication mode is selected by inputting pulses (12 pulses max.) to the FLMD0 pin after switching to the flash memory programming mode. The FLMD0 pulse is generated by the dedicated flash programmer.
Page 772: Communication Commands
The V850ES/JJ3 communicates with the dedicated flash programmer by means of commands. The signals sent from the dedicated flash programmer to the V850ES/JJ3 are called "commands". The response signals sent from the V850ES/JJ3 to the dedicated flash programmer are called "response commands".
Page 773: Pin Connection
FLMD0 pin via port control, etc., before writing to the flash memory. For details, see 27.5.5 (1) FLMD0 pin. Figure 27-10. FLMD0 Pin Connection Example V850ES/JJ3 Dedicated flash programmer connection pin FLMD0 Pull-down resistor (R...
Page 774 (output), a conflict of signals occurs. To avoid the conflict of signals, isolate the connection to the other device or set the other device to the output high-impedance status. Figure 27-12. Conflict of Signals (Serial Interface Input Pin) V850ES/JJ3 Dedicated flash programmer connection pins...
Page 775 V850ES/JJ3 Dedicated flash programmer connection pin Other device Input pin In the flash memory programming mode, if the signal the V850ES/JJ3 outputs affects the other device, isolate the signal on the other device side. V850ES/JJ3 Dedicated flash programmer connection pin...
Page 776 When a reset signal is input from the user system in the flash memory programming mode, the programming operation will not be performed correctly. Therefore, do not input signals other than the reset signals from the dedicated flash programmer. Figure 27-14. Conflict of Signals (RESET Pin) V850ES/JJ3 Dedicated flash programmer connection pin Conflict of signals...
Page 777: Rewriting By Self Programming
27.5.1 Overview The V850ES/JJ3 supports a flash macro service that allows the user program to rewrite the internal flash memory by itself. By using this interface and a self programming library that is used to rewrite the flash memory with a user application program, the flash memory can be rewritten by a user application transferred in advance to the internal RAM or external memory.
Page 778: Features
(1) Secure self programming (boot swap function) The V850ES/JJ3 supports a boot swap function that can exchange the physical memory of blocks 0 to 15 with the physical memory of blocks 16 to 31. By writing the start program to be rewritten to blocks 16 to 31 in advance and then swapping the physical memory, the entire area can be safely rewritten even if a power failure occurs during rewriting because the correct user program always exists in blocks 0 to 15.
Page 779: Standard Self Programming Flow
CHAPTER 27 FLASH MEMORY 27.5.3 Standard self programming flow The entire processing to rewrite the flash memory by flash self programming is illustrated below. Figure 27-17. Standard Self Programming Flow <R> Flash memory manipulation Flash environment initialization processing • Disable accessing flash area •...
Page 780: Flash Functions
CHAPTER 27 FLASH MEMORY 27.5.4 Flash functions Table 27-10. Flash Function List <R> Function Name Outline Support √ FlashInit Self-programming library initialization √ FlashEnv Flash environment start/end √ FlashFLMDCheck FLMD pin check √ FlashStatusCheck Hardware processing execution status check √ FlashBlockErase Block erase √...
Page 781: Internal Resources Used
CHAPTER 27 FLASH MEMORY 27.5.6 Internal resources used The following table lists the internal resources used for self programming. These internal resources can also be used freely for purposes other than self programming. Table 27-11. Internal Resources Used <R> Resource Name Description Note Stack area...
Page 782: Chapter 28 On-Chip Debug Function
The V850ES/JJ3 on-chip debug function can be implemented by the following two methods. • Using the DCU (debug control unit) On-chip debug function is implemented by the on-chip DCU in the V850ES/JJ3, with using the DRST, DCK, DMS, DDI, and DDO pins as the debug interface pins.
Page 783: Debugging With Dcu
Note 3 FLMD0 FLMD0 FLMD1/PDL5 MINICUBE V850ES/JJ3 Notes 1. Example of pin connection when MINICUBE is not connected 2. A pull-down resistor is provided on chip. 3. For flash memory rewriting 28.1.2 Interface signals The interface signals are described below.
Page 784 CHAPTER 28 ON-CHIP DEBUG FUNCTION (2) DCK This is a clock input signal. It supplies a 20 MHz or 10 MHz clock from MINICUBE. In the on-chip debug unit, the DMS and DDI signals are sampled at the rising edge of the DCK signal, and the data DDO is output at its falling edge.
Page 785: Maskable Functions
CHAPTER 28 ON-CHIP DEBUG FUNCTION 28.1.3 Maskable functions Reset, NMI, INTWDT2, WAIT, and HLDRQ signals can be masked. The maskable functions with the debugger (ID850QB) and the corresponding V850ES/JJ3 functions are listed below. Table 28-2. Maskable Functions Maskable Functions with ID850QB...
Page 786 CHAPTER 28 ON-CHIP DEBUG FUNCTION Note After reset: 01H Address: FFFFF9FCH < > OCDM OCDM0 OCDM0 Operation mode Selects normal operation mode (in which a pin that functions alternately as on-chip debug function pin is used as a port/peripheral function pin) and disconnects the on-chip pull-down resistor of the P05/INTP2/DRST pin.
Page 787: Operation
CHAPTER 28 ON-CHIP DEBUG FUNCTION 28.1.5 Operation The on-chip debug function is made invalid under the conditions shown in the table below. When this function is not used, keep the DRST pin low until the OCDM.OCDM0 flag is cleared to 0. OCDM0 Flag DRST Pin Invalid...
Page 788: Debugging Without Using Dcu
TXD/SO (transmit side) of the target connector to RXDA0/SIB0/SIB3 (receive side) of the V850ES/JJ3. 2. The V850ES/JJ3-side pin connected to this pin (FLMD0, FLMD1) can be used as an alternate- function pin other than while the memory is rewritten during a break in debugging, because this pin is in a Hi-Z state.
Page 789: Maskable Functions
Input Reset input pin on the target system 28.2.2 Maskable functions Only reset signals can be masked. The maskable functions with the debugger (ID850QB) and the corresponding V850ES/JJ3 functions are listed below. Table 28-4. Maskable Functions Maskable Functions with ID850QB Corresponding V850ES/JJ3 Functions −...
Page 790: Securement Of User Resources
CHAPTER 28 ON-CHIP DEBUG FUNCTION 28.2.3 Securement of user resources The user must prepare the following to perform communication between MINICUBE2 and the target device and implement each debug function. These items need to be set in the user program or using the compiler options. (1) Securement of memory space The shaded portions in Figure 28-4 are the areas reserved for placing the debug monitor program, so user programs and data cannot be allocated in these spaces.
Page 791 CHAPTER 28 ON-CHIP DEBUG FUNCTION Figure 28-4. Memory Spaces Where Debug Monitor Programs Are Allocated Internal ROM Internal RAM 3FFEFFFH (16 bytes) 3FFEFF0H (2 KB) Note 1 Internal RAM area Note 3 CSI0/UART receive Access-prohibited area Note 2 0000290H interrupt vector (4 bytes) Internal ROM area Security ID area...
Page 792 CHAPTER 28 ON-CHIP DEBUG FUNCTION (3) Reset vector A reset vector includes the jump instruction for the debug monitor program. [How to secure areas] It is not necessary to secure this area intentionally. When downloading a program, however, the debugger rewrites the reset vector in accordance with the following cases.
Page 793 To avoid problems that may occur during the debugger startup, however, it is recommended to secure this area in advance, using the compiler. The following shows examples for securing the area, using the NEC Electronics compiler CA850. Add the assemble source file and link directive code, as shown below.
Page 794 CHAPTER 28 ON-CHIP DEBUG FUNCTION (5) Securement of communication serial interface UARTA0, CSIB0, or CSIB3 is used for communication between MINICUBE2 and the target system. The settings related to the serial interface modes are performed by the debug monitor program, but if the setting is changed by the user program, a communication error may occur.
Page 795 CHAPTER 28 ON-CHIP DEBUG FUNCTION • Port registers when UARTA0 is used When UARTA0 is used, port registers are set to make the TXDA0 and RXDA0 pins valid by the debug monitor program. Do not change the following register settings with the user program during debugging. (The same value can be overwritten.) ×...
Page 796: Cautions
CHAPTER 28 ON-CHIP DEBUG FUNCTION • Port registers when CSIB3 is used When CSIB3 is used, port registers are set to make the SIB3, SOB3, SCKB3, and HS (PMC0) pins valid by the debug monitor program. Do not change the following register settings with the user program during debugging.
Page 797 CHAPTER 28 ON-CHIP DEBUG FUNCTION (3) When pseudo real-time RAM monitor (RRM) function and DMM function do not operate The pseudo RRM function and DMM function do not operate if one of the following conditions is satisfied. • Interrupts are disabled (DI) •...
Page 798: Rom Security Function
28.3 ROM Security Function 28.3.1 Security ID The flash memory versions of the V850ES/JJ3 perform authentication using a 10-byte ID code to prevent the contents of the flash memory from being read by an unauthorized person during on-chip debugging by the on-chip debug emulator.
Page 799: Setting
CHAPTER 28 ON-CHIP DEBUG FUNCTION 28.3.2 Setting The following shows how to set the ID code as shown in Table 28-5. When the ID code is set as shown in Table 28-5, the ID code input in the configuration dialog box of the ID850QB is “123456789ABCDEF123D4”...
Page 800 CHAPTER 28 ON-CHIP DEBUG FUNCTION [Program example (when using CA850 Ver. 3.10 or later)] #-------------------------------------- SECURITYID #-------------------------------------- .section "SECURITY_ID" --Interrupt handler address 0x70 .word 0x78563412 --0-3 byte code .word 0xF1DEBC9A --4-7 byte code .hword 0xD423 --8-9 byte code Remark Add the above program example to the startup files. User’s Manual U18376EJ3V0UD...
Page 801: Chapter 29 Electrical Specifications
CHAPTER 29 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (T = 25°C) (1/2) Parameter Symbol Conditions Ratings Unit −0.5 to +4.6 Supply voltage = EV = AV = AV REF0 REF1 −0.5 to +4.6 = EV = AV = AV REF0 REF1 −0.5 to +4.6 = EV = AV...
Page 802 CHAPTER 29 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (T = 25°C) (2/2) Parameter Symbol Conditions Ratings Unit Output current, low P00 to P06, P30 to P39, P40 to Per pin P42, P50 to P55, P60 to P615, Total of all pins P80, P81, P90 to P915 PCD0 to PCD3, PCM0 to PCM5, Per pin...
Page 803 CHAPTER 29 ELECTRICAL SPECIFICATIONS = −40 to +85°C, V Capacitance (T = EV = AV = AV = EV = AV = 0 V) REF0 REF1 Parameter Symbol Conditions MIN. TYP. MAX. Unit I/O capacitance = 1 MHz Unmeasured pins returned to 0 V Operating Conditions = −40 to +85°C, V = EV...
Page 804 After IDLE2 mode is Note 3 released Notes 1. The oscillation frequency shown above indicates only oscillator characteristics. Use the V850ES/JJ3 so that the internal operation conditions do not exceed the ratings shown in AC Characteristics and DC Characteristics. 2. Time required from start of oscillation until the resonator stabilizes.
Page 805 The oscillation voltage and oscillation frequency indicate only oscillator characteristics. Use the V850ES/JJ3 so that the internal operating conditions are within the specifications of the DC and AC characteristics. = −20 to +80°C) <R>...
Page 806 Oscillation Note 2 stabilization time Notes 1. The oscillation frequency shown above indicates only oscillator characteristics. Use the V850ES/JJ3 so that the internal operation conditions do not exceed the ratings shown in AC Characteristics and DC Characteristics. 2. Time required from when V reaches the oscillation voltage range (2.85 V (MIN.)) to when the crystal...
Page 807 CHAPTER 29 ELECTRICAL SPECIFICATIONS PLL Characteristics = −40 to +85°C, V = EV = AV = AV = EV = AV = 0 V) REF0 REF1 Parameter Symbol Conditions MIN. TYP. MAX. Unit ×4 mode Input frequency ×8 mode ×4 mode Output frequency ×8 mode μ...
Page 808 CHAPTER 29 ELECTRICAL SPECIFICATIONS DC Characteristics = −40 to +85°C, V = EV = AV = AV = EV = AV = 0 V) (1/3) REF0 REF1 Parameter Symbol Conditions MIN. TYP. MAX. Unit Input voltage, high RESET, FLMD0 0.8EV P00 to P06, P30 to P37, P42, P50 to P55, 0.8EV P60 to P615, P80, P81, P92 to P915...
Page 809 CHAPTER 29 ELECTRICAL SPECIFICATIONS DC Characteristics = −40 to +85°C, V = EV = AV = AV = EV = AV = 0 V) (2/3) REF0 REF1 Parameter Symbol Conditions MIN. TYP. MAX. Unit − 1.0 Output voltage, P00 to P06, Per pin Total of all pins = −1.0 mA...
Page 810 CHAPTER 29 ELECTRICAL SPECIFICATIONS DC Characteristics = −40 to +85°C, V = EV = AV = AV = EV = AV = 0 V) (3/3) REF0 REF1 Parameter Symbol Conditions MIN. TYP. MAX. Unit Note 1 Supply current Normal operation = 32 MHz (f = 4 MHz) = 20 MHz (f...
Page 811 CHAPTER 29 ELECTRICAL SPECIFICATIONS Data Retention Characteristics In STOP mode = −40 to +85°C, V = EV = AV = AV = EV = AV = 0 V) REF0 REF1 Parameter Symbol Conditions MIN. TYP. MAX. Unit Data retention voltage STOP mode (all functions stopped) DDDR μ...
Page 812 CHAPTER 29 ELECTRICAL SPECIFICATIONS AC Characteristics AC Test Input Measurement Points (V , AV , AV , EV REF0 REF1 Measurement points AC Test Output Measurement Points Measurement points Load Conditions (Device under measurement) = 50 pF Caution If the load capacitance exceeds 50 pF due to the circuit configuration, bring the load capacitance of the device to 50 pF or less by inserting a buffer or by some other means.
Page 813 CHAPTER 29 ELECTRICAL SPECIFICATIONS CLKOUT Output Timing = −40 to +85°C, V = EV = AV = AV = EV = AV = 0 V) REF0 REF1 Parameter Symbol Conditions MIN. MAX. Unit μ Output cycle <1> 31.25 ns 31.25 /2 −...
Page 814 CHAPTER 29 ELECTRICAL SPECIFICATIONS Bus Timing (1) In multiplexed bus mode Caution When operating at f > 20 MHz, be sure to insert address hold waits and address setup waits. (a) Read/write cycle (CLKOUT asynchronous) = −40 to +85°C, V = EV = AV = AV...
Page 815 CHAPTER 29 ELECTRICAL SPECIFICATIONS Read Cycle (CLKOUT Asynchronous): In Multiplexed Bus Mode CLKOUT (output) CS0 to CS3 (output) A16 to A23 (output) <9> Hi-Z AD0 to AD15 (I/O) Address Data <6> <7> <12> ASTB (output) <17> <14> <8> <13> <11> <10>...
Page 816 CHAPTER 29 ELECTRICAL SPECIFICATIONS Write Cycle (CLKOUT Asynchronous): In Multiplexed Bus Mode CLKOUT (output) CS0 to CS3 (output) A16 to A23 (output) AD0 to AD15 (I/O) Address Data <6> <7> ASTB (output) <17> <18> <14> <11> <19> <20> WR0, WR1 (output) <16>...
Page 817 CHAPTER 29 ELECTRICAL SPECIFICATIONS (b) Read/write cycle (CLKOUT synchronous): In multiplexed bus mode = −40 to +85°C, V = EV = AV = AV = EV = AV = 0 V, C = 50 pF) REF0 REF1 Parameter Symbol Conditions MIN.
Page 818 CHAPTER 29 ELECTRICAL SPECIFICATIONS Write Cycle (CLKOUT Synchronous): In Multiplexed Bus Mode CLKOUT (output) <29> CS0 to CS3 (output) A16 to A23 (output) <35> AD0 to AD15 (I/O) Address Data <31> <31> ASTB (output) WR0, WR1 (output) <32> <32> WAIT (input) <36>...
Page 819 CHAPTER 29 ELECTRICAL SPECIFICATIONS (2) In separate bus mode Caution When operating at f > 20 MHz, be sure to insert address hold waits, address setup waits, and data waits. (a) Read cycle (CLKOUT asynchronous): In separate bus mode = −40 to +85°C, V = EV = AV = AV...
Page 820 CHAPTER 29 ELECTRICAL SPECIFICATIONS Read Cycle (CLKOUT Asynchronous): In Separate Bus Mode CLKOUT (output) CS0 to CS3 (output) A0 to A23 (output) <39> <43> Hi-Z Hi-Z AD0 to AD15 (I/O) <42> <38> <41> <40> (output) <47> <45> <46> <44> WAIT (input) <48>...
Page 821 CHAPTER 29 ELECTRICAL SPECIFICATIONS (b) Write cycle (CLKOUT asynchronous): In separate bus mode = −40 to +85°C, V = EV = AV = AV = EV = AV = 0 V, C = 50 pF) REF0 REF1 Parameter Symbol Conditions MIN.
Page 822 CHAPTER 29 ELECTRICAL SPECIFICATIONS Write Cycle (CLKOUT Asynchronous): In Separate Bus Mode CLKOUT (output) CS0 to CS3 (output) A0 to A23 (output) <53> <58> Hi-Z Hi-Z AD0 to AD15 (I/O) <55> <57> <52> <56> <54> WR0, WR1 (output) <62> <60> <59>...
Page 823 CHAPTER 29 ELECTRICAL SPECIFICATIONS (c) Read cycle (CLKOUT synchronous): In separate bus mode = −40 to +85°C, V = EV = AV = AV = EV = AV = 0 V, C = 50 pF) REF0 REF1 Parameter Symbol Conditions MIN.
Page 824 CHAPTER 29 ELECTRICAL SPECIFICATIONS (d) Write cycle (CLKOUT synchronous): In separate bus mode = −40 to +85°C, V = EV = AV = AV = EV = AV = 0 V, C = 50 pF) REF0 REF1 Parameter Symbol Conditions MIN.
Page 825 CHAPTER 29 ELECTRICAL SPECIFICATIONS (3) Bus hold (a) CLKOUT asynchronous = −40 to +85°C, V = EV = AV = AV = EV = AV = 0 V, C = 50 pF) REF0 REF1 Parameter Symbol Conditions MIN. MAX. Unit HLDRQ high-level width <78>...
Page 826 CHAPTER 29 ELECTRICAL SPECIFICATIONS (b) CLKOUT synchronous = −40 to +85°C, V = EV = AV = AV = EV = AV = 0 V, C = 50 pF) REF0 REF1 Parameter Symbol Conditions MIN. MAX. Unit HLDRQ setup time (to CLKOUT↓) <83>...
Page 827 CHAPTER 29 ELECTRICAL SPECIFICATIONS Power On/Power Off/Reset Timing = −40 to +85°C, V = AV = EV = 0 V, C = 50 pF) Parameter Symbol Conditions MIN. MAX. Unit ↑ → V ↑ <87> ↑ → AV ↑ , AV <88>...
Page 828 CHAPTER 29 ELECTRICAL SPECIFICATIONS Key Return Timing = −40 to +85°C, V = EV = AV = AV = EV = AV = 0 V, C = 50 pF) REF1 Parameter Symbol Conditions MIN. MAX. Unit KRn high-level width Analog noise elimination WKRH KRn low-level width Analog noise elimination...
Page 829 CHAPTER 29 ELECTRICAL SPECIFICATIONS CSIB Timing (1) Master mode = −40 to +85°C, V = EV = AV = AV = EV = AV = 0 V, C = 50 pF) REF0 REF1 Parameter Symbol Conditions MIN. MAX. Unit SCKBn cycle time <94>...
Page 830 CHAPTER 29 ELECTRICAL SPECIFICATIONS = −40 to +85°C, V C Bus Mode (T = EV = AV = AV = EV = AV = 0 V, C = 50 pF) REF0 REF1 Parameter Symbol Normal Mode High-Speed Mode Unit MIN. MAX.
Page 831 CHAPTER 29 ELECTRICAL SPECIFICATIONS C Bus Mode <101> <102> SCL0n (I/O) <105> <103> <107> <106> <104> <108> <100> <109> <100> SDA0n (I/O) <99> <106> <107> Stop Start Restart Stop condition condition condition condition Remark n = 0 to 2 A/D Converter = −40 to +85°C, V , 3.0 V ≤...
Page 832 CHAPTER 29 ELECTRICAL SPECIFICATIONS D/A Converter = −40 to +85°C, V , 3.0 V ≤ AV ≤ 3.6 V, V = EV = AV = AV = EV = AV = 0 V, C = 50 pF) REF0 REF1 REF1 Parameter Symbol Conditions...
Page 833 CHAPTER 29 ELECTRICAL SPECIFICATIONS RAM Retention Detection = −40 to +85°C, V = EV = AV = AV = EV = AV = 0 V, C = 50 pF) REF0 REF1 Parameter Symbol Conditions MIN. TYP. MAX. Unit Detection voltage RAMH Supply voltage rise time = 0 to 2.85 V...
Page 834 CHAPTER 29 ELECTRICAL SPECIFICATIONS Flash Memory Programming Characteristics = −40 to +85°C, V = EV = AV = AV = EV = AV = 0 V, C = 50 pF) REF0 REF1 (1) Basic characteristics Parameter Symbol Conditions MIN. TYP. MAX.
Page 835 CHAPTER 29 ELECTRICAL SPECIFICATIONS (3) Programming characteristics Parameter Symbol Conditions MIN. TYP. MAX. Unit Chip erase time = 32 MHz, batch erase Write time per 256 bytes = 32 MHz Block internal verify time = 32 MHz Block blank check time = 32 MHz Flash memory = 32 MHz...
Page 836: Chapter 30 Package Drawing
(UNIT:mm) ITEM DIMENSIONS 20.00±0.20 20.00±0.20 22.00±0.20 22.00±0.20 1.60 MAX. 0.10±0.05 1.40±0.05 0.25 + 0.07 0.20 0.03 + 0.075 0.125 0.025 0.50 0.60±0.15 1.00±0.20 5° θ 3° 3° 0.50 0.08 0.08 1.25 1.25 P144GJ-50-GAE-1 NEC Electronics Corporation 2007 User’s Manual U18376EJ3V0UD...
Page 837: Chapter 31 Recommended Soldering Conditions
Caution Do not use different soldering methods together (except for partial heating). Remarks 1. Products with -AX at the end of the part number are lead-free products. 2. For soldering methods and conditions other than those recommended above, please contact an NEC Electronics sales representative.
Page 838: Appendix A Development Tools
APPENDIX A DEVELOPMENT TOOLS The following development tools are available for the development of systems that employ the V850ES/JJ3. Figure A-1 shows the development tool configuration. • Support for PC98-NX series Unless otherwise specified, products supported by IBM PC/AT compatibles are compatible with PC98-NX series computers.
Page 839 APPENDIX A DEVELOPMENT TOOLS Figure A-1. Development Tool Configuration Software package Language processing software Debugging software • Integrated debugger • C compiler package • System simulator • Device file Control software • Project manager Embedded software Note 1 • Real-time OS (Windows only) •...
Page 840: Software Package
APPENDIX A DEVELOPMENT TOOLS A.1 Software Package SP850 Development tools (software) commonly used with V850 microcontrollers are included Software package for V850 this package. microcontrollers μ Part number: S××××SP850 Remark ×××× in the part number differs depending on the host machine and OS used. μ...
Page 841: Debugging Tools (Hardware)
APPENDIX A DEVELOPMENT TOOLS A.4 Debugging Tools (Hardware) A.4.1 When using IECUBE QB-V850ESSX2 The system configuration when connecting the QB-V850ESSX2 to the host machine (PC-9821 series, PC/AT compatible) is shown below. Even if optional products are not prepared, connection is possible. Figure A-2.
Page 842 The in-circuit emulator serves to debug hardware and software when developing In-circuit emulator application systems using the V850ES/JJ3. It supports to the integrated debugger ID850QB. This emulator should be used in combination with a power supply unit and emulation probe. Use the USB interface cable to connect this emulator to the host machine.
Page 843: When Using Minicube Qb-V850Mini
8830E-026-170S (supplied with MINICUBE) Note 2 KEL connector 8830E-026-170L (sold separately) Notes 1. Download the device file from the NEC Electronics website. http://www.necel.com/micro/ods/eng/index.html 2. Product of KEL Corporation Remark The numbers in the angular brackets correspond to the numbers in Figure A-3.
Page 844: When Using Minicube2 Qb-Mini2
MINICUBE. The cable length is approximately 2 m. <4> MINICUBE2 This on-chip debug emulator serves to debug hardware and software when On-chip debug emulator developing application systems using the V850ES/JJ3. It supports integrated debugger ID850QB. <5> 16-pin target cable Cable to connect MINICUBE2 and the target system.
Page 845: Debugging Tools (Software)
APPENDIX A DEVELOPMENT TOOLS A.5 Debugging Tools (Software) SM850 (under development) This simulator is used with V850 microcontrollers. SM850 is Windows-based software. System simulator Debugging of C source and assembler files is possible during simulation of the target system operation on the host machine. By using SM850, logic verification and performance verification of applications can be performed independently from hardware development.
Page 846: Embedded Software
APPENDIX A DEVELOPMENT TOOLS A.6 Embedded Software μ RX850, RX850 Pro The RX850 and RX850 Pro are real-time OSs conforming to ITRON 3.0 specifications. Real-time OS A tool (configurator) for generating multiple information tables is supplied. RX850 Pro has more functions than the RX850. μ...
Page 847: Flash Memory Writing Tools
APPENDIX A DEVELOPMENT TOOLS A.7 Flash Memory Writing Tools Flashpro IV Flash programmer dedicated to microcontrollers with on-chip flash memory. (part number: PG-FP4) Flash programmer QB-MINI2 (MINICUBE2) On-chip debug emulator with programming function. FA-144GJ-UEN-A Flash memory writing adapter used connected to the Flashpro IV, etc. (not wired). Flash memory writing adapter FA-70F3368GJ-UEN-RX Flash memory writing adapter used connected to the Flashpro IV, etc.
Page 848: Appendix B Major Differences Between V850Es/Jj3 And V850Es/Jj2
APPENDIX B MAJOR DIFFERENCES BETWEEN V850ES/JJ3 AND V850ES/JJ2 Differences between the V850ES/JJ3 and V850ES/JJ2 are shown below. For details, refer to each corresponding section. Table B-1. Major Differences Between V850ES/JJ3 and V850ES/JJ2 (1/2) Major Differences V850ES/JJ3 V850ES/JJ2 Refer to: , BV...
Page 849 APPENDIX B MAJOR DIFFERENCES BETWEEN V850ES/JJ3 AND V850ES/JJ2 Table B-1. Major Differences Between V850ES/JJ3 and V850ES/JJ2 (2/2) Major Differences V850ES/JJ3 V850ES/JJ2 Refer to: Electrical Operating condition = 2.5 to 32 MHz = 2.5 to 20 MHz Chapter 29 specifications (internal system...
Page 850: Appendix C Register Index
APPENDIX C REGISTER INDEX (1/12) Symbol Name Unit Page ADA0CR0 A/D conversion result register 0 ADA0CR0H A/D conversion result register 0H ADA0CR1 A/D conversion result register 1 ADA0CR1H A/D conversion result register 1H ADA0CR2 A/D conversion result register 2 ADA0CR2H A/D conversion result register 2H ADA0CR3 A/D conversion result register 3...
Page 851 APPENDIX C REGISTER INDEX (2/12) Symbol Name Unit Page CB0CTL0 CSIB0 control register 0 CB0CTL1 CSIB0 control register 1 CB0CTL2 CSIB0 control register 2 CB0RIC Interrupt control register INTC CB0RX CSIB0 receive data register CB0RXL CSIB0 receive data register L CB0STR CSIB0 status register CB0TIC...
Page 852 APPENDIX C REGISTER INDEX (3/12) Symbol Name Unit Page CB4RXL CSIB4 receive data register L CB4STR CSIB4 status register CB4TIC Interrupt control register INTC CB4TX CSIB4 transmit data register CB4TXL CSIB4 transmit data register L CB5CTL0 CSIB5 control register 0 CB5CTL1 CSIB5 control register 1 CB5CTL2...
Page 853 APPENDIX C REGISTER INDEX (4/12) Symbol Name Unit Page DDA2L DMA destination address register 2L DDA3H DMA destination address register 3H DDA3L DMA destination address register 3L DMAIC0 Interrupt control register INTC DMAIC1 Interrupt control register INTC DMAIC2 Interrupt control register INTC DMAIC3 Interrupt control register...
Page 854 APPENDIX C REGISTER INDEX (5/12) Symbol Name Unit Page IICX1 IIC function expansion register 1 IICX2 IIC function expansion register 2 IMR0 Interrupt mask register 0 INTC IMR0H Interrupt mask register 0H INTC IMR0L Interrupt mask register 0L INTC IMR1 Interrupt mask register 1 INTC IMR1H...
Page 855 APPENDIX C REGISTER INDEX (6/12) Symbol Name Unit Page Port 6 register H Port Port 6 register L Port Port 7 register H Port Port 7 register L Port Port 8 register Port Port 9 register Port Port 9 register H Port Port 9 register L Port...
Page 856 APPENDIX C REGISTER INDEX (7/12) Symbol Name Unit Page PFCE9H Port 9 function control expansion register H Port PFCE9L Port 9 function control expansion register L Port PIC0 Interrupt control register INTC PIC1 Interrupt control register INTC PIC2 Interrupt control register INTC PIC3 Interrupt control register...
Page 857 APPENDIX C REGISTER INDEX (8/12) Symbol Name Unit Page PMCD Port CD mode register Port PMCDH Port DH mode control register Port PMCDL Port DL mode control register Port PMCDLH Port DL mode control register H Port PMCDLL Port DL mode control register L Port PMCM Port CM mode register...
Page 858 APPENDIX C REGISTER INDEX (9/12) Symbol Name Unit Page TP0CCIC1 Interrupt control register INTC TP0CCR0 TMP0 capture/compare register 0 Timer TP0CCR1 TMP0 capture/compare register 1 Timer TP0CNT TMP0 counter read buffer register Timer TP0CTL0 TMP0 control register 0 Timer TP0CTL1 TMP0 control register 1 Timer TP0IOC0...
Page 859 APPENDIX C REGISTER INDEX (10/12) Symbol Name Unit Page TP3OPT0 TMP3 option register 0 Timer TP3OVIC Interrupt control register INTC TP4CCIC0 Interrupt control register INTC TP4CCIC1 Interrupt control register INTC TP4CCR0 TMP4 capture/compare register 0 Timer TP4CCR1 TMP4 capture/compare register 1 Timer TP4CNT TMP4 counter read buffer register...
Page 860 APPENDIX C REGISTER INDEX (11/12) Symbol Name Unit Page TP7IOC0 TMP7 I/O control register 0 Timer TP7IOC1 TMP7 I/O control register 1 Timer TP7IOC2 TMP7 I/O control register 2 Timer TP7OPT0 TMP7 option register 0 Timer TP7OVIC Interrupt control register INTC TP8CCIC0 Interrupt control register...
Page 861 APPENDIX C REGISTER INDEX (12/12) Symbol Name Unit Page UA1OPT0 UARTA1 option control register 0 UART UA1RIC Interrupt control register INTC UA1RX UARTA1 receive data register UART UA1STR UARTA1 status register UART UA1TIC Interrupt control register INTC UA1TX UARTA1 transmit data register UART UA2CTL0 UARTA2 control register 0...
Page 862: Appendix D Instruction Set List
APPENDIX D INSTRUCTION SET LIST D.1 Conventions (1) Register symbols used to describe operands Register Symbol Explanation reg1 General-purpose registers: Used as source registers. reg2 General-purpose registers: Used mainly as destination registers. Also used as source register in some instructions. reg3 General-purpose registers: Used mainly to store the remainders of division results and the higher 32 bits of multiplication results.
Page 863 APPENDIX D INSTRUCTION SET LIST (3) Register symbols used in operations Register Symbol Explanation ← Input for GR [ ] General-purpose register SR [ ] System register zero-extend (n) Expand n with zeros until word length. sign-extend (n) Expand n with signs until word length. load-memory (a, b) Read size b data from address a.
Page 864 APPENDIX D INSTRUCTION SET LIST (5) Register symbols used in flag operations Identifier Explanation (Blank) No change Clear to 0 Set or cleared in accordance with the results. Previously saved values are restored. (6) Condition codes Condition Code Condition Formula Explanation (cccc) 0 0 0 0...
Page 865: Instruction Set (In Alphabetical Order)
APPENDIX D INSTRUCTION SET LIST D.2 Instruction Set (in Alphabetical Order) (1/6) Mnemonic Operand Opcode Operation Execution Flags Clock CY OV S Z SAT × × × × reg1,reg2 r r rr r0 01 11 0 RRRRR GR[reg2]←GR[reg2]+GR[reg1] × × ×...
Page 866 APPENDIX D INSTRUCTION SET LIST (2/6) Mnemonic Operand Opcode Operation Execution Flags Clock CY OV S Z SAT DBTRAP 1111100001000000 DBPC←PC+2 (restored PC) DBPSW←PSW PSW.NP←1 PSW.EP←1 PSW.ID←1 PC←00000060H 0000011111100000 PSW.ID←1 0000000101100000 DISPOSE imm5,list12 0 0 0 0 0 1 1 0 0 1 i i i i i L sp←sp+zero-extend(imm5 logically shift left by 2) LLLLLLLLLLL00000 GR[reg in list12]←Load-memory(sp,Word)
Page 867 APPENDIX D INSTRUCTION SET LIST (3/6) Mnemonic Operand Opcode Operation Execution Flags Clock CY OV S Z SAT LD.H disp16[reg1],reg2 rrrrr111001RRRRR adr←GR[reg1]+sign-extend(disp16) Note ddddddddddddddd0 GR[reg2]←sign-extend(Load-memory(adr,Halfword)) Note 8 LDSR reg2,regID rrrrr111111RRRRR SR[regID]←GR[reg2] Other than regID = PSW 0000000000100000 × × × ×...
Page 868 APPENDIX D INSTRUCTION SET LIST (4/6) Mnemonic Operand Opcode Operation Execution Flags Clock CY OV S Z SAT × × reg1,reg2 r r rr r0 01 00 0 RRRRR GR[reg2]←GR[reg2]OR GR[reg1] × × imm16,reg1,reg2 r r rr r1 10 10 0 RRRRR GR[reg2]←GR[reg1]OR zero-extend(imm16) i i i i i i i i i i i i i i i i PREPARE...
Page 869 APPENDIX D INSTRUCTION SET LIST (5/6) Mnemonic Operand Opcode Operation Execution Flags Clock CY OV S Z SAT × SET1 bit#3,disp16[reg1] 00bbb111110RRRRR adr←GR[reg1]+sign-extend(disp16) dddddddddddddddd Z flag←Not (Load-memory-bit(adr,bit#3)) Note 3 Note 3 Note 3 Store-memory-bit(adr,bit#3,1) × reg2,[reg1] r r rr r1 11 11 1 RRRRR adr←GR[reg1] Z flag←Not(Load-memory-bit(adr,reg2)) 0000000011100000...
Page 870 APPENDIX D INSTRUCTION SET LIST (6/6) Mnemonic Operand Opcode Operation Execution Flags Clock CY OV S Z SAT × × × × reg1,reg2 r r rr r0 01 10 1 RRRRR GR[reg2]←GR[reg2]–GR[reg1] × × × × SUBR reg1,reg2 r r rr r0 01 10 0 RRRRR GR[reg2]←GR[reg1]–GR[reg2] SWITCH reg1 00000000010RRRRR adr←(PC+2) + (GR [reg1] logically shift left by 1)
Page 871 APPENDIX D INSTRUCTION SET LIST Notes 12. In this instruction, for convenience of mnemonic description, the source register is made reg2, but the reg1 field is used in the opcode. Therefore, the meaning of register specification in the mnemonic description and in the opcode differs from other instructions. r r r r r = regID specification RRRRR = reg2 specification...
Page 872: Appendix E List Of Cautions
APPENDIX E LIST OF CAUTIONS This appendix lists cautions described in this document. “Classification (hard/soft)” in table is as follows. Hard: Cautions for microcontroller internal/external hardware Soft: Cautions for software such as register settings or programs (1/37) Function Details of Cautions Page Function...
Page 873 83 immediately after a write access to the PRCMD register, the PRERR bit is set to Registers to be Be sure to set the following registers first when using the V850ES/JJ3. p. 84 • System wait control register (VSWC) set first •...
Page 874 APPENDIX E LIST OF CAUTIONS (3/37) Function Details of Cautions Page Function Port PM1 register When using one of the P10 and P11 pins as an I/O port and the other as a D/A p. 97 functions output pin, do so in an application where the port I/O level does not change during D/A output.
Page 875 APPENDIX E LIST OF CAUTIONS (4/37) Function Details of Cautions Page Function Functions P6 register To read/write bits 8 to 15 of the P6 register in 8-bit or 1-bit units, specify them as p. 111 bits 0 to 7 of the P6H register. PM6 register To read/write bits 8 to 15 of the PM6 register in 8-bit or 1-bit units, specify them p.
Page 876 APPENDIX E LIST OF CAUTIONS (5/37) Function Details of Cautions Page Function Port PMDL register To read/write bits 8 to 15 of the PMDL register in 8-bit or 1-bit units, specify them p. 136 functions as bits 0 to 7 of the PMDLH register. PMCDL register When the SMSEL bit of the EXIMC register = 1 (separate mode) and the BS30 to p.
Page 877 APPENDIX E LIST OF CAUTIONS (6/37) Function Details of Cautions Page Function Port PFn.PFnm bit In port mode, the PFn.PFnm bit is valid only in the output mode (PMn.PMnm bit = p. 181 functions in port mode 0). In the input mode (PMnm bit = 1), the value of the PFnm bit is not reflected in the buffer.
Page 878 Also, do not access an external memory area until the initial settings of the DWC0 functions register are complete. When V850ES/JJ3 is used in separate bus mode and operated at f > 20 MHz, p. 196 be sure to insert one or more wait.
Page 879 APPENDIX E LIST OF CAUTIONS (8/37) Function Details of Cautions Page Function Clock LOCKR register The LOCK register does not reflect the lock status of the PLL in real time. p. 221 generation μ PLLS register Set so that the lockup time is 800 s or longer.
Page 880 APPENDIX E LIST OF CAUTIONS (9/37) Function Details of Cautions Page Function 16-bit TPnCCR1 Accessing the TPnCCR1 register is prohibited in the following statuses. For p. 235 timer/ register details, see 3.4.8 (2) Accessing specific on-chip peripheral I/O registers. • When the CPU operates with the subclock and the main clock oscillation is event counter P stopped...
Page 881 APPENDIX E LIST OF CAUTIONS (10/37) Function Details of Cautions Page Function 16-bit Note on To change the set value of the TPnCCRm register to a smaller value, stop p. 274 timer/ rewriting counting once, and then change the set value. event TPnCCRm If the value of the TPnCCRm register is rewritten to a smaller value during...
Page 882 APPENDIX E LIST OF CAUTIONS (11/37) Function Details of Cautions Page Function 16-bit TQ0IOC2 The TQ0ETS1 and TQ0ETS0 bits are valid only when the external trigger pulse p. 320 timer/ register output mode (TQ0CTL1.TQ0MD2 to TQ0CTL1.TQ0MD0 bits = 010) or the one- event shot pulse output mode (TQ0CTL1.TQ0MD2 to TQ0CTL1.TQ0MD0 = 011) is set.
Page 883 APPENDIX E LIST OF CAUTIONS (12/37) Function Details of Cautions Page Function 16-bit Notes on To change the value of the TQ0CCR0 register to a smaller value, stop counting 337, timer/ rewriting once and then change the set value. event TQ0CCR0 If the value of the TQ0CCR0 register is rewritten to a smaller value during counter Q...
Page 884 APPENDIX E LIST OF CAUTIONS (13/37) Function Details of Cautions Page Function 16-bit TM0CMP0, Rewriting the TM0CMP0 and TM0CTL0 registers is prohibited while TMM0 is p. 418 interval TM0CTL0 operating. timer M registers If these registers are rewritten while the TM0CE bit is 1, the operation cannot be (TMM) guaranteed.
Page 885 APPENDIX E LIST OF CAUTIONS (14/37) Function Details of Cautions Page Function Watchdog WDTM2 register To stop the operation of watchdog timer 2, set the RCM.RSTOP bit to 1 (to stop p. 431 timer 2 the internal oscillator) and write 00H in the WDTM2 register. If the RCM.RSTOP function bit cannot be set to 1, set the WDCS23 bit to 1 (2 is selected and the clock...
Page 886 APPENDIX E LIST OF CAUTIONS (15/37) Function Details of Cautions Page Function ADA0M0 A write operation to bit 0 is ignored. p. 446 converter register Changing the ADA0M1.ADA0FR2 to ADA0M1.ADA0FR0 bits is prohibited while p. 446 A/D conversion is enabled (ADA0CE bit = 1). When writing data to the ADA0M0, ADA0M2, ADA0S, ADA0PFM, or ADA0PFT p.
Page 887 APPENDIX E LIST OF CAUTIONS (16/37) Function Details of Cautions Page Function ADA0S register When writing data to the ADA0S register in the following modes, stop the A/D p. 451 converter conversion by clearing the AD0M0.ADA0CE bit to 0. After the data is written to the register, enable the A/D conversion again by setting the ADA0CE bit to 1.
Page 888 APPENDIX E LIST OF CAUTIONS (17/37) Function Details of Cautions Page Function Input range of Input the voltage within the specified range to the ANI0 to ANI15 pins. If a voltage p. 469 converter ANI0 to ANI15 equal to or higher than AV or equal to or lower than AV (even within the REF0...
Page 889 APPENDIX E LIST OF CAUTIONS (18/37) Function Details of Cautions Page Function Standby mode Because the A/D converter stops operating in the STOP mode, conversion results p. 471 converter are invalid, so power consumption can be reduced. Operations are resumed after the STOP mode is released, but the A/D conversion results after the STOP mode is released are invalid.
Page 890 APPENDIX E LIST OF CAUTIONS (19/37) Function Details of Cautions Page Function DA0M register The output trigger in the real-time output mode (DA0MDn bit = 1) is as follows. p. 478 • When n = 0: INTTP2CC0 signal (see CHAPTER 7 16-BIT TIMER/EVENT converter COUNTER P (TMP)) •...
Page 891 APPENDIX E LIST OF CAUTIONS (20/37) Function Details of Cautions Page Function Asynchro- UART When reception is completed, read the UAnRX register after the reception p. 505 nous serial reception complete interrupt request signal (INTUAnR) has been generated, and clear the interface A UAnPWR or UAnRXE bit to 0.
Page 892 APPENDIX E LIST OF CAUTIONS (21/37) Function Details of Cautions Page Function Asynchro- Start up Start up the UARTAn in the following sequence. p. 518 nous serial UARTAn <1> Set the UAnCTL0.UAnPWR bit to 1. interface A <2> Set the ports. (UARTA) <3>...
Page 893 APPENDIX E LIST OF CAUTIONS (22/37) Function Details of Cautions Page Function 3-wire Baud rage Set f to 8 MHz or lower. p. 566 BRGm variable- generation length When When transferring transmit data and receive data using DMA transfer, error p.
Page 894 OCKS1 register to 00H (I C division clock stopped status). Start condition When the IICCn.IICEn bit of the V850ES/JJ3 is set to 1 while communications p. 593 with other devices are in progress, the start condition may be detected depending on the status of the communication line.
Page 895 Details of Cautions Page Function C bus When the IICCn.IICEn bit of the V850ES/JJ3 is set to 1 while communications p. 631 When among other devices are in progress, the start condition may be detected communication depending on the status of the communication line. Be sure to set the IICCn.IICEn among other bit to 1 when the SCL0n and SDA0n lines are high level.
Page 896 APPENDIX E LIST OF CAUTIONS (25/37) Function Details of Cautions Page Function DSA0 to DSA3 When the value of the DSAn register is read, two 16-bit registers, DSAnH and p. 649 function registers DSAnL, are read. If reading and updating conflict, the value being updated may (DMA be read (see 18.13 Cautions).
Page 897 APPENDIX E LIST OF CAUTIONS (26/37) Function Details of Cautions Page Function DCHC0 to The TCn bit is read-only. p. 653 function DCHC3 The INITn and STGn bits are write-only. p. 653 (DMA registers Be sure to clear bits 6 to 3 of the DCHCn register to 0. p.
Page 898 APPENDIX E LIST OF CAUTIONS (27/37) Function Details of Cautions Page Function Caution for When executing the following instructions located in the internal RAM, do not p. 665 function DMA transfer execute a DMA transfer that transfers data to/from the internal RAM (transfer (DMA executed on source/destination), because the CPU may not operate correctly afterward.
Page 899 APPENDIX E LIST OF CAUTIONS (28/37) Function Details of Cautions Page Function <4> Again, clear the Enn bit of the channel to be forcibly terminated. DMA transfer p. 667 If the target of transfer for the channel to be forcibly terminated (transfer function initialization source/destination) is the internal RAM, execute this operation once...
Page 900 APPENDIX E LIST OF CAUTIONS (29/37) Function Details of Cautions Page Function DMA start factor Do not start two or more DMA channels with the same start factor. If two or more p. 668 function channels are started with the same factor, DMA for which a channel has already (DMA been set may be started or a DMA channel with a lower priority may be controller)
Page 901 APPENDIX E LIST OF CAUTIONS (30/37) Function Details of Cautions Page Function Interrupt/ ISPR register If an interrupt is acknowledged while the ISPR register is being read in the p. 690 exception interrupt enabled (EI) status, the value of the ISPR register after the bits of the processing register have been set by acknowledging the interrupt may be read.
Page 902 APPENDIX E LIST OF CAUTIONS (31/37) Function Details of Cautions Page Function Interrupt/ NFC register After the sampling clock has been changed, it takes 3 sampling clocks to initialize p. 704 exception the digital noise eliminator. Therefore, if an INTP3 valid edge is input within these processing 3 sampling clocks after the sampling clock has been changed, an interrupt function...
Page 903 APPENDIX E LIST OF CAUTIONS (32/37) Function Details of Cautions Page Function p. 714 Standby HALT mode If the HALT instruction is executed while an unmasked interrupt request signal is function being held pending, the status shifts to HALT mode, but the HALT mode is then released immediately by the pending interrupt request.
Page 904 APPENDIX E LIST OF CAUTIONS (33/37) Function Details of Cautions Page Function μ p. 727 Standby Releasing sub- When the sub-IDLE mode is released, 12 cycles of the subclock (about 366 function IDLE mode elapse from when the interrupt request signal that releases the sub-IDLE mode is generated to when the mode is released.
Page 905 APPENDIX E LIST OF CAUTIONS (34/37) Function Details of Cautions Page Function p. 751 CRCD register Accessing the CRCD register is prohibited in the following statuses. For details, function refer to 3.4.9 (2) Accessing specific on-chip peripheral I/O registers. • When the CPU operates with the subclock and the main clock oscillation is stopped •...
Page 906 APPENDIX E LIST OF CAUTIONS (35/37) Function Details of Cautions Page Function On-chip Cautions (DUC) In the on-chip debug mode, the DDO pin is forcibly set to the high-level output. p. 787 debug Cautions (other Do not mount a device that was used for debugging on a mass-produced product, p.
Page 907 The oscillation frequency shown above indicates only oscillator characteristics. p. 804 oscillator Use the V850ES/JJ3 so that the internal operation conditions do not exceed the characteristics ratings shown in AC Characteristics and DC Characteristics. Time required to set up the flash memory. Secure the setup time using the OSTS p.
Page 908 APPENDIX E LIST OF CAUTIONS (37/37) Function Details of Cautions Page Function Electrical Subclock The subclock oscillator is designed as a low-amplitude circuit for reducing power p. 806 specifica- oscillator consumption, and is more prone to malfunction due to noise than the main clock tions characteristics oscillator.
Page 909: Appendix F Revision History
APPENDIX F REVISION HISTORY F.1 Major Revisions in This Edition Page Description • Under development → mass production Throughout μ PD70F3743GJ-GAE-AX, 70F3744GJ-GAE-AX, 70F3745GJ-GAE-AX, 70F3746GJ-GAE-AX pp. 259, 260 Modification of Figure 7-18 Register Setting for Operation in External Trigger Pulse Output Mode pp.
Page 910: Revision History Of Previous Editions
Modification of Figure 27-1 Flash Memory Mapping Modification of Figure 28-4 Memory Spaces Where Debug Monitor Programs Are CHAPTER 28 ON-CHIP Allocated DEBUG FUNCTION Modification of Table B-1 Major Differences Between V850ES/JJ3 and APPENDIX B MAJOR V850ES/JJ2 DIFFERENCES BETWEEN V850ES/JJ3 AND...
Page 911 Kawasaki, Kanagawa 211-8668, Japan Tel: 044-435-5111 http://www.necel.com/ [Asia & Oceania] [America] [Europe] NEC Electronics (China) Co., Ltd NEC Electronics America, Inc. NEC Electronics (Europe) GmbH 7th Floor, Quantum Plaza, No. 27 ZhiChunLu Haidian 2880 Scott Blvd. Arcadiastrasse 10 District, Beijing 100083, P.R.China Santa Clara, CA 95050-2554, U.S.A.

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