NEC UPD703116 User Manual page 53

(2) NMI status saving registers (FEPC, FEPSW)
There are two NMI status saving registers, FEPC and FEPSW.
Upon occurrence of a non-maskable interrupt (NMI), the contents of the program counter (PC) are saved to
FEPC and the contents of the program status word (PSW) are saved to FEPSW.
The address of the next instruction following the instruction executed when a non-maskable interrupt occurs
is saved to FEPC, except for some instructions.
The current PSW contents are saved to FEPSW.
Bits 31 to 26 of FEPC and bits 31 to 8 of FEPSW are reserved (fixed to 0) for future function expansion.
When the RETI instruction has been executed, the values of FEPC and FEPSW are restored to the PC and
PSW, respectively.
31 26 25
FEPC
0 0 0 0 0 0
31
FEPSW
0 0 0 0 0 0
(3) Interrupt source register (ECR)
Upon occurrence of an interrupt or an exception, the interrupt source register (ECR) holds the source of an
interrupt or an exception. The value held by ECR is the exception code coded for each interrupt source. This
register is a read-only register, and thus data cannot be written to it using the LDSR instruction.
31
ECR
Bit position Bit name
31 to 16 FECC Non-maskable interrupt (NMI) exception code
15 to 0 EICC Exception, maskable interrupt exception code
CHAPTER 3 CPU FUNCTION
(PC contents saved)
0 0 0 0 0 0 0 0 0 0 0 0
16 15
FECC
User's Manual U14492EJ5V0UD
8 7
0 0 0 0 0 0 (PSW contents saved)
EICC
Description
0
After reset
0xxxxxxxH
(x: Undefined)
0
After reset
000000xxH
(x: Undefined)
0
After reset
00000000H
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