NEC UPD703116 User Manual page 340

Bit position Bit name
11, 3 ECEEn
10, 2 OSTEn
9, 8, 1, 0 UDSEn1,
UDSEn0
Remark n = 0, 1
340
CHAPTER 9 TIMER/COUNTER FUNCTION
Specifies TM2n count operation enable/disable through ECLR signal input.
0: TM2n count operation not enabled
1: TM2n count operation enabled
Cautions 1. In the 32-bit cascade operation mode (CASE1 = 1), the TM2n
count operation using ECLR signal input is not performed.
2. When the ECEEn bit = 1, always set the CESE1 and CESE0 bits of
the CSE0 register to 10 (through input).
3. In the 32-bit cascade operation mode (CASE1 = 1), only TM21 is
affected by the ECEEn bit setting.
Specifies stop mode.
0: TM2n count stopped when count value is 0.
1: TM2n count not stopped when count value is 0.
Caution When the TM2n count stop is cancelled when the OSTE1n bit = 1
(TM2n count is stopped when the count value is 0), TM2n counts up
except when the UDSEn1, UDSEn0 bits = 10. The count direction
when the UDSEn1 and UDSEn0 bits = 10 is determined by the value
.
of ECLR
Specifies TM2n up/down count.
UDSEn1 UDSEn0
0 0 Perform only up count.
Clear TM2n with compare match signal.
0 1 Count up after TM2n has become 0, and count down
after a compare match occurs for sub-channels 0, 5
(triangular wave up/down count).
1 0 Selects up/down count according to the ECLR signal
input.
Up count when ECLR = 1
Down count when ECLR = 0
1 1 Setting prohibited
Cautions 1. In the 32-bit cascade operation mode (CASE1 bit = 1), set the
UDSEn1 and UDSEn0 bits to 00.
2. When the UDSEn1 and UDSEn0 bits = 10, be sure to set the
CESE1 and CESE0 bits of the CSE0 register to 10 (through input).
3. When the UDSEn1 and UDSEn0 bits = 10, compare match
between TM2n and CVSEx0 has no effect on the TM2n count
operation (x: 0 when n = 0, 5 when n = 1).
User's Manual U14492EJ5V0UD
Function
Count
(2/2)