NEC UPD703116 User Manual page 256

Next, an example of the operation timing, which depends on the values set to CM0n0 to CM0n2 (BFCMn0 to
BFCMn2) is shown.
(a) When CM0nx (BFCMnx) ≥ CM0n3 is set
Figure 9-17. Operation Timing in PWM Mode 0 (Symmetric Triangular Wave, BFCMnx ≥ CM0n3)
Interrupt request
Positive phase
(TO0n0, TO0n2, TO0n4)
Negative phase
(TO0n1, TO0n3, TO0n5)
Remarks 1. n = 0, 1
2. x = 0 to 2
3. t: Dead time = (DTRRn + 1)/f
4. The above figure shows an active high case.
When a value greater than CM0n3 is set to BFCMnx, the positive phase side (TO0n0, TO0n2, TO0n4
pins) outputs a low level, and the negative phase side (TO0n1, TO0n3, TO0n5 pins) continues to output
a high level. This feature is effective for outputting a low-level or high-level width exceeding the PWM
cycle in an application such as inverter control. Furthermore, if CM0nx = CM0n3 is set, matching of TM0n
and CM0nx is detected during down counting by TM0n, so that the F/F remains reset as is, and does not
get set.
The above explanation applies to an active high case. In an active low case, the levels of positive and
negative phases are merely inverted and other operations remain the same.
256
CHAPTER 9 TIMER/COUNTER FUNCTION
CM0n3
a
TM0n
count value
0000H
CM0nx
match
BFCMnx ≥ CM0n3
BFCMnx a
a
CM0nx
INTCM0n3
F/F
DTMnx
t
(f
CLK CLK
User's Manual U14492EJ5V0UD
CM0n3
a
CM0nx
match
BFCMnx ≥ CM0n3
BFCMnx ≥ CM0n3
INTTM0n INTCM0n3
t
: Base clock)
INTTM0n