NEC UPD703116 User Manual page 438

(3) Baud rate setting example
f
Baud Rate XX
(bps)
f
CLK
9
300 f /2
XX
8
600 f /2
XX
7
1200 f /2
XX
6
2400 f /2
XX
5
4800 f /2
XX
4
9600 f /2
XX
3
19200 f /2
XX
3
31250 f /2
XX
2
38400 f /2
XX
1
76800 f /2
XX
1
153600 f /2
XX
1
312500 f /2
XX
1
625000 f /2
XX
1
1250000 f /2
XX
1
1562500 f /2
XX
Caution The maximum allowable frequency of the base clock (f
Remark f : Internal system clock frequency
XX
f : Base clock frequency
CLK
k: Setting values of MDL7 to MDL0 bits in BRGC0 register
ERR: Baud rate error [%]
438
CHAPTER 10 SERIAL INTERFACE FUNCTION
Table 10-3. Baud Rate Generator Setting Data
= 50 MHz f = 40 MHz
XX
k ERR f k
CLK
10
163 0.15 f /2 65
XX
9
163 0.15 f /2 65
XX
8
163 0.15 f /2 65
XX
7
163 0.15 f /2 65
XX
6
163 0.15 f /2 65
XX
5
163 0.15 f /2 65
XX
4
163 0.15 f /2 65
XX
3
100 0 f /2 80
XX
3
163 0.15 f /2 65
XX
2
163 0.15 f /2 65
XX
1
81 0.47 f /2 65
XX
1
40 0 f /2 32
XX
1
20 0 f /2 16
XX
1
10 0 f /2 8
XX
1
8 0 f /2 8
XX
User's Manual U14492EJ5V0UD
f = 33 MHz
XX
ERR f k ERR
CLK
8
0.16 f /2 215 –0.07
XX
7
0.16 f /2 215 –0.07
XX
6
0.16 f /2 215 –0.07
XX
5
0.16 f /2 215 –0.07
XX
4
0.16 f /2 215 –0.07
XX
3
0.16 f /2 215 –0.07
XX
2
0.16 f /2 215 –0.07
XX
2
0 f /2 132 0
XX
1
0.16 f /2 215 –0.07
XX
1
0.16 f /2 107 0.39
XX
1
0.16 f /2 54 –0.54
XX
1
0 f /2 26 1.54
XX
1
0 f /2 13 1.54
XX
−17.5
1
0 f /2 8
XX
−18.6 − − −
) is 25 MHz.
CLK
f = 10 MHz
XX
f k ERR
CLK
7
f /2 130 0.16
XX
6
f /2 130 0.16
XX
5
f /2 130 0.16
XX
4
f /2 130 0.16
XX
3
f /2 130 0.16
XX
2
f /2 130 0.16
XX
1
f /2 130 0.16
XX
1
f /2 80 0
XX
0
f /2 130 0.16
XX
0
f /2 65 0.16
XX
0
f /2 33 –1.36
XX
0
f /2 16 0
XX
0
f /2 8 0
XX
− − −
− − −