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6.12.1 Restriction related to DMA transfer forcible termination
When terminating a DMA transfer by setting the INITn bit of the DCHCn register, the transfer may not be
terminated, but just suspended, even though the INITn bit is set to 1. As a result, when the DMA transfer of a channel
that should have been terminated is resumed, the DMA transfer will terminate after an unexpected number of
transfers are completed and a DMA transfer completion interrupt may occur.
[Preventive measures]
This problem can be avoided by implementing any of the following workarounds.
(1) Stop all the transfers from DMA channels temporarily.
The following measure is effective if the program does not assume that the TCn bit of the DCHCn register is 1
except for the following workaround processing. (Since the TCn bit of the DCHCn register is cleared to 0
when it is read, execution of the following procedure (ii) under step <5> clears this bit.)
<1> Disable interrupts (DI state).
<2> Read the DMA restart register (DRST) and transfer the ENn bit of each channel to a general-purpose
register (value A).
<3> Write 00H to the DMA restart register (DRST) twice
By executing twice, the DMA transfer is definitely stopped before proceeding to <4>.
<4> Set the INITn bit of the DCHCn register of the channel to be forcibly terminated to 1.
<5> Perform the following operations for value A read in step <2>. (Value B)
(i) Clear the bit of the channel to be forcibly terminated to 0
(ii) If the TCn of the DCHCn register and ENn bit of the DRST register of the channel that is not
terminated forcibly are 1 (AND makes 1), clear the bit of the channel to 0.
<6> Write value B in <5> to the DRST register.
<7> Enable interrupts (EI state).
Note Execute three times if the transfer target (transfer source or transfer destination) is the internal
RAM.
Caution Be sure to execute step <5> to prevent the ENn bit of the DRST register from being set
illegally for channels that are terminated normally during the period of steps <2> and
<3>.
Remark
n = 0 to 3
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CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER)
User's Manual U14492EJ5V0UD
Note
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