Forcible Interruption; Dma Transfer End - NEC UPD703116 User Manual

6.10 Forcible Interruption

DMA transfer can be forcibly interrupted by NMI input during DMA transfer.
At such a time, the DMAC clears the Enn bit of the DCHCn register of all channels to 0 and the DMA transfer
disabled state is entered. An NMI request can then be acknowledged after the DMA transfer executed during NMI
input is terminated (n = 0 to 3).
If DMA transfer has been forcibly interrupted, perform forcible termination of the DMA using the INITn bit of the
DCHCn register and then initialize.

6.11 DMA Transfer End

When DMA transfer ends and the TCn bit of the DCHCn register is set to 1, a DMA transfer end interrupt
(INTDMAn) is issued to the interrupt controller (INTC) (n = 0 to 3).
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CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER)
User's Manual U14492EJ5V0UD