Idle Mode - NEC UPD703116 User Manual

8.5.4 IDLE mode

(1) Setting and operation status
In IDLE mode, the clock generator (oscillator and PLL synthesizer) continues to operate, but the supply of
internal system clocks is stopped which causes the overall system to stop.
When IDLE mode is released, the system can be switched to normal operation mode quickly because the
oscillator's oscillation stabilization time or the PLL lockup time need not be secured.
The system is switched to IDLE mode by setting the PSC or PSMR register using a store instruction (ST or
SST instruction) or a bit manipulation instruction (SET1, CLR1, or NOT1 instruction) (see 8.5.2 Control
registers).
In IDLE mode, program execution is stopped, and the contents of all registers, internal RAM, and ports are
maintained in the state they were in immediately before execution stopped.
peripheral I/O units (excluding ports) also is stopped.
Table 8-4 shows the status of each hardware unit in IDLE mode.
Clock generator
Internal system clock
CPU
Ports
On-chip peripheral I/O (excluding ports)
Internal data
AD0 to AD15
A16 to A23
RD
UWR, LWR
CS0 to CS7
HLDAK
HLDRQ
WAIT
ASTB
CLKOUT
Note NBD cannot be used in IDLE mode.
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CHAPTER 8 CLOCK GENERATION FUNCTION
Table 8-4. Operation Status in IDLE Mode
Function
User's Manual U14492EJ5V0UD
Operation Status
Operating
Stopped
Stopped
Maintained
Stopped (CSI0 and CSI1 are operable in slave mode)
All internal data such as CPU registers, statuses, data,
and the contents of internal RAM are maintained in the
state they were in immediately before IDLE mode began.
High impedance
High-level output
High impedance
Input (no sampling)
High-level output
Low-level output
The operation of on-chip
Note