Page 1 User’s Manual m m m m m PD780228 Subseries 8-bit Single-chip Microcontroller m PD780226 m PD780228 m PD78F0228 Document No. U12012EJ2V0UM00 (2nd edition) Date Published June 1997 N Printed in Japan © 1997 Printed in Japan...
Page 2 [MEMO]...
Page 3: Notes For Cmos Devices
Reset operation must be executed immediately after power-on for devices having reset function. FIP and IEBus are trademarks of NEC Corporation. MS-DOS and Windows are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries.
Page 4 The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products may be prohibited without governmental license. To export or re-export some or all of these products from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
Page 5: Major Revisions In This Edition
Major Revisions in This Edition Page Description Change of m PD780226 and 780228 from “under development” to “developed” Throughout p.16 2.3 I/O Circuits of Pins and Connections of Unused Pins Change of I/O circuit types of ports 7, 8, 9, and 10 of mask ROM model as follows: Ports 7, 8, and 9: type 15-D to type 15-F Port 10 : type 14-D to type 14-F...
Page 6: Regional Information
Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: •...
Page 7 PREFACE This manual has been prepared for user engineers who understand the functions of the m PD780228 Readers subseries and design and develop its application systems and programs. Purpose This manual is intended for the users to understand the functions described in the Organization section below.
Page 8 Legend Data representation weight : High digits on the left and low digits on the right Active low representations : xxx (top bar over pin or signal name) Note : Description of Note in the text. Caution : Information requiring particular attention Remark : Additional explanatory material Numeral representations...
Page 9 • Documents related to development tools (User’s Manual) Document Name Document Number English Japanese RA78K Series Assembler Package Operation EEU-1399 EEU-809 Language EEU-1404 EEU-815 RA78K Series Structured Assembler Preprocessor EEU-1402 EEU-817 RA78K0 Assembler Package Operation U11802E U11802J Assembly Language U11801E U11801J Structured Assembly U11789E...
Page 10 Document Name Document Number English Japanese IC Package Manual C10943X Semiconductor Device Mounting Technology Manual C10535E C10535J Quality Grades on NEC Semiconductor Devices C11531E C11531J NEC Semiconductor Device Reliability/Quality Control System C10983E C10983J Electrostatic Discharge (ESD) Test — MEM-539 Guide to Quality Assurance for Semiconductor Devices...
Page 11: Table Of Contents
TABLE OF CONTENTS CHAPTER 1 GENERAL .......................... 1 Features ..........................1 Application Fields ......................... 1 Ordering Information ......................1 Pin Configuration (Top View) ....................2 78K/0 Series Expansion ....................... 4 Block Diagram ........................6 Functional Outline ......................... 7 Mask Option ........................... 8 CHAPTER 2 PIN FUNCTIONS ........................
Page 12 Processor Registers ......................28 3.2.1 Control registers ........................28 3.2.2 General registers ........................31 3.2.3 Special function registers (SFR: Special Function Register) ..........32 Addressing of Instruction Address .................. 35 3.3.1 Relative addressing ........................35 3.3.2 Immediate addressing ....................... 36 3.3.3 Table indirect addressing ......................
Page 13 Clock Generator Operations ....................74 Changing CPU Clock ......................75 5.6.1 Time required to change CPU clock ..................75 5.6.2 CPU clock changing procedure ....................76 CHAPTER 6 8-BIT REMOTE CONTROL TIMER ................. 77 Function of 8-Bit Remote Control Timer ................77 Configuration of 8-Bit Remote Control Timer ..............
Page 14 CHAPTER 11 FIP CONTROLLER/DRIVER ..................127 11.1 Function of FIP Controller/Driver ..................127 11.2 Configuration of FIP Controller/Driver ................128 11.3 Registers Controlling FIP Controller/Driver..............129 11.3.1 Control registers ........................129 11.3.2 One display period and blanking width .................. 133 11.4 Display Data Memory ......................
Page 15 16.2 Operation List ........................185 16.3 Instructions Listed by Addressing Type ................ 192 APPENDIX A DIFFERENCES BETWEEN m m m m m PD78044H, 780228, AND 780208 SUBSERIES ..197 APPENDIX B DEVELOPMENT TOOLS .................... 199 Language Processing Software ..................201 Flash Memory Writing Tools ....................
Page 16 LIST OF FIGURES (1/3) Figure No. Title Page Pin Input/Output Circuit List ........................17 Memory Map ( m PD780226) ........................19 Memory Map ( m PD780228) ........................20 Memory Map ( m PD78F0228) ........................21 Addressing of Data Memory ( m PD780226) .................... 25 Addressing of Data Memory ( m PD780228) ....................
Page 17: List Of Figures
LIST OF FIGURES (2/3) Figure No. Title Page Timing of Interval Timer Operation ......................90 Timing of External Event Counter Operation (with rising edge specified) ..........92 PWM Output Operation Timing ....................... 95 Operation Timing When CR5n Is Changed .................... 96 16-Bit Resolution Cascade Mode ......................
Page 18 LIST OF FIGURES (3/3) Figure No. Title Page 12-1 Basic Configuration of Interrupt Function ..................... 145 12-2 Interrupt Request Flag Register Format ....................148 12-3 Interrupt Mask Flag Register Format ....................149 12-4 Priority Specify Flag Register Format ....................150 12-5 External Interrupt Rising Edge Enable Register Format ..............
Page 19 LIST OF TABLES (1/2) Table No. Title Page Mask Options of Mask ROM Models ......................8 I/O Circuit Type of Each Pin ........................16 Internal ROM Capacity ..........................22 Vector Table .............................. 22 Special Function Registers ........................33 Port Function ............................50 Port Configuration ............................
Page 20: List Of Tables
LIST OF TABLES (2/2) Table No. Title Page 14-1 Hardware Status after Reset ......................... 173 Differences between m PD78F0228 and Mask ROM Models ............... 175 15-1 15-2 Set Value of Memory Size Select Register ................... 176 15-3 Communication Modes .......................... 178 15-4 Major Functions of Flash Memory Programming .................
Page 21: Chapter 1 General
CHAPTER 1 GENERAL CHAPTER 1 GENERAL 1.1 Features • High-capacity ROM and RAM Item Program Memory Data Memory Mask ROM Flash memory Internal high- Internal display Part Number speed RAM expansion RAM m PD780226 48K bytes — 1024 bytes 512 bytes 96 bytes m PD780228 60K bytes...
Page 22: Pin Configuration (Top View)
CHAPTER 1 GENERAL 1.4 Pin Configuration (Top View) • 100-pin plastic QFP (14 ¥ ¥ ¥ ¥ ¥ 20 mm) m m m m m PD780226GF-xxx-3BA, 780228GF-xxx-3BA, 78F0228GF-3BA Note 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 LOAD P74/FIP20 P75/FIP21...
Page 23 CHAPTER 1 GENERAL ANI0-ANI7 : Analog Input P90-P97 : Port9 : Analog Power Supply P100-P107 : Port10 : Analog Ground RESET : Reset FIP0-FIP47 : Fluorescent Indicator Panel : Serial Clock : Internally Connected : Serial Input INTP0, INTP1 : Interrupt from Peripherals : Serial Output P00, P01 : Port0...
Page 24: Series Expansion
CHAPTER 1 GENERAL 1.5 78K/0 Series Expansion The following shows the 78K/0 Series products development. Subseries name are shown inside frames. Products in mass production Products under development Y subseries products are compatible with I C bus. Control µ µ µ...
Page 25 CHAPTER 1 GENERAL The following lists the main functional differences between subseries products. Function Timer 8-bit 10-bit 8-bit MIN. External Serial Interface Capacity 8-bit 16-bit Watch WDT A/D A/D D/A Value Expansion Subseries Name Control m PD78075B 32K-40K 4ch 1ch 1ch 1ch 8ch –...
Page 26: Block Diagram
CHAPTER 1 GENERAL 1.6 Block Diagram PORT0 P00, P01 8-bit REMOTE CONTROLLER TI1/P23 PORT1 P10-P17 TIMER (TM1) P20-P25 PORT2 8-bit PWM TIMER TIO50/P24 PORT4 P40-P47 (TM50) 78K/0 FLASH PORT5 P50-P57 CPU CORE MEMORY 8-bit PWM TIMER TIO51/P25 (TM51) PORT6 P60-P67 WATCHDOG TIMER PORT7 P70-P77...
Page 27: Functional Outline
CHAPTER 1 GENERAL 1.7 Functional Outline m PD780226 m PD780228 m PD78F0228 Part Number Item Internal memory Mask ROM Flash memory Note 48K bytes 60K bytes 60K bytes High-speed RAM 1024 bytes Expansion RAM 512 bytes FIP display RAM 96 bytes General-purpose register 8 bits ¥...
Page 28: Mask Option
CHAPTER 1 GENERAL 1.8 Mask Option The mask ROM models ( m PD780226 and 780228) have mask options. By specifying the mask options when placing an order for these models, the pull-up and pull-down resistors shown in Table 1-1 can be connected. If these mask options are used when pull-up and pull-down resistors are necessary, the number of components can be decreased and the mounting area can be reduced.
Page 29: Chapter 2 Pin Functions
CHAPTER 2 PIN FUNCTIONS CHAPTER 2 PIN FUNCTIONS 2.1 Pin Function List (1) Port pins (1/2) Pin Name Function At Reset Shared with: Port 0. Input INTP0 2-bit I/O port. Can be set in input or output mode in 1-bit units. INTP1 Internal pull-up resistor can be used via software when this port is used as input port.
Page 30 CHAPTER 2 PIN FUNCTIONS (1) Port pins (2/2) Pin Name Function At Reset Shared with: P80-P87 Port 8. Input FIP24-FIP31 P-ch open-drain 8-bit high-voltage I/O port. Can be set in input or output mode in 1-bit units. Internal pull-down resistor can be used by mask option in 1-bit units (mask ROM models only).
Page 31 CHAPTER 2 PIN FUNCTIONS (2) Pins other than port pins Pin Name Function At Reset Shared with: INTP0 Input Valid edge (rising, falling, or both rising and falling) can be specified. Input INTP1 External interrupt request input. Serial clock input/output of serial interface. Input Output Serial data output of serial interface.
Page 32: Pin Functions
CHAPTER 2 PIN FUNCTIONS 2.2 Pin Functions 2.2.1 P00 and P01 (Port 0) P00 and P01 are used as a 2-bit I/O port. These pins also have external interrupt request input functions in addition to the I/O port function. Port 0 can be set in the following operation modes in 1-bit units. (1) Port mode P00 and P01 function as a 2-bit I/O port in this mode.
Page 33: P40 Through P47 (Port 4)
CHAPTER 2 PIN FUNCTIONS (c) TI1 Timer input pin of the 8-bit remote control timer. (d) TIO50 and TIO51 Capture trigger input pin of the 8-bit PWM timers and timer output pin. 2.2.4 P40 through P47 (Port 4) P40 through 47 constitute an 8-bit I/O port. This port can be set in the input or output mode in 1-bit units by using the port mode register 4 (PM4).
Page 34: P90 Through P97 (Port 9)
CHAPTER 2 PIN FUNCTIONS 2.2.9 P90 through P97 (Port 9) P90 through P97 constitute an 8-bit I/O port. These pins are also used as FIP controller/driver output pins. The following operation modes can be specified in 1-bit units. (1) Port mode P90 through P97 function as an 8-bit I/O port in this mode.
Page 35: Vdd0 Through Vdd2
CHAPTER 2 PIN FUNCTIONS 2.2.17 V through V supplies a positive voltage to the ports. supplies a positive voltage to the internal function blocks other than the ports, analog block, and FIP controller/ driver. supplies a positive voltage to the FIP controller/driver. 2.2.18 V and V is the ground pin for the ports.
Page 36: I/O Circuits Of Pins And Connections Of Unused Pins
CHAPTER 2 PIN FUNCTIONS 2.3 I/O Circuits of Pins and Connections of Unused Pins Table 2-1 shows the I/O circuit types of the respective pins, and the recommended connections of each pin when it is not used. For the configuration of each type of the I/O circuit, refer to Figure 2-1. Table 2-1.
Page 37 CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin Input/Output Circuit List (1/2) Type 2 Type 9 Comparator P-ch N-ch – (Threshold voltage) Schmitt-Triggered Input with Hysteresis Characteristics input enable Type 5-H Type 13-J Mask Pull-up Option P-ch enable IN/OUT Data N-ch Output disable Data P-ch...
Page 38 CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin Input/Output Circuit List (2/2) Type 15-F Type 14-C P-ch P-ch Data IN/OUT P-ch P-ch N-ch data N-ch Mask Option N-ch LOAD LOAD Type 14-F Type 15-E P-ch P-ch data IN/OUT P-ch P-ch Data N-ch Mask Option...
Page 39: Chapter 3 Cpu Architecture
CHAPTER 3 CPU ARCHITECTURE CHAPTER 3 CPU ARCHITECTURE 3.1 Memory Space Each model in the m PD780228 subseries can access a memory space of 64K bytes. Figures 3-1 through 3-3 show the memory map. Figure 3-1. Memory Map ( m m m m m PD780226) F F F F H Special function registers (SFR) 256 ×...
Page 40 CHAPTER 3 CPU ARCHITECTURE Figure 3-2. Memory Map ( m m m m m PD780228) F F F F H Special function registers (SFR) 256 × 8 bits F F 0 0 H F E F F H General-purpose registers 32 ×...
Page 41 CHAPTER 3 CPU ARCHITECTURE Figure 3-3. Memory Map ( m m m m m PD78F0228) F F F F H Special function registers (SFR) 256 × 8 bits F F 0 0 H F E F F H General-purpose registers 32 ×...
Page 42: Internal Program Memory Space
CHAPTER 3 CPU ARCHITECTURE 3.1.1 Internal program memory space The internal program memory space stores programs and table data. Usually, this space is accessed by program counter (PC). Each model in the m PD780228 subseries has an internal ROM (or flash memory) of the following capacity. Table 3-1.
Page 43: Internal Data Memory Space
CHAPTER 3 CPU ARCHITECTURE 3.1.2 Internal data memory space The m PD780228 subseries has the following RAM. (1) Internal high-speed RAM This RAM consists of addresses FB00H through FEFFH, or 1024 ¥ 8 bits. Of these addresses, FEE0H through FEFFH constitute a 32-byte area to which four banks of general-purpose registers, with each bank consisting of eight 8-bit registers, are allocated.
Page 44: Data Memory Addressing
CHAPTER 3 CPU ARCHITECTURE 3.1.4 Data memory addressing Specifying the address of the instruction to be executed next, or specifying an address of the register or memory to be manipulated when an instruction is executed is called addressing. The address of the instruction to be executed next is addressed by the program counter (PC) (for details, refer to 3.3 Addressing of Instruction Address).
Page 45 CHAPTER 3 CPU ARCHITECTURE Figure 3-4. Addressing of Data Memory ( m m m m m PD780226) F F F F H Special function registers (SFR) SFR addressing 256 × 8 bits F F 2 0 H F F 1 F H F F 0 0 H F E F F H General-purpose registers...
Page 46 CHAPTER 3 CPU ARCHITECTURE Figure 3-5. Addressing of Data Memory ( m m m m m PD780228) F F F F H Special function registers (SFR) SFR addressing 256 × 8 bits F F 2 0 H F F 1 F H F F 0 0 H F E F F H General-purpose registers...
Page 47 CHAPTER 3 CPU ARCHITECTURE Figure 3-6. Addressing of Data Memory ( m m m m m PD78F0228) F F F F H Special function registers (SFR) SFR addressing 256 × 8 bits F F 2 0 H F F 1 F H F F 0 0 H F E F F H General-purpose registers...
Page 48: Processor Registers
CHAPTER 3 CPU ARCHITECTURE 3.2 Processor Registers The m PD780228 subseries units incorporate the following processor registers. 3.2.1 Control registers The control registers control the program sequence, statuses and stack memory. A program counter (PC), a program status word (PSW) and a stack pointer (SP) are control registers. (1) Program counter (PC) The program counter is a 16-bit register which holds the address information of the next program to be executed.
Page 49 CHAPTER 3 CPU ARCHITECTURE (c) Register bank select flags (RBS0 and RBS1) These are 2-bit flags to select one of the four register banks. In these flags, the 2-bit information which indicates the register bank selected by SEL RBn instruction execution is stored.
Page 50 CHAPTER 3 CPU ARCHITECTURE Figure 3-10. Data to be Saved to Stack Memory Interrupt and BRK Instruction CALL, CALLF, and PUSH rp Instruction CALLT Instruction SP – 3 SP – 2 SP – 2 SP – 3 PC7 to PC0 Register Pair SP –...
Page 51: General Registers
CHAPTER 3 CPU ARCHITECTURE 3.2.2 General registers A general register is mapped at particular addresses (FEE0H to FEFFH) of the data memory. It consists of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L, and H). Each register can also be used as an 8-bit register.
Page 52: Special Function Registers (Sfr: Special Function Register)
CHAPTER 3 CPU ARCHITECTURE 3.2.3 Special function registers (SFR: Special Function Register) Unlike a general register, each special function register has special functions. It is allocated in the FF00H to FFFFH area. The special function register can be manipulated, like the general register, with the operation, transfer and bit manipulation instructions.
Page 53 CHAPTER 3 CPU ARCHITECTURE Table 3-3. Special Function Registers (1/2) Address Special Function Register (SFR) Name Symbol R/W Manipulatable Bit Units At Reset 1 bit 8 bits 16 bits FF00H Port 0 — FF01H Port 1 — FF02H Port 2 —...
Page 54 CHAPTER 3 CPU ARCHITECTURE Table 3-3. Special Function Registers (2/2) Address Special Function Register (SFR) Name Symbol R/W Manipulatable Bit Units At Reset 1 bit 8 bits 16 bits FF90H Display mode register 0 DSPM0 — FF91H Display mode register 1 DSPM1 —...
Page 55: Addressing Of Instruction Address
CHAPTER 3 CPU ARCHITECTURE 3.3 Addressing of Instruction Address An instruction address is determined by program counter (PC) contents. Program counter (PC) contents are normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed.
Page 56: Immediate Addressing
CHAPTER 3 CPU ARCHITECTURE 3.3.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16 or BR !addr16 or CALLF !addr11 instruction is executed. The CALL !addr16 and BR !addr16 instruction can branch in the entire memory space.
Page 57 CHAPTER 3 CPU ARCHITECTURE 3.3.3 Table indirect addressing [Function] Table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the immediate data of an operation code are transferred to the program counter (PC) and branched. Before the CALLT [addr5] instruction is executed, table indirect addressing is performed.
Page 58: Register Addressing
CHAPTER 3 CPU ARCHITECTURE 3.3.4 Register addressing [Function] Register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC) and branched. This function is carried out when the BR AX instruction is executed. [Illustration]...
Page 59: Addressing Of Operand Address
CHAPTER 3 CPU ARCHITECTURE 3.4 Addressing of Operand Address The following various methods are available to specify the register and memory (addressing) which undergo manipulation during instruction execution. 3.4.1 Implied addressing [Function] The register which functions as an accumulator (A and AX) in the general register is automatically (tacitly) addressed.
Page 60: Register Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.2 Register addressing [Function] This addressing accesses a general register as an operand. The general register accessed is specified by the register bank select flags (RBS0 and RBS1) and register specify code (Rn or RPn) in an instruction code. Register addressing is carried out when an instruction with the following operand format is executed.
Page 61: Direct Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.3 Direct addressing [Function] This addressing directly addresses the memory indicated by the immediate data in an instruction word. [Operand format] Identifier Description addr16 Label or 16-bit immediate data [Description example] MOV A, !0FE00H; when setting !addr16 to FE00H Operation code OP code [Illustration]...
Page 62: Short Direct Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.4 Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. The fixed space to which this addressing is applied is the 256-byte space of addresses FE20H to FF1FH. Addresses FE20H to FEFFH constitute a part of the SFR area, and the internal high-speed RAM is mapped to this area.
Page 63 CHAPTER 3 CPU ARCHITECTURE [Description example] MOV 0FE30H, #50H; when setting saddr to FE30H and immediate data to 50H OP code Operation code 30H (saddr to offset) 50H (immediate data) [Illustration] OP code saddr-offset Short Direct Memory α Effective address When 8-bit immediate data is 20H to FFH, α...
Page 64: Special Function Register (Sfr) Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.5 Special function register (SFR) addressing [Function] The memory-mapped special function register (SFR) is addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the SFR mapped at FF00H to FF1FH can be accessed with short direct addressing.
Page 65: Register Indirect Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.6 Register indirect addressing [Function] The addressing addresses the memory with the contents of a register pair specified as an operand. The register pair to be accessed is specified by the register bank select flags (RBS0 and RBS1) and register pair specify code in an instruction code.
Page 66: Based Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.7 Based addressing [Function] This addressing addresses the memory by adding 8-bit immediate data to the contents of the HL register pair which is used as a base register and by using the result of the addition. The HL register pair to be accessed is in the register bank specified by the register bank select flags (RBS0 and RBS1).
Page 67: Based Indexed Addressing
CHAPTER 3 CPU ARCHITECTURE 3.4.8 Based indexed addressing [Function] This addressing addresses the memory by adding the contents of the HL register pair, which is used as a base register, to the contents of the B or C register specified in the instruction word, and by using the result of the addition.
Page 68 CHAPTER 3 CPU ARCHITECTURE [MEMO]...
Page 69: Chapter 4 Port Functions
CHAPTER 4 PORT FUNCTIONS CHAPTER 4 PORT FUNCTIONS 4.1 Port Functions The m PD780228 subseries incorporates eight input ports, eight output ports and 56 input/output ports. Figure 4- 1 shows the port configuration. Every port is capable of 1-bit and 8-bit manipulations and can carry out considerably varied control operations.
Page 70 CHAPTER 4 PORT FUNCTIONS Table 4-1. Port Function Pin Name Function Shared with: Port 0. INTP0 2-bit I/O port. Can be set in input or output mode in 1-bit units. INTP1 Internal pull-up resistor can be used via software when this port is used as input port. P10-P17 Port 1.
Page 71: Port Configuration
CHAPTER 4 PORT FUNCTIONS 4.2 Port Configuration A port consists of the following hardware. Table 4-2. Port Configuration Item Configuration Control register Port mode register (PMm: m = 0, 2, 4-6) Pull-up resistor option register (PUn: n = 0, 2, 4) Port Total: 72 (8 inputs, 8 outputs, 56 inputs/outputs) Pull-up resistor...
Page 72 CHAPTER 4 PORT FUNCTIONS Figure 4-2. P00 and P01 Block Diagram PU00, PU01 P-ch Selector PORT P00/INTP0, Output Latch P01/INTP1 (P00 and P01) PM00 and PM01 : Pull-up resistor option register : Port mode register : Port 0 read signal WR : Port 0 write signal...
Page 73: Port 1
CHAPTER 4 PORT FUNCTIONS 4.2.2 Port 1 Port 1 is an 8-bit input only port. A/D converter analog input is provided as an alternate function. Figure 4-3 shows a block diagram of port 1. Figure 4-3. P10 to P17 Block Diagram P10/ANI0 to P17/ANI7 : Port 1 read signal...
Page 74: Port 2
CHAPTER 4 PORT FUNCTIONS 4.2.3 Port 2 Port 2 is a 6-bit input/output port with output latch. P20 to P25 pins can specify the input mode/output mode in 1-bit units with the port mode register 2 (PM2). When P20 to P25 pins are used as input ports, an on-chip pull-up resistor can be connected to them in 1-bit units with a pull-up resistor option register 2 (PU2).
Page 75 CHAPTER 4 PORT FUNCTIONS Figure 4-5. P21 to P25 Block Diagram PU21-PU25 P-ch Selector PORT P21/SO, Output Latch P22/SI, (P21-P25) P23/TI1, P24/TIO50, P25/TIO51 PM21-PM25 Alternate Function : Pull-up resistor option register : Port mode register : Port 2 read signal WR : Port 2 write signal...
Page 76: Port 4
CHAPTER 4 PORT FUNCTIONS 4.2.4 Port 4 Port 4 is an 8-bit input/output port with output latch. P40 to P47 pins can specify the input mode/output mode in 1-bit units with the port mode register 4 (PM4). When P40 to P47 pins are used as input ports, an on-chip pull-up resistor can be connected to them in 1-bit units with a pull-up resistor option register 4 (PU4).
Page 77: Port 5
CHAPTER 4 PORT FUNCTIONS 4.2.5 Port 5 Port 5 is an 8-bit input/output port with output latch. Pins from 50 to 57 can specify I/O mode in 1-bit units with the port mode register 5 (PM5). On-chip pull-up resistors can be connected in 1-bit units with the mask option in case of mask ROM model.
Page 78: Port 6
CHAPTER 4 PORT FUNCTIONS 4.2.6 Port 6 Port 6 is an 8-bit input/output port with output latch. Pins from 60 to 67 can specify I/O mode in 1-bit units with the port mode register 6 (PM6). On-chip pull-up resistors can be connected in 1-bit units with the mask option in case of mask ROM model.
Page 79: Port 7
CHAPTER 4 PORT FUNCTIONS 4.2.7 Port 7 Port 7 is an 8-bit input/output port with output latch. When using this port as an output port, the value assigned to the output latch (P70 through P77) is output. When it is used as an input port, set the output latch (P70 through P77) to “0”, and read the port read (PLR70 through PLR77).
Page 80: Port 8
CHAPTER 4 PORT FUNCTIONS 4.2.8 Port 8 Port 8 is an 8-bit input/output port with output latch. When using this port as an output port, the value assigned to the output latch (P80 through P87) is output. When it is used as an input port, set the output latch (P80 through P87) to “0”, and read the port read (PLR80 through PLR87).
Page 81: Port 9
CHAPTER 4 PORT FUNCTIONS 4.2.9 Port 9 Port 9 is an 8-bit input/output port with output latch. When using this port as an output port, the value assigned to the output latch (P90 through P97) is output. When it is used as an input port, set the output latch (P90 through P97) to “0”, and read the port read (PLR90 through PLR97).
Page 82: Port 10
CHAPTER 4 PORT FUNCTIONS 4.2.10 Port 10 Port 10 is an 8-bit output only port. On-chip pull-down resistors can be connected in 1-bit units with the mask option in case of mask ROM model. The m PD78F0228 has no pull-down resistor. In addition, FIP controller/driver segment/digit output is provided as an alternate function.
Page 83: Port Function Control Registers
CHAPTER 4 PORT FUNCTIONS 4.3 Port Function Control Registers The following two types of registers control the ports. • Port mode registers (PM0, PM2, PM4 to PM6) • Pull-up resistor option register (PU0, PU2, PU4) (1) Port mode registers (PM0, PM2, PM4 to PM6) These registers are used to set port input/output in 1-bit units.
Page 84 CHAPTER 4 PORT FUNCTIONS Figure 4-13. Port Mode Register Format Symbol Address At Reset PM01 PM00 FF20H PM25 PM24 PM23 PM22 PM21 PM20 FF22H PM46 PM45 PM44 PM43 PM42 PM41 PM47 PM40 FF24H PM56 PM55 PM54 PM53 PM52 PM51 PM50 FF25H PM57 FF26H...
Page 85 CHAPTER 4 PORT FUNCTIONS (2) Pull-up resistor option registers (PU0, PU2, PU4) This register is used to set whether or not to use an internal pull-up resistor of pins at ports 0, 2, 4 in 1-bit units. A pull-up resistor is internally used at bits which are set to the input mode at a bit where on-chip pull-up resistor use has been specified with PU0, PU2, and PU4.
Page 86: Port Function Operations
CHAPTER 4 PORT FUNCTIONS 4.4 Port Function Operations Port operations differ depending on whether the input or output mode is set, as shown below. 4.4.1 Writing to input/output port (1) Output mode A value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin.
Page 87: Selecting Mask Option
CHAPTER 4 PORT FUNCTIONS 4.5 Selecting Mask Option The mask ROM models have the following mask options. The m PD78F0228 does not have mask options. Table 4-4. Comparison between Mask Options of Mask ROM Models and m m m m m PD78F0228 m PD78F0228 Pin Name Mask Option of Mask ROM Model...
Page 88 CHAPTER 4 PORT FUNCTIONS [MEMO]...
Page 89: Chapter 5 Clock Generator
CHAPTER 5 CLOCK GENERATOR CHAPTER 5 CLOCK GENERATOR 5.1 Clock Generator Functions The clock generator generates clock to be supplied to the CPU and peripheral hardware. The following type of system clock oscillators is available. • Main system clock oscillator This circuit oscillates at frequencies of 5.0 MHz.
Page 90: Register Controlling Clock Generation Circuit
CHAPTER 5 CLOCK GENERATOR 5.3 Register Controlling Clock Generation Circuit The clock generation circuit is controlled by the processor clock control register (PCC). • Processor clock control register (PCC) This register selects a CPU clock and selects a division ratio. PCC is set by using a 1-bit or 8-bit memory manipulation instruction.
Page 91: System Clock Oscillator
CHAPTER 5 CLOCK GENERATOR 5.4 System Clock Oscillator 5.4.1 Main system clock oscillator The main system clock oscillator oscillates with a crystal resonator or a ceramic resonator (5.0 MHz TYP.) connected to the X1 and X2 pins. External clocks can be input to the main system clock oscillator. In this case, input a clock signal to the X1 pin and an antiphase clock signal to the X2 pin.
Page 92 CHAPTER 5 CLOCK GENERATOR Figure 5-4. Examples of Resonator with Bad Connection (1/2) (a) Too long wiring of connected circuit (b) Crossed signal lines PORTn (n = 0-2, 4-10) (c) High alternating current close to (d) Current flowing through ground line signal lines of oscillator circuit (potentials at points A, B, and C change)
Page 93: Divider
CHAPTER 5 CLOCK GENERATOR Figure 5-4. Examples of Resonator with Bad Connection (2/2) (e) Signal extracted 5.4.2 Divider The divider divides the main system clock oscillator output (f ) and generates various clocks.
Page 94: Clock Generator Operations
CHAPTER 5 CLOCK GENERATOR 5.5 Clock Generator Operations The clock generator generates the following various types of clocks and controls the CPU operating mode including the standby mode. • Main system clock f • CPU clock f • Clock to peripheral hardware The function and operation of the clock generator circuit are determined by the processor clock control register (PCC) as follows: (a) Upon generation of RESET signal, the lowest speed mode of the main system clock (6.4 m s when operated...
Page 95: Changing Cpu Clock
CHAPTER 5 CLOCK GENERATOR 5.6 Changing CPU Clock 5.6.1 Time required to change CPU clock The CPU clock can be changed by using bits 0 through 2 (PCC0 through PCC2) of the processor clock control register (PCC). Actually, the clock is not changed immediately after PCC has been rewritten, and the CPU operates with the old clock until the specified number of instructions (refer to Table 5-3) has been executed after PCC was changed.
Page 96: Cpu Clock Changing Procedure
CHAPTER 5 CLOCK GENERATOR 5.6.2 CPU clock changing procedure The CPU clock is changed in the following procedure. Figure 5-5. Changing CPU Clock RESET CPU clock Slowest Fastest operation operation Wait (13.1 ms at 5.0 MHz) Internal reset operation (1) The CPU is reset if the RESET pin is made low after power application. The reset is cleared and the main system clock starts oscillating if the RESET pin is later made high.
Page 97: Chapter 6 8-Bit Remote Control Timer
CHAPTER 6 8-BIT REMOTE CONTROL TIMER CHAPTER 6 8-BIT REMOTE CONTROL TIMER 6.1 Function of 8-Bit Remote Control Timer The 8-bit remote control timer has a pulse width measurement function with a resolution of 8 bits. Pulse width is measured from a difference in count value when the valid edge has been detected while the timer operates in the free-running mode.
Page 98: Registers Controlling 8-Bit Remote Control Timer
CHAPTER 6 8-BIT REMOTE CONTROL TIMER 6.3 Registers Controlling 8-Bit Remote Control Timer The following three types of registers control the 8-bit remote control timer. • Timer mode control register 1 (TMC1) • 8-bit capture registers (CP10 and CP11) • 8-bit timer register (TM1) (1) Timer mode control register 1 (TMC1) This register enables or disables the operation of the 8-bit timer (TM1), sets the count clock, and detects overflow.
Page 99 CHAPTER 6 8-BIT REMOTE CONTROL TIMER (2) 8-bit capture registers (CP10 and CP11) These 8-bit registers capture the contents of the 8-bit timer (TM1). The capture operation is performed in synchronization with the valid edge input to the TI1 pin (capture trigger). The contents of CP10 are retained until the next rising edge of the TI1 pin is detected.
Page 100: Operation Of 8-Bit Remote Control Timer
CHAPTER 6 8-BIT REMOTE CONTROL TIMER 6.4 Operation of 8-Bit Remote Control Timer The 8-bit remote control timer operates as a pulse width measuring circuit. The width of a high-level or low-level external pulse input to the TI1 pin is measured by operating the 8-bit timer (TM1) in the free-running mode.
Page 101 CHAPTER 6 8-BIT REMOTE CONTROL TIMER Figure 6-3. Timing of Pulse Width Measurement (2/2) (2) Measure pulse width in synchronization with both rising and falling edges Count value of TM1 Capture Capture Capture Capture Count starts TCE = 1 INTTM10 INTTM11 CP10 CP11...
Page 102 CHAPTER 6 8-BIT REMOTE CONTROL TIMER [MEMO]...
Page 103: Chapter 7 8-Bit Pwm Timers
CHAPTER 7 8-BIT PWM TIMERS CHAPTER 7 8-BIT PWM TIMERS 7.1 Functions of 8-Bit PWM Timers The 8-bit PWM timers have the following two operation modes: • Mode in which only an 8-bit timer (TM5n: n = 0 or 1) is used (single mode) •...
Page 104: Configuration Of 8-Bit Pwm Timers
CHAPTER 7 8-BIT PWM TIMERS 7.2 Configuration of 8-Bit PWM Timers The 8-bit PWM timers consist of the following hardware: Table 7-1. Configuration of 8-Bit PWM Timers Item Configuration Timer register 8-bit counter 5n (TM5n) Register 8-bit compare register 5n (CR5n) Timer output TIO5n Control registers...
Page 105 CHAPTER 7 8-BIT PWM TIMERS (1) 8-bit counter 5n (TM5n: n = 0 or 1) TM5n is an 8-bit read-only register that counts the count pulse. The value of this counter is incremented in synchronization with the rising edge of the count clock. When the count value is read during operation, input of the count clock is temporarily stopped, and the count value at that point is read.
Page 106: Registers Controlling 8-Bit Pwm Timers
CHAPTER 7 8-BIT PWM TIMERS 7.3 Registers Controlling 8-Bit PWM Timers The following two types of registers control the 8-bit PWM timers. • Timer clock select register 5n (TCL5n: n = 0 or 1) • 8-bit timer mode control register 5n (TMC5n: n = 0 or 1) (1) Timer clock select register 5n (TCL5n: n = 0 or 1) This register sets the count clock of the 8-bit counter 5n (TM5n: n = 0 or 1).
Page 107 CHAPTER 7 8-BIT PWM TIMERS (2) 8-bit timer mode control register 5n (TMC5n: n = 0 or 1) TMC5n sets has the following six functions: <1> Controls count operation of 8-bit counter 5n (TM5n: n = 0 or 1) <2> Selects operation mode of 8-bit counter 5n (TM5n: n = 0 or 1) <3>...
Page 108 CHAPTER 7 8-BIT PWM TIMERS Figure 7-3. Format of 8-Bit Timer Control Register 5n Symbol < 7 > < 3 > < 2 > Address At Reset TMC5n TCE5n TMC5n6 TMC5n4 LVS5n LVR5n TMC5n1 TOE5n FF70H(TMC50), FF78H(TMC51) TCE5n Controls counting by TM5n Clears counter to 0 and disables counting (prescaler disabled) Starts counting TMC5n6...
Page 109: Operations Of 8-Bit Pwm Timers
CHAPTER 7 8-BIT PWM TIMERS 7.4 Operations of 8-Bit PWM Timers 7.4.1 Operation as interval timer (8-bit operation) An 8-bit PWM timer operates as an interval timer that generates an interrupt request at intervals specified by the count value set to the 8-bit compare register 5n (CR5n) in advance. When the count value of the 8-bit counter 5n (TM5n) coincides with the set value of CR5n, the value of TM5n is cleared to 0 and TM5n continues counting.
Page 110 CHAPTER 7 8-BIT PWM TIMERS Figure 7-4. Timing of Interval Timer Operation (1/3) (a) Basic operation Count clock TM5n count value Count starts Clear Clear CR5n TCE5n INTTM5n Interrupt request accepted Interrupt request accepted TIO5n Interval time Interval time Interval time Remarks 1.
Page 111 CHAPTER 7 8-BIT PWM TIMERS Figure 7-4. Timing of Interval Timer Operation (2/3) (c) When CR5n = FFH Count clock TM5n FEH FFH 00H CR5n TCE5n INTTM5n Interrupt request accepted Interrupt request accepted TIO5n Interval time n = 0 or 1 (d) Operation when CR5n is changed (M <...
Page 112: Operation As External Event Counter
CHAPTER 7 8-BIT PWM TIMERS Figure 7-4. Timing of Interval Timer Operation (3/3) (e) Operation when CR5n is changed (M > N) Count clock TM5n N–1 M–1 CR5n TCE5n INTTM5n TIO5n Change of CR5n n = 0 or 1 7.4.2 Operation as external event counter The external event counter counts the number of count clock pulses input to TIO5n from an external source.
Page 113: Square Wave (8-Bit Resolution) Output Operation
CHAPTER 7 8-BIT PWM TIMERS 7.4.3 Square wave (8-bit resolution) output operation A square wave of any frequency can be output at intervals specified by the value set in advance to the 8-bit compare register 5n (CR5n). If the bit 0 (TOE5n) of the 8-bit timer mode control register 5n (TMC5n) is set to 1, the output status of TIO5n is inverted at intervals specified by the count value set in advance to CR5n.
Page 114: 8-Bit Pwm Output Operation
CHAPTER 7 8-BIT PWM TIMERS 7.4.4 8-bit PWM output operation The PWM timer performs 8-bit PWM output operation when bit 6 of the 8-bit timer mode control register 5n (TMC5n) is set to “1”, and outputs a pulse with a duty factor determined by the value set to the 8-bit compare register 5n (CR5n) from the TIO5n pin.
Page 115 CHAPTER 7 8-BIT PWM TIMERS (a) Basic PWM output operation Figure 7-6. PWM Output Operation Timing (i) Basic operation (when active level = H) Count clock TM5n 00H 01H FFH 00H 01H 02H N N+1 FFH 00H 01H 02H CR5n TCE5n INTTM5n TIO5n...
Page 116 CHAPTER 7 8-BIT PWM TIMERS (b) Operation when CR5n is changed Figure 7-7. Operation Timing When CR5n Is Changed (i) If CR5n value is changed from N to M before overflow of TM5n Count clock TM5n N N+1 N+2 FFH 00H 01H M M+1 M+2 FFH 00H 01H 02H M M+1 M+2...
Page 117 CHAPTER 7 8-BIT PWM TIMERS (2) Cascade (16-bit timer) mode • Operation as interval timer (with 16-bit resolution) The two PWM timers can be used as a 16-bit timer/counter by setting bit 4 (TMC5n4) of the 8-bit timer mode control register 5n (TMC5n) to “1”. In this case, the 16-bit timer/counter operates as an interval timer that repeatedly generates an interrupt request at intervals specified by the count value set in advance to the 8-bit compare register 5n (CR5n).
Page 118 CHAPTER 7 8-BIT PWM TIMERS Figure 7-8 shows an example of the timing in the 16-bit resolution cascade mode. Figure 7-8. 16-Bit Resolution Cascade Mode Count clock TM50 N N+1 FFH 00H FFH 00H FFH 00H 01H N 00H 01H A 00H TM51 M–1 M...
Page 119: Notes On 8-Bit Pwm Timers
CHAPTER 7 8-BIT PWM TIMERS 7.5 Notes on 8-Bit PWM Timers (1) Error on starting timer The time until the coincidence signal is generated after the timer has been started includes an error of up to 1 clock, because the 8-bit counter n (TM5n: n = 0 or 1) is started in asynchronization with the count pulse. Figure 7-9.
Page 120 CHAPTER 7 8-BIT PWM TIMERS [MEMO]...
Page 121: Chapter 8 Watchdog Timer
CHAPTER 8 WATCHDOG TIMER CHAPTER 8 WATCHDOG TIMER 8.1 Function of Watchdog Timer The watchdog timer has the following functions: • Watchdog timer • Interval timer • Selection of oscillation stabilization time Caution Select whether the watchdog timer is used in the watchdog timer mode or interval timer mode, by using the watchdog timer mode register (WDTM).
Page 122: Configuration Of Watchdog Timer
CHAPTER 8 WATCHDOG TIMER 8.2 Configuration of Watchdog Timer The watchdog timer consists of the following hardware. Table 8-3. Configuration of Watchdog Timer Item Configuration Control register Oscillation stabilization time select register (OSTS) Watchdog timer clock select register (WDCS) Watchdog timer mode register (WDTM) Figure 8-1.
Page 123: Registers Controlling Watchdog Timer
CHAPTER 8 WATCHDOG TIMER 8.3 Registers Controlling Watchdog Timer The following three types of registers control the watchdog timer. • Oscillation stabilization time select register (OSTS) • Watchdog timer clock select register (WDCS) • Watchdog timer mode register (WDTM) (1) Oscillation stabilization time select register (OSTS) This register selects the oscillation stabilization time during which oscillation is stabilized after the RESET signal has been deasserted or the STOP mode has been released.
Page 124 CHAPTER 8 WATCHDOG TIMER (2) Watchdog timer clock select register (WDCS) This register selects the overflow time of the watchdog timer or interval timer. It is set by using an 8-bit manipulation instruction. The value of this register is initialized to 00H by RESET input. Figure 8-3.
Page 125 CHAPTER 8 WATCHDOG TIMER (3) Watchdog timer mode register (WDTM) This register selects the operation mode of the watchdog timer, and enables or disables the counting operation. It is set by using a 1-bit or 8-bit memory manipulation instruction. The value of this register is initialized to 00H by RESET input. Figure 8-4.
Page 126: Operation Of Watchdog Timer
CHAPTER 8 WATCHDOG TIMER 8.4 Operation of Watchdog Timer 8.4.1 Operation as watchdog timer The watchdog timer operates to detect a program hang-up when bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 1. The count clock of the watchdog timer (hang-up detection time interval) can be selected by bits 0 through 2 (WDCS0 through WDCS2) of the watchdog timer clock select register (WDCS).
Page 127: Operation As Interval Timer
CHAPTER 8 WATCHDOG TIMER 8.4.2 Operation as interval timer The watchdog timer operates as an interval timer that repeatedly generates an interrupt request at intervals specified by the count value set in advance if bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is cleared to 0.
Page 128 CHAPTER 8 WATCHDOG TIMER [MEMO]...
Page 129: Chapter 9 A/D Converter
CHAPTER 9 A/D CONVERTER CHAPTER 9 A/D CONVERTER 9.1 Function of A/D Converter The A/D converter converts analog input signals into digital values with a resolution of 8 bits. Eight analog input channels (ANI0 through ANI7) can be controlled. The A/D conversion operation can be started only by software. One of the analog input channels, ANI0 through ANI7, is selected for A/D conversion.
Page 130 CHAPTER 9 A/D CONVERTER Figure 9-1. A/D Converter Block Diagram ANI0 Sample & hold circuit ANI1 ANI2 Voltage comparator ANI3 ANI4 ANI5 ANI6 ANI7 Successive approximation register (SAR) Control INTAD circuit A/D conversion result register (ADCRH0) ADS03 ADS02 ADS01 ADS00 FR02 FR01 FR00 Analog input channel A/D converter mode...
Page 131 CHAPTER 9 A/D CONVERTER (4) Voltage comparator The voltage comparator compares the analog input signal with the output voltage of the series resistor string. (5) Series resistor string The series resistor string is connected between the AV and AV pins, and generates a voltage to be compared with the input analog signal.
Page 132: Registers Controlling A/D Converter
CHAPTER 9 A/D CONVERTER 9.3 Registers Controlling A/D Converter The following two types of registers control the A/D converter. • A/D converter mode register (ADM0) • Analog input channel specification register (ADS0) (1) A/D converter mode register (ADM0) This register specifies the conversion time of the input analog signal to be converted, and starts or stops the conversion operation.
Page 133 CHAPTER 9 A/D CONVERTER (2) Analog input channel specification register (ADS0) This register specifies a port that inputs the analog voltage to be converted. It is set by using a 1-bit or 8-bit memory manipulation instruction. The value of this register is initialized to 00H by RESET input. Figure 9-3.
Page 134: Operation Of A/D Converter
CHAPTER 9 A/D CONVERTER 9.4 Operation of A/D Converter 9.4.1 Basic operation of A/D converter (1) Select one channel for A/D conversion by using the analog input channel specification register (ADS0). (2) The sample & hold circuit samples the voltage input to the selected analog input channel. (3) The sample &...
Page 135 CHAPTER 9 A/D CONVERTER Figure 9-4. Basic Operation of A/D Converter Conversion time Sampling time Operation of Sampling A/D conversion A/D converter Conversion Undefined result Conversion ADCRH0 result INTAD The A/D conversion operation is performed successively until bit 7 (CS0) of the A/D converter mode register (ADM0) is reset to 0 by software.
Page 136: Input Voltage And Conversion Result
CHAPTER 9 A/D CONVERTER 9.4.2 Input voltage and conversion result The analog voltage input to an analog input pin (ANI0 to ANI7) and the result of A/D conversion (A/D conversion result register (ADCRH0)) have the following relation: ADCRH0 = INT ( ¥...
Page 137: Operation Mode Of A/D Converter
CHAPTER 9 A/D CONVERTER 9.4.3 Operation mode of A/D converter Select one analog input channel from ANI0 through ANI7 by the analog input channel specification register (ADS0) to start A/D conversion. The A/D conversion operation can be started only by software (by setting the A/D converter mode register (ADM0)). The A/D conversion result is stored in the A/D conversion result register (ADCRH0), and an interrupt request signal (INTAD) is generated.
Page 138: Notes On A/D Converter
CHAPTER 9 A/D CONVERTER 9.5 Notes on A/D Converter (1) Current consumption in standby mode The A/D converter is stopped in the standby mode. At this time, the current consumption can be reduced by stopping the conversion (by clearing bit 7 (CS0) of the A/D converter mode register (ADM0) to 0). Figure 9-7 shows how the current consumption can be reduced in the standby mode.
Page 139 CHAPTER 9 A/D CONVERTER (4) Noise measures To maintain the 8-bit resolution, care must be exercised that no noise is superimposed on the AV and ANI0 through ANI7 pins. The higher the output impedance of the analog input source, the heavier the influence of noise.
Page 140 CHAPTER 9 A/D CONVERTER Figure 9-9. A/D Conversion End Interrupt Request Generation Timing ADS0 rewriting ADS0 rewriting ADIF is set, but conversion of (ANIn conversion starts) (ANIm conversion starts) ANIm is not completed ANIn ANIn ANIm ANIm A/D conversion ANIn ANIn ANIm ANIm...
Page 141: Chapter 10 Serial Interface
CHAPTER 10 SERIAL INTERFACE CHAPTER 10 SERIAL INTERFACE 10.1 Function of Serial Interface The serial interface has the following two modes. • Operation stop mode • Three-wire serial I/O mode (1) Operation stop mode This mode is used when serial transfer is not performed. (2) Three-wire serial I/O mode (with MSB first) In this mode, 8-bit data is transferred by using three lines: serial clock (SCK), serial output (SO), and serial input (SI).
Page 142 CHAPTER 10 SERIAL INTERFACE Figure 10-1. Serial Interface Block Diagram Internal bus Serial operation SIO3 write mode register 3 Serial I/O shift CSIE3 MODE0 SCL31 SCL30 SIO3 read SI/P22 register 3 (SIO3) MODE0 SO/P21 MODE0 SCK/P20 Sampling Serial clock Clock INTCSI3 circuit counter...
Page 143: Registers Controlling Serial Interface
CHAPTER 10 SERIAL INTERFACE 10.3 Registers Controlling Serial Interface The serial interface is controlled by the serial operation mode register 3 (CSIM3). • Serial operation mode register 3 (CSIM3) This register selects the serial clock and operation mode of the serial interface, and enables or disables the operation.
Page 144: Operation Of Serial Interface
CHAPTER 10 SERIAL INTERFACE 10.4 Operation of Serial Interface The serial interface operates in the following two modes: • Operation stop mode • Three-wire serial I/O mode 10.4.1 Operation stop mode In the operation stop mode, the power consumption can be reduced because serial transfer is not executed. Because the serial I/O shift register 3 (SIO3) does not perform the shift operation, this register can be used as a normal 8-bit register.
Page 145: Three-Wire Serial I/O Mode
CHAPTER 10 SERIAL INTERFACE 10.4.2 Three-wire serial I/O mode The three-wire serial I/O mode is useful for connecting a peripheral I/O or display controller having a clocked serial interface. Communication is established by using three lines: serial clock (SCK), serial output (SO), and serial input (SI). (1) Register setting The three-wire serial I/O mode is set by the serial operation mode register 3 (CSIM3).
Page 146 CHAPTER 10 SERIAL INTERFACE (2) Communication operation In the three-wire serial I/O mode, data is transmitted or received in 8-bit units. Each bit of the data is transmitted or received in synchronization with the serial clock. The shift operation of the serial I/O shift register 3 (SIO3) is performed in synchronization with the falling of the serial clock (SCK).
Page 147: Chapter 11 Fip Controller/Driver
CHAPTER 11 FIP CONTROLLER/DRIVER CHAPTER 11 FIP CONTROLLER/DRIVER 11.1 Function of FIP Controller/Driver The FIP controller/driver of the m PD780228 subseries has the following functions. (1) Can output display signals (DMA operation) by automatically reading display data. (2) The pins not used for FIP display can be used as I/O port or output port pins (FIP16 through FIP47 pins only). (3) Luminance can be adjusted in 8 steps by display mode register 1 (DSPM1).
Page 148: Configuration Of Fip Controller/Driver
CHAPTER 11 FIP CONTROLLER/DRIVER 11.2 Configuration of FIP Controller/Driver The FIP controller/driver consists of the following hardware. Table 11-2. FIP Controller/Driver Configuration Item Configuration Display Control register Display mode register 0 (DSPM0) Display mode register 1 (DSPM1) Display mode register 2 (DSPM2) Figure 11-1.
Page 149: Registers Controlling Fip Controller/Driver
CHAPTER 11 FIP CONTROLLER/DRIVER 11.3 Registers Controlling FIP Controller/Driver 11.3.1 Control registers The following three types of registers control the FIP controller/driver. • Display mode register 0 (DSPM0) • Display mode register 1 (DSPM1) • Display mode register 2 (DSPM2) (1) Display mode register 0 (DSPM0) DSPM0 performs the following setting.
Page 150 CHAPTER 11 FIP CONTROLLER/DRIVER Figure 11-2. Display Mode Register 0 Format Symbol < 7 > Address At Reset DSPM0 DSPEN FOUT5 FOUT4 FOUT3 FOUT2 FOUT1 FOUT0 FF90H DSPEN Enables or disables FIP Disables Enables FOUT5 FOUT4 FOUT3 FOUT2 FOUT1 FOUT0 Number of FIP output pins 17-24 25-32...
Page 151 CHAPTER 11 FIP CONTROLLER/DRIVER (2) Display mode register 1 (DSPM1) DSPM1 performs the following setting: • Blanking width of FIP output signal • Number of display patterns DSPM1 is set by using an 8-bit memory manipulation instruction. The value of this register is set to 01H by RESET input. Figure 11-3.
Page 152 CHAPTER 11 FIP CONTROLLER/DRIVER (3) Display mode register 2 (DSPM2) DSPM2 performs the following setting. It also indicates the status of the display timing/key scan. • Insertion of key scan timing • Display cycle (TDSP) DSPM2 is set by using a 1-bit or 8-bit memory manipulation instruction. However, only bit 7 (KSF) can be read by a 1-bit memory manipulation instruction.
Page 153: One Display Period And Blanking Width
CHAPTER 11 FIP CONTROLLER/DRIVER 11.3.2 One display period and blanking width The FIP output signals are blanked equally at the beginning and end of the display period by the blanking width set by bits 0 through 2 (FBLK0 through FBLK2) of the display mode register 1 (DSPM1). Figure 11-5.
Page 154: Display Data Memory
CHAPTER 11 FIP CONTROLLER/DRIVER 11.4 Display Data Memory The display data memory is a 96-byte RAM area that stores data to be displayed, and is mapped to addresses FA00H through FA5FH. The FIP controller reads the data stored in the display data memory independently of the CPU operation for FIP display (DMA operation).
Page 155: Key Scan Flag And Key Scan Data
CHAPTER 11 FIP CONTROLLER/DRIVER 11.5 Key Scan Flag and Key Scan Data 11.5.1 Key scan flag The key scan flag (KSF) is set to 1 during key scan timing, and is automatically reset to 0 at display timing. KSF is mapped to bit 7 of the display mode register 2 (DSPM2) and can be tested in 1-bit units. It cannot be written, however.
Page 156: Leakage Emission Of Fluorescent Indicator Panel
CHAPTER 11 FIP CONTROLLER/DRIVER 11.6 Leakage Emission of Fluorescent Indicator Panel Leakage emission may take place when a fluorescent indicator panel is driven by the m PD780228 subseries. The possible causes of this leakage emission are as follows: (1) Short blanking time Figure 11-7 shows the signal waveforms of a 2-digit display where the first digit T0 lights and the second digit remains dark.
Page 157 CHAPTER 11 FIP CONTROLLER/DRIVER (2) Segment-grid capacitance of fluorescent indicator panel Even if a sufficiently long blanking time is ensured as shown in Figure 11-9, leakage emission may still occur. This is because the fluorescent indicator panel has a capacitance between the grid and segment, as indicated by C in the figure, and the timing signal pin is raised via C .
Page 158 CHAPTER 11 FIP CONTROLLER/DRIVER Figure 11-9. Leakage Emission Caused by C...
Page 159: Calculation Of Total Power Dissipation
CHAPTER 11 FIP CONTROLLER/DRIVER 11.7 Calculation of Total Power Dissipation The following three power dissipation are available for the m PD780208 subseries. The sum of the three power dissipation should be less than the total power dissipation P (refer to Figure 11-10) (80 % or less of ratings is recommended).
Page 160 CHAPTER 11 FIP CONTROLLER/DRIVER By placing the above conditions in calculation <1> to <3>, the total dissipation can be worked out. <1> CPU power dissipation: 5.5 V ¥ 21.0 mA = 115.5 mW <2> Output pin power dissipation: Total current value of each grid ) ¥...
Page 161 CHAPTER 11 FIP CONTROLLER/DRIVER Figure 11-11. Relationship between Display Data Memory and FIP Output with 10 Segments-11 Digits Displayed Display data memory 20 19 18 17 16 15 14 13 12 11 10 (FIP output pins : FIP0-FIP20)
Page 162 CHAPTER 11 FIP CONTROLLER/DRIVER [MEMO]...
Page 163: Chapter 12 Interrupt Functions
CHAPTER 12 INTERRUPT FUNCTIONS CHAPTER 12 INTERRUPT FUNCTIONS 12.1 Interrupt Function Types The following three types of interrupt functions are used. (1) Non-maskable interrupt This interrupt is acknowledged unconditionally even in a disabled state. It does not undergo interrupt priority control and is given top priority over all other interrupt requests.
Page 164: Interrupt Sources And Configuration
CHAPTER 12 INTERRUPT FUNCTIONS 12.2 Interrupt Sources and Configuration A total of 12 non-maskable, maskable and software interrupts are incorporated in the interrupt sources (see Table 12-1). Table 12-1. Interrupt Sources Vector Basic Interrupt Default Interrupt Source Internal/ Table Configuration Note 1 Note 2 Type...
Page 165 CHAPTER 12 INTERRUPT FUNCTIONS Figure 12-1. Basic Configuration of Interrupt Function (1/2) (A) Internal non-maskable interrupt Internal Bus Vector Table Interrupt Priority Control Address Request Circuit Generator Standby Release Signal (B) Internal maskable interrupt Internal Bus Vector Table Priority Control Interrupt Address Circuit...
Page 166 CHAPTER 12 INTERRUPT FUNCTIONS Figure 12-1. Basic Configuration of Interrupt Function (2/2) (D) External maskable interrupt (INTTM10, INTTM11) Internal Bus Vector Table Priority Control Interrupt Edge Address Circuit Request Detector Generator Standby Release Signal (E) Software interrupt Internal Bus Vector Table Interrupt Priority Control Address...
Page 167 CHAPTER 12 INTERRUPT FUNCTIONS 12.3 Interrupt Function Control Registers The following six types of registers are used to control the interrupt functions. • Interrupt request flag register (IF0L and IF0H) • Interrupt mask flag register (MK0L and MK0H) • Priority specify flag register (PR0L and PR0H) •...
Page 168: Interrupt Function Control Registers
CHAPTER 12 INTERRUPT FUNCTIONS (1) Interrupt request flag registers (IF0L and IF0H) The interrupt request flag is set to (1) when the corresponding interrupt request is generated or an instruction is executed. It is cleared to (0) when an instruction is executed upon acknowledgment of an interrupt request or upon application of RESET input.
Page 169 CHAPTER 12 INTERRUPT FUNCTIONS (2) Interrupt mask flag registers (MK0L and MK0H) The interrupt mask flag is used to enable/disable the corresponding maskable interrupt service and to set standby clear enable/disable. MK0L and MK0H are set with a 1-bit or 8-bit memory manipulation instruction. When MK0L and MK0H are used in combination as a 16-bit register MK0, they are set with a 16-bit memory operation instruction.
Page 170 CHAPTER 12 INTERRUPT FUNCTIONS (3) Priority specify flag registers (PR0L and PR0H) The priority specify flag is used to set the corresponding maskable interrupt priority orders. PR0L and PR0H are set with a 1-bit or 8-bit memory manipulation instruction. When PR0L and PR0H are used in combination as a 16-bit register PR0, they are set with a 16-bit memory operation instruction.
Page 171 CHAPTER 12 INTERRUPT FUNCTIONS (4) External interrupt rising edge enable register (EGP) This register specifies whether the valid edges of INTP0 and INTP1 are specified to be the rising edge. It is set by using a 1-bit or 8-bit memory manipulation instruction. The value of this register is initialized to 00H by RESET input.
Page 172 CHAPTER 12 INTERRUPT FUNCTIONS (6) Program status word (PSW) The program status word is a register to hold the instruction execution result and the current status for interrupt request. The IE flag to set maskable interrupt enable/disable and the ISP flag to control multiple interrupt processing are mapped.
Page 173: Interrupt Servicing Operations
CHAPTER 12 INTERRUPT FUNCTIONS 12.4 Interrupt Servicing Operations 12.4.1 Non-maskable interrupt request acknowledge operation A non-maskable interrupt request is unconditionally acknowledged even if in an interrupt acknowledge disable state. It does not undergo interrupt priority control and has highest priority over all other interrupts. If a non-maskable interrupt request is acknowledged, the contents are saved in the stacks, PSW and PC, in that order, the IE and ISP flags are reset to 0, and the vector table contents are loaded into PC and branched.
Page 174 CHAPTER 12 INTERRUPT FUNCTIONS Figure 12-8. Flowchart of Occurrence and Acknowledge Non-Maskable Interrupt Start WDTM4 = 1 (with watchdog timer mode selected) Interval timer Overflow in WDTM3 = 0 (with non-maskable interrupt selected) Reset processing Interrupt request generation WDT interrupt servicing Interrupt request reserve Interrupt control...
Page 175 CHAPTER 12 INTERRUPT FUNCTIONS Figure 12-10. Non-Maskable Interrupt Request Acknowledge Operation (a) If a new non-maskable interrupt request is generated during non-maskable interrupt servicing program execution Main Routine NMI Request <1> Execution NMI Request <1> NMI Request <2> Reserve NMI Request <2> 1 Instruction Execution Reserved NMI Request <2>...
Page 176: Maskable Interrupt Request Acknowledge Operation
CHAPTER 12 INTERRUPT FUNCTIONS 12.4.2 Maskable interrupt request acknowledge operation A maskable interrupt request becomes acknowledgeable when an interrupt request flag is set to 1 and the interrupt mask (MK) flag is cleared to 0. A vectored interrupt request is acknowledged in an interrupt enable state (with IE flag set to 1).
Page 177 CHAPTER 12 INTERRUPT FUNCTIONS Figure 12-11. Interrupt Request Acknowledge Processing Algorithm Start xxIF = 1? (Interrupt Request Generation) xxMK = 0? Interrupt request reserve Yes (High Priority) xxPR = 0? No (Low Priority) Any high- priority interrupt request simultaneously among simultaneously generated generated xxPR = 0 xxPR = 0 interrupts interrupt requests...
Page 178: Software Interrupt Request Acknowledge Operation
CHAPTER 12 INTERRUPT FUNCTIONS Figure 12-12. Interrupt Request Acknowledge Timing (Minimum Time) 6 Clocks Interrupt PSW and PC Save, Jump to CPU Processing Instruction Instruction Servicing Interrupt Servicing Program xxIF (xxPR = 1) 8 Clocks xxIF (xxPR = 0) 7 Clocks Remark 1 clock : : CPU clock) Figure 12-13.
Page 179: Multiple Interrupt Servicing
CHAPTER 12 INTERRUPT FUNCTIONS 12.4.4 Multiple interrupt servicing Acknowledging another interrupt while one interrupt is processed is called multiple interrupts. A multiple interrupt is not generated unless acknowledge of the interrupt request is enabled (IE = 1) (except the non-maskable interrupt). When an interrupt request is acknowledged, the other interrupt requests are disabled (IE = 0).
Page 180 CHAPTER 12 INTERRUPT FUNCTIONS Figure 12-14. Multiple Interrupt Examples Example 1. Two multiple interrupts are generated. Main Processing INTxx INTyy INTzz Servicing Servicing Servicing IE = 0 IE = 0 IE = 0 INTxx INTyy INTzz (PR = 1) (PR = 0) (PR = 0) RETI RETI...
Page 181 CHAPTER 12 INTERRUPT FUNCTIONS Example 3. Multiple interrupt is not generated because an interrupt is not processed. INTxx INTyy Main Processing Servicing Servicing IE = 0 INTyy (PR = 0) INTxx RETI (PR = 0) IE = 0 1 Instruction Execution RETI Because interrupts are not enabled (the EI instruction is not issued) in interrupt processing INTxx, interrupt request...
Page 182: Interrupt Request Reserve
CHAPTER 12 INTERRUPT FUNCTIONS 12.4.5 Interrupt request reserve Some instructions keep the acceptance of an interrupt request, if one occurs, pending until execution of the next instruction is completed. These instructions (that keep interrupt requests pending) are listed below. • MOV PSW, #byte •...
Page 183: Chapter 13 Standby Function
CHAPTER 13 STANDBY FUNCTION CHAPTER 13 STANDBY FUNCTION 13.1 Standby Function and Configuration 13.1.1 Standby function The standby function is intended to decrease the power consumption of the system. The following two modes are available. (1) HALT mode HALT instruction execution sets the HALT mode. The HALT mode is intended to stop the CPU operation clock. The system clock oscillator continues oscillating.
Page 184: Standby Function Control Register
CHAPTER 13 STANDBY FUNCTION 13.1.2 Standby function control register The wait time after the STOP mode is cleared upon interrupt request until the oscillation stabilizes is controlled with the oscillation stabilization time select register (OSTS). OSTS is set with a 1-bit/8-bit memory manipulation instruction. RESET input sets OSTS to 04H.
Page 185: Standby Function Operations
CHAPTER 13 STANDBY FUNCTION 13.2 Standby Function Operations 13.2.1 HALT mode (1) HALT mode set and operating status The HALT mode is set by executing the HALT instruction. The operating status in the HALT mode is described below. Table 13-1. HALT Mode Operating Status Item Operating status Clock Generator...
Page 186 CHAPTER 13 STANDBY FUNCTION (2) HALT mode clear The HALT mode can be cleared with the following three types of sources. (a) Clear upon unmasked interrupt request An unmasked interrupt request is used to clear the HALT mode. If interrupt request acknowledge is enabled, vectored interrupt service is carried out.
Page 187 CHAPTER 13 STANDBY FUNCTION (c) Clear upon RESET input As is the case with normal reset operation, a program is executed after branch to the reset vector address. Figure 13-3. HALT Mode Release by RESET Input HALT Wait Instruction : 13.1 ms) RESET Signal Oscillation...
Page 188: Stop Mode
CHAPTER 13 STANDBY FUNCTION 13.2.2 STOP mode (1) STOP mode set and operating status The STOP mode is set by executing the STOP instruction. Cautions 1. When the STOP mode is set, X2 pin is internally pulled-up to V to suppress the leakage at the crystal oscillator.
Page 189 CHAPTER 13 STANDBY FUNCTION (2) STOP mode release The STOP mode can be cleared with the following two types of sources. (a) Release by unmasked interrupt request An unmasked interrupt request is used to release the STOP mode. If interrupt request acknowledge is enabled after the lapse of oscillation stabilization time, vectored interrupt service is carried out.
Page 190 CHAPTER 13 STANDBY FUNCTION (b) Release by RESET input The STOP mode is cleared and after the lapse of oscillation stabilization time, reset operation is carried out. Figure 13-5. Release by STOP Mode RESET Input Wait STOP : 13.1 ms) Instruction RESET Signal...
Page 191: Chapter 14 Reset Function
CHAPTER 14 RESET FUNCTION CHAPTER 14 RESET FUNCTION 14.1 Reset Function The following two operations are available to generate the reset signal. (1) External reset input with RESET pin (2) Internal reset by watchdog timer overrun time detection External reset and internal reset have no functional differences. In both cases, program execution starts at the address at 0000H and 0001H by RESET input.
Page 192 CHAPTER 14 RESET FUNCTION Figure 14-2. Timing of Reset Input by RESET Input Oscillation Reset Period Normal Operation Stabilization Normal Operation (Oscillation Stop) (Reset Processing) Time Wait RESET Internal Reset Signal Delay Delay Hi-Z Port Pin Figure 14-3. Timing of Reset due to Watchdog Timer Overflow Oscillation Reset Period Normal Operation...
Page 193 CHAPTER 14 RESET FUNCTION Table 14-1. Hardware Status after Reset Hardware Status after Reset Note 1 Program counter (PC) Contents of reset vector table (0000H, 0001H) are set Stack pointer (SP) Undefined Program status word (PSW) Note 2 Data memory Undefined Note 2 General-purpose register...
Page 194 CHAPTER 14 RESET FUNCTION [MEMO]...
Page 195: Chapter 15 M M M M M Pd78F0228
CHAPTER 15 m m m m m PD78F0228 CHAPTER 15 m m m m m PD78F0228 The m PD78F0228 has a flash memory to which a program can be written or whose contents can be erased with the device mounted on the PC board of the target system. Table 15-1 shows the differences between the flash memory model ( m PD78F0228) and mask ROM models ( m PD780226 and 780228).
Page 196: Memory Size Select Register
CHAPTER 15 m m m m m PD78F0228 15.1 Memory Size Select Register The m PD78F0228 can select the internal memory capacities by using the memory size select register (IMS). By setting IMS, the memory mapping of the m PD78F0228 can be made the same as that of a mask ROM model with different internal memory capacities.
Page 197: Internal Expansion Ram Size Select Register
CHAPTER 15 m m m m m PD78F0228 15.2 Internal Expansion RAM Size Select Register The internal expansion RAM size select register (IXS) specifies the internal expansion RAM capacity. IXS is set by using an 8-bit memory manipulation instruction. The value of this register is set to 0CH by RESET input. Caution Be sure to set 0BH to IXS in the initial settings of the program.
Page 198: Flash Memory Programming
CHAPTER 15 m m m m m PD78F0228 15.3 Flash Memory Programming The flash memory can be written with the device mounted on the target system (on-board). To write the flash memory, connect a dedicated flash writer (Flashpro II: part number FL-PR2) to the host machine and target system. The flash memory can be also written on a flash memory writing adapter connected to the Flashpro II.
Page 199: Function Of Flash Memory Programming
CHAPTER 15 m m m m m PD78F0228 15.3.2 Function of flash memory programming By transmitting/receiving commands/data in the selected communication mode, operations of the flash memory such as writing are performed. Table 15-14 lists the major functions of the flash memory programming. Table 15-4.
Page 200: Connection Of Flashpro Ii
CHAPTER 15 m m m m m PD78F0228 15.3.3 Connection of Flashpro II Connection between the Flashpro II and m PD78F0228 differs depending on the selected communication mode. Figures 15-4 and 15-5 show the connections in the respective mode. Figure 15-4. Connection of Flashpro II in 3-Wire Serial I/O Mode µ...
Page 201: Chapter 16 Instruction Set
CHAPTER 16 INSTRUCTION SET CHAPTER 16 INSTRUCTION SET The instruction set for the m PD780228 subseries is described in the following pages. For the details of operations and mnemonics (instruction codes) of each instruction, refer to 78K/0 Series User’s Manual: Instructions (U12326E).
Page 202: Legend
CHAPTER 16 INSTRUCTION SET 16.1 Legend 16.1.1 Operand identifiers and description methods Operands are described in the “Operand” column of each instruction in accordance with the description method of the instruction operand identifier (refer to the assembler specifications for detail). When there are two or more description methods, select one of them.
Page 203: Description Of "Operation" Column
CHAPTER 16 INSTRUCTION SET 16.1.2 Description of “operation” column : A register; 8-bit accumulator : X register : B register : C register : D register : E register : H register : L register : AX register pair; 16-bit accumulator : BC register pair : DE register pair : HL register pair...
Page 204: Operation List
CHAPTER 16 INSTRUCTION SET 16.2 Operation List Instruction Mnemonic Operands Byte Clock Operation Flag Group Note 1 Note 2 Z AC CY r, #byte — r ¨ byte saddr, #byte (saddr) ¨ byte sfr ¨ byte sfr, #byte — Note 3 A ¨...
Page 205 CHAPTER 16 INSTRUCTION SET Instruction Mnemonic Operands Byte Clock Operation Flag Group Note 1 Note 2 Z AC CY rp, #word — rp ¨ word (saddrp) ¨ word saddrp, #word sfrp ¨ word sfrp, #word — AX, saddrp AX ¨ (saddrp) saddrp, AX (saddrp) ¨...
Page 206 CHAPTER 16 INSTRUCTION SET Instruction Mnemonic Operands Byte Clock Operation Flag Group Note 1 Note 2 Z AC CY A, CY ¨ A – byte ¥ ¥ ¥ A, #byte — saddr, #byte (saddr), CY ¨ (saddr) – byte ¥ ¥...
Page 207 CHAPTER 16 INSTRUCTION SET Instruction Mnemonic Operands Byte Clock Operation Flag Group Note 1 Note 2 Z AC CY A ¨ A ¦ byte ¥ A, #byte — saddr, #byte (saddr) ¨ (saddr) ¦ byte ¥ Note 3 A ¨ A ¦ r ¥...
Page 208 CHAPTER 16 INSTRUCTION SET Instruction Mnemonic Operands Byte Clock Operation Flag Group Note 1 Note 2 Z AC CY ADDW AX, #word — AX, CY ¨ AX + word ¥ ¥ ¥ 16-bit SUBW AX, #word — AX, CY ¨ AX – word ¥...
Page 209 CHAPTER 16 INSTRUCTION SET Instruction Mnemonic Operands Byte Clock Operation Flag Group Note 1 Note 2 Z AC CY CY ¨ CY Ÿ (saddr.bit) ¥ CY, saddr.bit CY, sfr.bit — CY ¨ CY Ÿ sfr.bit ¥ CY ¨ CY Ÿ A.bit ¥...
Page 210 CHAPTER 16 INSTRUCTION SET Instruction Mnemonic Operands Byte Clock Operation Flag Group Note 1 Note 2 Z AC CY (SP – 1) ¨ (PC + 3) (SP – 2) ¨ (PC + 3) , PC ¨ addr16, CALL !addr16 — SP ¨...
Page 211 CHAPTER 16 INSTRUCTION SET Instruction Mnemonic Operands Byte Clock Operation Flag Group Note 1 Note 2 Z AC CY PC ¨ PC + 3 + jdisp8 if(saddr.bit) = 1 saddr.bit, $addr16 sfr.bit, $addr16 — PC ¨ PC + 4 + jdisp8 if sfr.bit = 1 PC ¨...
Page 212: Instructions Listed By Addressing Type
CHAPTER 16 INSTRUCTION SET 16.3 Instructions Listed by Addressing Type (1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ...
Page 213 CHAPTER 16 INSTRUCTION SET Second [HL+byte] Operand Note #byte saddr !addr16 [DE] [HL] None [HL+B] $addr16 First [HL+C] Operand ADDC RORC SUBC ADDC ADDC ADDC ADDC ADDC ROLC SUBC SUBC SUBC SUBC SUBC ADDC SUBC B, C DBNZ saddr DBNZ ADDC SUBC !addr16...
Page 214 CHAPTER 16 INSTRUCTION SET (2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW Second Operand Note #word sfrp saddrp !addr16 None First Operand ADDW MOVW MOVW MOVW MOVW MOVW SUBW XCHW CMPW Note MOVW MOVW INCW DECW PUSH sfrp MOVW...
Page 215 CHAPTER 16 INSTRUCTION SET (4) Call instructions/branch instructions CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ Second Operand !addr16 !addr11 [addr5] $addr16 First Operand Basic instruction CALL CALLF CALLT Compound instruciton BTCLR DBNZ (5) Other instructions ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP...
Page 216 CHAPTER 16 INSTRUCTION SET [MEMO]...
Page 217: Appendix A Differences Between M M M M M Pd78044H, 780228, And 780208 Subseries
APPENDIX A DIFFERENCES BETWEEN m m m m m PD78044H, 780228, AND 780208 SUBSERIES APPENDIX A DIFFERENCES BETWEEN m m m m m PD78044H, 780228, AND 780208 SUBSERIES Table A-1 shows the major differences between the m PD78044H, 780228, and 780208 subseries. Table A-1.
Page 218 APPENDIX A DIFFERENCES BETWEEN m m m m m PD78044H, 780228, AND 780208 SUBSERIES [MEMO]...
Page 219: Appendix B Development Tools
APPENDIX B DEVELOPMENT TOOLS APPENDIX B DEVELOPMENT TOOLS The following development tools are available for the development of systems which employ the m PD780228 subseries. Figure B-1 shows the development tools.
Page 220 APPENDIX B DEVELOPMENT TOOLS Figure B-1. Development Tools Language processing software Embedded software • Assembler package • Real-time OS and OS • C compiler package • Fuzzy inference development • C library source file support system • System simulator • Integrated debugger •...
Page 221: Language Processing Software
APPENDIX B DEVELOPMENT TOOLS B.1 Language Processing Software RA78K/0 This is a program to convert a program written in mnemonics into an object code executable with a Assembler package microcontroller. Further, this assembler is provided with functions capable of automatically creating symbol tables and branch instruction optimization.
Page 222: Flash Memory Writing Tools
APPENDIX B DEVELOPMENT TOOLS B.2 Flash Memory Writing Tools Flashpro II Flash writer dedicated to microcontroller with flash memory. (part number: FL-PR2) This is a product of Naito Densei Machida Mfg. Co., Ltd. Flash writer FA-100GF Flash memory writing adapter for m PD780228 subseries and is connected to Flashpro II. Flash memory writing adapter This adapter is for a 100-pin plastic QFP (GF-3BA type).
Page 223: Debugging Tools
This is a lid used when a device is mounted to the NQPACK100RB. Note Under development Remarks 1. NQPACK100RB, YQPACK100RB, and HQPACK100RB are products of Tokyo Eletech Corp. (03- 5295-1661). Consult NEC distributor when purchasing these products. 2. NQPACK100RB, YQPACK100RB, and HQPACK100RB are available in one unit.
Page 224: Software
APPENDIX B DEVELOPMENT TOOLS B.3.2 Software (1/2) SM78K0 Debugs program at C source level or assembler level while simulating operation of target system System simulator on host machine. SM78K0 runs on Windows. By using the SM78K0, the logic and performance of an application can be verified independently of hardware development even when the in-circuit emulator is not used.
Page 225 APPENDIX B DEVELOPMENT TOOLS B.3.2 Software (2/2) ID78K0 The ID78K0 is a control program to debug the 78K/0 series. Integrated Debugger The ID78K0 uses Windows on personal computers and OSF/Motif™ on EWS as graphical interface, and presents the appearance and operatability conforming to these platforms. The ID78K0 has enhanced debugging function supporting C language, and the trace result can be displayed by using the window integration function that interlocks source program, disassemble display, and memory display to the trace result.
Page 226: Os For Ibm Pc
APPENDIX B DEVELOPMENT TOOLS B.4 OS for IBM PC The following OSs for the IBM PC are supported. To operate SM78K0, ID78K/0, and FE9200 (refer to C.2 Fuzzy Inference Development Support System), Windows (Ver. 3.0 to Ver. 3.1) is necessary. Version PC DOS Ver.
Page 227 APPENDIX B DEVELOPMENT TOOLS PACKAGE DRAWINGS OF NQPACK100RB, HQPACK100RB, AND YQPACK100RB Figure B-2. NQPACK100RB (Target-Connected Side) Package Drawings (Reference) Protrusion height ITEM MILLIMETERS INCHES ITEM MILLIMETERS INCHES 21.75 0.856 22.75 0.896 14.25 0.561 0.020 0.65x19=12.35 0.026x0.748=0.486 0.020 φ φ 0.65 0.026 4- 2.0 4- 0.079...
Page 228 APPENDIX B DEVELOPMENT TOOLS Figure B-3. HQPACK100RB (Lid for Device Mounted) Package Drawings (Reference) G H I ITEM MILLIMETERS INCHES ITEM MILLIMETERS INCHES 17.4 0.685 2.25 0.089 0.65x19=12.35 0.026x0.748=0.486 0.063 0.65 0.026 0.25 0.010 0.236 16.57 0.652 23.75 0.935 17.57 0.692 0.276 0.020...
Page 229 APPENDIX B DEVELOPMENT TOOLS Figure B-4. YQPACK100RB (Probe Side) Package Drawings (Reference) R N O P ITEM MILLIMETERS INCHES ITEM MILLIMETERS INCHES 17.4 0.685 0.685 0.65x19=12.35 0.026x0.748=0.486 0.026 0.65 0.026 14.75 0.748 0.236 15.55 0.486 16.85 0.663 0.016 19.25 0.758 0.016 21.65 0.852...
Page 230 APPENDIX B DEVELOPMENT TOOLS [MEMO]...
Page 231: Appendix C Embedded Software
APPENDIX C EMBEDDED SOFTWARE APPENDIX C EMBEDDED SOFTWARE For efficient program development and maintenance of the m PD780228 subseries, the following embedded software products are available.
Page 232: Real-Time Os
APPENDIX C EMBEDDED SOFTWARE C.1 Real-time OS (1/2) RX78K/0 is a real-time OS which is based on the m ITRON specification. RX78K/0 Real-time OS Supplied with the RX78K/0 nucleus and a tool to prepare multiple information tables (configurator). Used in combination with optional assembler package (RA78K/0) and device file (DF780228). Part Number: m SxxxxRX78013- Caution When purchasing the RX78K/0, fill in the purchase application form in advance, and sign the User Agreement.
Page 233 APPENDIX C EMBEDDED SOFTWARE C.1 Real-time OS (2/2) m ITRON-specification subset OS. Nucleus of MX78K0 is supplied. MX78K0 This OS performs task management, event management, and time management. It controls the task execution sequence for task management and selects the task to be executed next. Part number: m SxxxxMX78K0- Remark xxxx and in the part number differs depending on the host machine and OS, etc.
Page 234: Fuzzy Inference Development Support System
APPENDIX C EMBEDDED SOFTWARE C.2 Fuzzy Inference Development Support System FE9000/FE9200 Program supporting input of fuzzy knowledge data (fuzzy rule and membership function), editing Fuzzy Knowledge Data (edit), and evaluation (simulation). Preparation Tool FE9200 operations on Windows. Part Number (Product Name): m SxxxxFE9000 (PC-9800 series) m SxxxxFE9200 (IBM PC/AT and compatible machines) FT9080/FT9085 Program converting fuzzy knowledge data obtained by using fuzzy knowledge data preparation...
Page 235: Appendix D Register Index
APPENDIX D REGISTER INDEX APPENDIX D REGISTER INDEX D.1 Register Index ADCRH0 : A/D conversion result register ... 110 : A/D converter mode register ... 112 AD0S : A/D converter input select register ... 113 CR10 : 8-bit compare register 10 ... 79 CR11 : 8-bit capture register 11 ...
Page 236 APPENDIX D REGISTER INDEX : Port 8 ... 60 : Port 9 ... 61 : Port 10 ... 62 PLR7 : Port read 7 ... 59 PLR8 : Port read 8 ... 60 PLR9 : Port read 9 ... 61 : Processor clock control register ...
Page 237: Appendix E Revision History
APPENDIX E REVISION HISTORY APPENDIX E REVISION HISTORY This table shows the revision history of this manual. The column under the heading “Chapter” indicates the chapter of the preceding edition in which a revision has been made. Edition Major Revision from Previous Edition Chapter Change of m PD780226 and 780228 from “under development”...
Page 238 APPENDIX E REVISION HISTORY [MEMO]...
Page 239 Facsimile Message Although NEC has taken all possible steps to ensure that the documentation supplied to our customers is complete, bug free and up-to-date, we readily accept that From: errors may occur. Despite all the care and precautions we've taken, you may Name encounter problems in the documentation.

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