NEC UPD703116 User Manual page 296

TCLR1n/
INTP1n1
TCUD1n/
INTP1n0
f /2
XX
f /4
XX
TIUD1n
Note The INTP1n1 interrupt is the signal of the capture trigger signal from the INTP1n1 pin or the capture
trigger signal from the INTP1n0 pin, selected by the CSLn bit of the CSL1n register.
Remarks 1. n = 0, 1
2. f : Internal system clock
XX
3. f : Base clock (16 MHz (MAX.))
CLK
296
CHAPTER 9 TIMER/COUNTER FUNCTION
Figure 9-48. Block Diagram of Timer 1
Internal bus
Edge
detector
CC1n1
Edge
detector
Edge
detector
Edge
1/2, 1/4, 1/8, 1/16,
detector
1/32, 1/64, 1/128
Clock SELCLK
f
control
CLK
Edge
CM1n0
detector
Internal bus
User's Manual U14492EJ5V0UD
CC1n0
TM1UBDn CMD
TCLR
Clear
TM1n
ENMD MSEL
CM1n1
RLEN
CLR1, CLR0
INTP1n0/
Selector
INTCC1n0
Note
INTP1n1 /
Selector
INTCC1n1
TM1OVFn TM1UDFn
Output
TO1n
control
ALVT10
INTCM1n0
INTCM1n1