Page 1 User's Manual µ PD784038, 784038Y Subseries 16-Bit Single-Chip Microcontrollers Hardware µ PD784031 µ PD784031Y µ PD784031(A) µ PD784035 µ PD784035Y µ PD784035(A) µ PD784036 µ PD784036Y µ PD784036(A) µ PD784037 µ PD784037Y µ PD784038 µ PD784038Y µ PD78P4038 µ PD78P4038Y Document No.
Page 2 [MEMO] User’s Manual U11316EJ4V1UD...
Page 3 Reset operation must be executed immediately after power-on for devices having reset function. EEPROM, FIP, and IEBus are trademarks of NEC Electronics Corporation. MS-DOS, Windows, and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries.
Page 4 NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Page 5 Regional Information Some information contained in this document may vary from country to country. Before using any NEC Electronics product in your application, pIease contact the NEC Electronics office in your country to obtain a list of authorized representatives and distributors. They will verify: •...
Page 6 Major Revisions in This Edition (1/2) Page Description Throughout Addition of the following special grade products to the target products • µ PD784031GC(A)-3B9, 784035GC(A)-×××-3B9, 784036GC(A)-×××-3B9 Deletion of the following packages • µ PD784031GC-3B9, 784031GK-BE9, 784035GC-×××-3B9, 784035GK-×××-BE9, 784036GC-×××-3B9, 784036GK-×××-BE9, 784037GC-×××-3B9, 784037GK-×××-BE9, 784038GC-×××-3B9, 784038GK-×××-BE9, 78P4038GC-3B9, 78P4038GC-×××-3B9, 78P4038GC-×××-8BT, 78P4038GK-BE9, 78P4038GK-×××-BE9, 78P4038KK-T...
Page 7 Major Revisions in This Edition (2/2) Page Description CHAPTER 18 3-WIRE/2-WIRE SERIAL I/O MODE pp.452, 453 • Modification of Figure 18-6 3-Wire Serial I/O Mode Timing • 18.6 CAUTIONS p.460 • Addition of caution on transmit data write in 3-wire serial I/O mode p.460 •...
Page 8 PREFACE Intended Readership This manual is intended for user engineers who understand the functions of the µ PD784038, 784038Y Subseries and wish to design application systems using these subseries. The following are the target products in the µ PD784038, 784038Y Subseries. •...
Page 9 How to Read This Manual Readers are required to have a general knowledge of electrical and logic circuits and microcontrollers. • Unless otherwise specified The µ PD784038 in the µ PD784038 Subseries is treated as the representative model of the mask ROM models, the µ...
Page 10 Decimal ....× × × × Hexadecimal ..× × × × H Register Notation Where the bit number is marked with a circle, the bit name is reserved for NEC Electronics × × assembler and is defined as an sfr variable by the #pragma sfr directive for C compiler.
Page 11 Related Documents The related documents in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents Related to Devices Document Name Document No. µ PD784038, 784038Y Subseries User’s Manual - Hardware This manual 78K/IV Series Application Note - Software Fundamentals U10095E 78K/IV Series User's Manual - Instructions U10905E...
Page 12 SEMICONDUCTOR SELECTION GUIDE - Products & Packages - X13769E Semiconductor Device Mounting Technology Manual C10535E Quality Grades on NEC Semiconductor Devices C11531E NEC Semiconductor Device Reliability/Quality Control System C10983E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E Caution The related documents listed above are subject to change without notice.
Page 13: Table Of Contents
CONTENTS CHAPTER 1 GENERAL ....................... FEATURES ........................ORDERING INFORMATION AND QUALITY GRADES ........... 1.2.1 Ordering Information ......................1.2.2 Quality Grades ......................... PIN CONFIGURATION (TOP VIEW) ................1.3.1 Normal Operating Mode ....................≥ +5 V/+12.5 V, RESET = L) ........1.3.2 PROM Programming Mode (V APPLICATION SYSTEM CONFIGURATION EXAMPLE (PPC) ......
Page 14 3.8.1 Configuration ........................3.8.2 Functions .......................... SPECIAL FUNCTION REGISTERS (SFRS) .............. 3.10 CAUTIONS ........................CHAPTER 4 CLOCK GENERATOR ................... CONFIGURATION AND FUNCTION ................CONTROL REGISTERS ....................4.2.1 Standby Control Register (STBC) ................... 4.2.2 Oscillation Stabilization Time Specification Register (OSTS) ........CLOCK GENERATOR OPERATION ................
Page 15 5.7.1 Hardware Configuration ....................5.7.2 I/O Mode/Control Mode Setting ..................5.7.3 Operating Status ......................5.7.4 Internal Pull-Up Resistors ....................5.7.5 Direct LED Drive ......................PORT 6 ........................... 5.8.1 Hardware Configuration ....................5.8.2 I/O Mode/Control Mode Setting ..................5.8.3 Operating Status ......................5.8.4 Internal Pull-Up Resistors ....................
Page 16 8.8.2 Operation as Interval Timer (2) ..................8.8.3 Pulse Width Measurement Operation ................8.8.4 Operation as PWM Output ....................8.8.5 Operation as PPG Output ....................8.8.6 Example of Software Triggered One-Shot Pulse Output ..........CAUTIONS ........................CHAPTER 9 TIMER/COUNTER 1 ....................FUNCTIONS ........................
Page 17 10.9.5 Operation as PPG Output ....................10.9.6 Operation as External Event Counter ................10.9.7 Operation as One-Shot Timer ..................10.10 CAUTIONS ........................CHAPTER 11 TIMER 3 ........................11.1 FUNCTION ........................11.2 CONFIGURATION ......................11.3 TIMER 3 CONTROL REGISTERS ................11.4 TIMER REGISTER 3 (TM3) OPERATION ..............
Page 18 14.4 EXTERNAL CIRCUIT OF A/D CONVERTER ............14.5 CAUTIONS ........................CHAPTER 15 D/A CONVERTER ....................15.1 CONFIGURATION ......................15.2 D/A CONVERTER MODE REGISTER (DAM) ............15.3 D/A CONVERTER OPERATION .................. 15.3.1 Basic Operation ....................... 15.3.2 D/A Converter Standby Operation .................. 15.4 CAUTIONS ........................
Page 19 18.4.2 Operation When Transmission Only is Enabled ............18.4.3 Operation When Reception Only is Enabled ..............18.4.4 Operation When Transmission/Reception is Enabled ........... 18.4.5 Corrective Action in Case of Slippage of Serial Clock and Shift Operations ....18.5 2-WIRE SERIAL I/O MODE ..................18.5.1 Basic Operation Timing ....................
Page 20 21.1.1 External Interrupt Mode Registers (INTM0, INTM1) ............21.1.2 Sampling Clock Selection Register (SCS0) ..............21.2 EDGE DETECTION FOR PINS P20, P25 AND P26 ..........21.3 EDGE DETECTION FOR PIN P21 ................21.4 EDGE DETECTION FOR PINS P22 TO P24 ............21.5 CAUTIONS ........................
Page 21 22.11 INTERRUPT AND MACRO SERVICE OPERATION TIMING ........ 22.11.1 Interrupt Acknowledge Processing Time ................ 22.11.2 Processing Time of Macro Service ................. 22.12 RESTORING INTERRUPT FUNCTION TO INITIAL STATE ........22.13 CAUTIONS ........................CHAPTER 23 LOCAL BUS INTERFACE FUNCTION ............. 23.1 MEMORY EXTENSION FUNCTION ................
Page 22 26.4 SCREENING OF ONE-TIME PROM PRODUCT ............26.5 CAUTIONS ........................CHAPTER 27 INSTRUCTION OPERATIONS................27.1 LEGEND ........................... 27.2 LIST OF OPERATIONS ....................27.3 INSTRUCTIONS LISTED BY TYPE OF ADDRESSING ......... CHAPTER 28 ELECTRICAL SPECIFICATIONS ................ CHAPTER 29 PACKAGE DRAWINGS ..................CHAPTER 30 RECOMMENDED SOLDERING CONDITIONS ..........
Page 23 LIST OF FIGURES (1/12) Figure No. Title Page Pin Input/Output Circuits ...................... µ PD784031 Memory Map ....................µ PD784035 Memory Map ....................µ PD784036 Memory Map ....................µ PD784037 Memory Map ....................µ PD784038 Memory Map ....................Internal RAM Memory Map ....................Internal Memory Size Switching Register (IMS) Format ............
Page 24 LIST OF FIGURES (2/12) Figure No. Title Page 5-19 Pull-Up Resistor Option Register (PUO) Format ..............5-20 Pull-Up Resistor Specification (Port 1) ................5-21 Example of Direct LED Drive ....................5-22 Block Diagram of P20 to P24, P26 and P27 (Port 2) ............5-23 Block Diagram of P25 (Port 2) ....................
Page 25 LIST OF FIGURES (3/12) Figure No. Title Page 5-61 Port 7 Block Diagram ......................5-62 Port 7 Mode Register (PM7) Format ................... 5-63 Port Specified as Output Port ....................5-64 Port Specified as Input Port ....................Real-Time Output Port Block Diagram ................Real-Time Output Port Control Register (RTPC) Format ..........
Page 26 LIST OF FIGURES (4/12) Figure No. Title Page 8-26 Example of 100% Duty With PPG Output ................8-27 Example of Extended PPG Output Cycle ................8-28 When Timer/Counter 0 is Stopped During PPG Signal Output ......... 8-29 Example of Software Triggered One-Shot Pulse Output ........... 8-30 Interval Timer Operation (1) Timing ..................
Page 27 LIST OF FIGURES (5/12) Figure No. Title Page 9-12 Example of the Case Where the External Event Counter Does Not Distinguish Between One Valid Edge Input and No Valid Edge Input ..........9-13 Methods of Enabling the External Event Counter to Distinguish No Valid Edge Input ..9-14 Compare Operation in 8-Bit Operating Mode ..............
Page 28 LIST OF FIGURES (6/12) Figure No. Title Page 10-15 One-Shot Timer Operation ....................10-16 Compare Operation in 8-Bit Operating Mode ..............10-17 Compare Operation in 16-Bit Operating Mode ..............10-18 TM2 Clearance after Match Detection ................10-19 Capture Operation in 8-Bit Operating Mode ............... 10-20 Capture Operation in 16-Bit Operating Mode ..............
Page 29 LIST OF FIGURES (7/12) Figure No. Title Page 10-58 External Event Counter Operation Setting Procedure ............10-59 One-Shot Timer Operation ....................10-60 Control Register Settings for One-Shot Timer Operation ..........10-61 One-Shot Timer Operation Setting Procedure ..............10-62 One-Shot Timer Operation Start Procedure from Second Time Onward ......10-63 Operation When Counting is Started ..................
Page 30 LIST OF FIGURES (8/12) Figure No. Title Page 14-8 Scan Mode 1 Operation Timing ................... 14-9 Software Start Select Mode A/D Conversion Operation ............ 14-10 Software Start Scan Mode A/D Conversion Operation ............14-11 Hardware Start Select Mode A/D Conversion Operation ........... 14-12 Hardware Start Scan Mode A/D Conversion Operation .............
Page 31 LIST OF FIGURES (9/12) Figure No. Title Page 19-1 Example of Serial Bus Configuration Using I C Bus ............19-2 Block Diagram of Clock-Synchronous Serial Interface (In I C Bus Mode) ....... 19-3 Clocked Serial Interface Mode Register (CSIM) Format ........... 19-4 C Bus Control Register (IICC) Format ................
Page 32 LIST OF FIGURES (10/12) Figure No. Title Page 22-13 Examples of Servicing When Another Interrupt Request is Generated During Interrupt Service ....................... 22-14 Examples of Servicing of Simultaneously Generated Interrupts ........22-15 Differences in Level 3 Interrupt Acknowledgment According to IMC Register Setting ..22-16 Differences between Vectored Interrupt and Macro Service Processing ......
Page 33 LIST OF FIGURES (11/12) Figure No. Title Page 23-8 Write Timing ......................... 23-9 Memory Extension Mode Register (MM) Format..............23-10 Programmable Wait Control Register (PWC1/PWC2) Format ........... 23-11 Address Wait Function Read/Write Timing ................. 23-12 Wait Control Spaces ......................23-13 Access Wait Function Read Timing ..................
Page 34 LIST OF FIGURES (12/12) Figure No. Title Page Package Drawing of EV-9200GC-80 (Reference) .............. Recommended Board Installation Pattern of EV-9200GC-80 (Reference) ....... TGK-080SDW Package Drawing (Reference) ..............User’s Manual U11316EJ4V1UD...
Page 35 LIST OF TABLES (1/3) Table No. Title Page Port 1 Operating Modes ....................... Port 2 Operating Modes ....................... Port 3 Operating Modes (n = 0 to 7) ................... Port 6 Operating Modes ....................... Pin Input/Output Circuit Types and Recommended Connection When Not Used ... Vector Table .........................
Page 36 LIST OF TABLES (2/3) Table No. Title Page Timer/Counter 1 Intervals ....................Timer/Counter 1 Pulse Width Measurement Range ............Timer/Counter 1 Pulse Width Measurement Time ............. Limits of Reading Timer Register ..................Maximum Input Frequency and Minimum Input Pulse Width That Can be Counted as Events .......................
Page 37 LIST OF TABLES (3/3) Table No. Title Page 22-7 Interrupt Acknowledge Processing Time ................22-8 Macro Service Processing Time ..................23-1 System Clock Frequency and Refresh Pulse Output Cycle When Pseudo-static RAM is Used ....................24-1 Operating States in HALT Mode ..................24-2 HALT Mode Release and Operations after Release ............
Page 38: Chapter 1 General
CHAPTER 1 GENERAL The µ PD784038 Subseries comprises 78K/IV Series products that can perform input/output directly with analog signals. The 78K/IV Series comprises 16-bit single-chip microcontrollers equipped with a high-performance CPU that has a function such as accessing a 1-Mbyte memory space. The µ PD784038 Subseries is upward-compatible with the 78K/II Series, and has pin compatibility with µ...
Page 39 CHAPTER 1 GENERAL 78K/IV Series Product Development Diagram : Products in mass-production Supports I C bus Supports multimaster I C bus µ PD784038Y µ PD784225Y µ PD784038 µ PD784225 Standard models Enhanced internal memory capacity 80-pin, ROM correction added µ Pin-compatible with the PD784026 µ...
Page 40: Features
CHAPTER 1 GENERAL 1.1 FEATURES • 78K/IV Series • Pin-compatible with µ PD78234 Subseries and µ PD784026 Subseries • Internal memory of µ PD78234 Subseries and µ PD784026 Subseries expanded • High-speed instruction execution • Minimum instruction execution time (32-MHz operation): 125 ns •...
Page 41: Ordering Information And Quality Grades
CHAPTER 1 GENERAL 1.2 ORDERING INFORMATION AND QUALITY GRADES 1.2.1 Ordering Information (1) µ PD784038 Subseries Part Number Package Internal ROM µ PD784031GC-8BT 80-pin plastic QFP (14 x 14, 1.4 mm thickness) None µ PD784031GK-9EU 80-pin plastic TQFP (fine pitch) (12 x 12) None µ...
Page 42 CHAPTER 1 GENERAL (2) µ PD784038Y Subseries Part Number Package Internal ROM µ PD784031YGC-8BT 80-pin plastic QFP (14 x 14, 1.4 mm thickness) None µ PD784031YGK-9EU 80-pin plastic TQFP (fine pitch) (12 x 12) None µ PD784035YGC-×××-8BT 80-pin plastic QFP (14 x 14, 1.4 mm thickness) Mask ROM µ...
Page 43: Quality Grades
80-pin plastic TQFP (fine pitch) (12 x 12) Standard Please refer to the document "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by NEC Corporation for the specification of the quality grades of the devices and their recommended applications.
Page 44 CHAPTER 1 GENERAL (2) µ PD784038Y Subseries Part Number Package Quality Grades µ PD784031YGC-8BT 80-pin plastic QFP (14 x 14, 1.4 mm thickness) Standard µ PD784031YGK-9EU 80-pin plastic TQFP (fine pitch) (12 x 12) Standard µ PD784035YGC-×××-8BT 80-pin plastic QFP (14 x 14, 1.4 mm thickness) Standard µ...
Page 45: Pin Configuration (Top View)
CHAPTER 1 GENERAL 1.3 PIN CONFIGURATION (TOP VIEW) 1.3.1 Normal Operating Mode • 80-pin plastic QFP (14 x 14, 2.7 mm thickness) µ PD784031GC(A)-3B9, 784035GC(A)-×××-3B9, 784036GC(A)-×××-3B9 • 80-pin plastic QFP (14 x 14, 1.4 mm thickness) µ PD784031GC-8BT, 784035GC-×××-8BT, 784036GC-×××-8BT, 784037GC-×××-8BT, 784038GC-×××-8BT, 78P4038GC-8BT, 784031YGC-8BT, 784035YGC-×××-8BT, 784036YGC-×××-8BT, 784037YGC-×××-8BT, 784038YGC-×××-8BT, 78P4038YGC-8BT •...
Page 46 CHAPTER 1 GENERAL 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 P32/SCK0/SCL P74/ANI4 P33/SO0/SDA P73/ANI3 P34/TO0 P72/ANI2 P35/TO1 P71/ANI1 P36/TO2 P70/ANI0 P37/TO3 RESET P14/TxD2/SO2 P13/RxD2/SI2 P12/ASCK2/SCK2 P11/PWM1 P10/PWM0 Note TEST ASTB/CLKOUT...
Page 47 CHAPTER 1 GENERAL P00 to P07 : Port 0 AD0 to AD7 : Address/Data Bus P10 to P17 : Port 1 A8 to A19 : Address Bus P20 to P27 : Port 2 : Read Strobe P30 to P37 : Port 3 : Write Strobe P40 to P47 : Port 4...
Page 48: Prom Programming Mode
CHAPTER 1 GENERAL ≥ 1.3.2 PROM Programming Mode (V +5 V/+12.5 V, RESET = L) • 80-pin plastic QFP (14 × × × × × 14, 1.4 mm thick) µ PD78P4038GC-8BT, 78P4038YGC-8BT • 80-pin plastic TQFP (fine pitch) (12 × × × × × 12) µ...
Page 49: Application System Configuration Example (Ppc)
CHAPTER 1 GENERAL 1.4 APPLICATION SYSTEM CONFIGURATION EXAMPLE (PPC) µ PD784038 Paper Detection Serial Paper Feed Detection Communication Paper Out Detection Document Base (Scanner) Position Detection SCK1 Control Panel Paper Transport INTP0 Detection Drum, Toner High-Voltage Control Circuit Transfer Charge Fixing Heater Fixing Roller Control Circuit...
Page 50: Block Diagram
CHAPTER 1 GENERAL 1.5 BLOCK DIAGRAM RxD/SI1 Programmable UART/IOE2 TxD/SO1 Interrupt Baud-Rate INTP0 to INTP5 Controller ASCK/SCK1 Generator RxD2/SI2 INTP3 UART/IOE1 Timer/Counter 0 TxD2/SO2 (16 Bits) Baud-Rate ASCK2/SCK2 Generator SCK0/SCL Timer/Counter 1 Note 1 Clocked INTP0 (16 Bits) Serial SO0/SDA Interface INTP1 Note 2...
Page 51: List Of Functions
CHAPTER 1 GENERAL 1.6 LIST OF FUNCTIONS (1/2) µ PD784031 µ PD784035 µ PD784036 µ PD784037 µ PD784038 µ PD78P4038 Part Number µ PD784031Y µ PD784035Y µ PD784036Y µ PD784037Y µ PD784038Y µ PD78P4038Y Item Number of basic instructions (mnemonics) 8 bits ×...
Page 52 CHAPTER 1 GENERAL (2/2) µ PD784031 µ PD784035 µ PD784036 µ PD784037 µ PD784038 µ PD78P4038 Part Number µ PD784031Y µ PD784035Y µ PD784036Y µ PD784037Y µ PD784038Y µ PD78P4038Y Item Clock output — Selectable from f /2, f /4, f /8, f /16 (also can be used as 1-bit output port) Watchdog timer...
Page 53: Differences Between Standard-Grade Products And Special-Grade Products
CHAPTER 1 GENERAL 1.7 DIFFERENCES BETWEEN STANDARD-GRADE PRODUCTS AND SPECIAL-GRADE PRODUCTS µ PD784031(A), µ PD784035(A), µ PD784036(A) µ PD784031, µ PD784035, µ PD784036 Part Number Item Quality grade Special Standard Package 80-pin plastic QFP (14 x 14, 2.7 mm thick) 80-pin plastic QFP (14 x 14, 1.4 mm thick) 80-pin plastic TQFP (fine pitch, 12 x 12) 1.8 MAJOR DIFFERENCES WITH µ...
Page 54: Chapter 2 Pin Functions
CHAPTER 2 PIN FUNCTIONS 2.1 PIN FUNCTION TABLES 2.1.1 Normal Operating Mode (1) Port pins (1/2) Pin Name Input/Output Alternate Function Functions P00 to P07 Input/output — Port 0 (P0): • 8-bit input/output port • Can be used as real-time output ports (4 bits × 2) •...
Page 55 CHAPTER 2 PIN FUNCTIONS (1) Port pins (2/2) Pin Name Input/Output Alternate Function Functions Note 1 P40 to P47 Input/output AD0 to AD7 Port 4 (P4): • 8-bit input/output port • Input/output specifiable bit-wise • For input mode pins, on-chip pull-up resistor connection can be specified at once by a software setting •...
Page 56 CHAPTER 2 PIN FUNCTIONS (2) Non-port pins (1/2) Pin Name Input/Output Alternate Function Functions TO0/TO3 Output P34 to P37 Timer output Input P23/INTP2 Count clock input to timer/counter 2 Input P30/SI1 Serial data input (UART0) RxD2 P13/SI2 Serial data input (UART2) Output P31/SO1 Serial data output (UART0)
Page 57: Prom Programming Mode
CHAPTER 2 PIN FUNCTIONS (2) Non-port pins (2/2) Pin Name Input/Output Alternate Function Functions ASTB Output CLKOUT Time division address (A0 to A7) latch timing output (during external memory access) CLKOUT Note 1 Output ASTB Clock output RESET Input — Chip reset Input —...
Page 58: Pin Functions
CHAPTER 2 PIN FUNCTIONS 2.2 PIN FUNCTIONS 2.2.1 Normal Operating Mode (1) P00 to P07 (Port 0) ... 3-state input/output Port 0 is an 8-bit input/output port with an output latch, and has direct transistor drive capability. Input/output can be specified bit-wise by means of the port 0 mode register (PM0).
Page 59 CHAPTER 2 PIN FUNCTIONS (iii) RxD2/SI2 RxD2 is the asynchronous serial interface serial data input pin. SI2 is the serial data input pin (in 3-wire serial I/O2 mode). (iv) TxD2/SO2 TxD2 is the asynchronous serial interface serial data output pin. SO2 is the serial data output pin (in 3-wire serial I/O2 mode).
Page 60 CHAPTER 2 PIN FUNCTIONS (ii) INTP0 to INTP5 (Interrupt from Peripherals) External interrupt request input pins. When the valid edge specified by the external interrupt mode register 0, (INTM0/INTM1) is detected by pins INTP0 to INTP5, an interrupt is generated (see CHAPTER 21 EDGE DETECTION FUNCTION).
Page 61 CHAPTER 2 PIN FUNCTIONS (a) Port mode Each port specified as port mode by the port 3 mode control (PMC3) register can be specified as input/output bit-wise by means of the port 3 mode register (PM3). (b) Control signal input/output mode Pins can be set as control pins bit-wise by setting the port 3 mode control (PMC3) register.
Page 62 CHAPTER 2 PIN FUNCTIONS (7) P60 to P67 (Port 6) ... 3-state input/output • With µ µ µ µ µ PD784031 P60 to P63 are output port pins and P66 and P67 are input/output port pins with output latch. P64 to P67 incorporate a software programmable pull-up resistor. In addition to the functions as port pins, these pins also have various alternate-function control signal pin functions, as shown in Table 2-4.
Page 63 CHAPTER 2 PIN FUNCTIONS (b) Control signal input/output mode A16 to A19 (Address Bus) Upper address bus output pins in case of external memory space extension (10000H to FFFFFH). These pins operate in accordance with the memory extension mode register (MM). (ii) RD (Read Strobe) Pin that outputs the strobe signal for an external memory read operation.
Page 64 (22) TEST Pin used by NEC Electronics for IC testing. Must be directly connected to V Caution In the µ µ µ µ µ PD78233 and 78237, the TEST pin is the MODE pin and is fixed high. When changing over from the µ...
Page 65: Prom Programming Mode ( Μ Pd78P4038)
CHAPTER 2 PIN FUNCTIONS 2.2.2 PROM Programming Mode ( µ µ µ µ µ PD78P4038) (1) V (Programming Power Supply) ... Input Input pin that sets the µ PD78P4038 to the PROM programming mode. When the input voltage of this pin is +5 V or more and the RESET input is driven low, the µ...
Page 66: Input/Output Circuits And Connection Of Unused Pins
CHAPTER 2 PIN FUNCTIONS 2.3 INPUT/OUTPUT CIRCUITS AND CONNECTION OF UNUSED PINS Table 2-5 shows the input/output circuit types of the pins that have functions, and the connection method when that function is not used. Each input/output circuit type is shown in Figure 2-1. Table 2-5 Pin Input/Output Circuit Types and Recommended Connection When Not Used (1/2) Input/Output Recommended Connection...
Page 67 CHAPTER 2 PIN FUNCTIONS Table 2-5 Pin Input/Output Circuit Types and Recommended Connection When Not Used (2/2) Input/Output Recommended Connection Pin Name Input/Output Circuit Type When Not Used P70/ANI0 to P77/ANI7 20-A Input/output Input : Connect to V or V Output : Leave open ANO0, ANO1 Output...
Page 68 CHAPTER 2 PIN FUNCTIONS Figure 2-1 Pin Input/Output Circuits Type 1-A Type 2-C Pullup Enable Type 2 Schmitt-triggered input with hysteresis characteristics. Schmitt-triggered input with hysteresis characteristics. Type 5-H Type 4-B Pullup Data Enable Data Output Disable IN/OUT Output Disable Push-pull output allowing output to be set to high impedance (P-ch &...
Page 69: Cautions
CHAPTER 2 PIN FUNCTIONS 2.4 CAUTIONS (1) When connecting unused pins, if the input/output mode is undefined for an input/output alternate-function pin, it should be connected to V with a resistor of several tens of kΩ (especially when the reset input pin becomes the low-level input voltage or over upon powering on, and when input/output is switched by software.) (2) P60 to P63 of the µ...
Page 70: Chapter 3 Cpu Architecture
CHAPTER 3 CPU ARCHITECTURE 3.1 MEMORY SPACE The µ PD784038 can access a 1-Mbyte memory space. The mapping of the internal data area (special function registers and internal RAM) depends on the LOCATION instruction. A LOCATION instruction must be executed after reset release, and can only be used once.
Page 71 CHAPTER 3 CPU ARCHITECTURE (1) When LOCATION 0H instruction is executed • Internal memory The internal data area and internal ROM area are follows: Parts Number Internal Data Area Internal ROM Area µ PD784031 0F700H to 0FFFFH — µ PD784035 00000H to 0BFFFH µ...
Page 72 When LOCATION 0H Instruction Is Executed When Location 0FH Instruction Is Executed F F F F F H F F F F F H Special Function Registers (SFRs) F F F D F H F F F D 0 H (256 bytes) F F F 0 0 H F F E F F H...
Page 73 When LOCATION 0H Instruction Is Executed When Location 0FH Instruction Is Executed F F F F F H F F F F F H Special Function Registers (SFRs) F F F D F H Note 1 F F F D 0 H (256 bytes) F F F 0 0 H F F E F F H...
Page 74 When LOCATION 0H Instruction Is Executed When Location 0FH Instruction Is Executed F F F F F H F F F F F H Special Function Registers (SFRs) F F F D F H Note 1 F F F D 0 H (256 bytes) F F F 0 0 H F F E F F H...
Page 75 When LOCATION 0H Instruction Is Executed When Location 0FH Instruction Is Executed F F F F F H F F F F F H Special Function Registers (SFRs) F F F D F H Note 1 F F F D 0 H (256 bytes) F F F 0 0 H F F E F F H...
Page 76 When LOCATION 0H Instruction Is Executed When Location 0FH Instruction Is Executed F F F F F H F F F F F H Special Function Registers (SFRs) F F F D F H Note 1 F F F D 0 H (256 bytes) F F F 0 0 H 0 F E F F H...
Page 77: Internal Rom Area
CHAPTER 3 CPU ARCHITECTURE 3.2 INTERNAL ROM AREA The µ PD784038 Subseries products shown below incorporate ROM which is used to store programs, table data, etc. If the internal ROM area and internal data area overlap when the LOCATION 0H instruction is executed, the internal data area is accessed, and the overlapping part of the internal ROM area cannot be accessed.
Page 78: Base Area
CHAPTER 3 CPU ARCHITECTURE 3.3 BASE AREA The space from 0 to FFFFH comprises the base area. The base area is the object for the following uses: • Reset entry address • Interrupt entry address • CALLT instruction entry address •...
Page 79: Callt Instruction Table Area
CHAPTER 3 CPU ARCHITECTURE Table 3-1 Vector Table Vector Table Address Interrupt Cause 0003CH Operand error 0003EH 00000H Reset (RESET input) 00002H 00004H 00006H INTP0 00008H INTP1 0000AH INTP2 0000CH INTP3 0000EH INTC00 00010H INTC01 00012H INTC10 00014H INTC11 00016H INTC20 00018H INTC21...
Page 80: Internal Data Area
CHAPTER 3 CPU ARCHITECTURE 3.4 INTERNAL DATA AREA The internal data area consists of the internal RAM area and special function register area (see Figures 3-1 to 3-5). The final address of the internal data area can be specified by means of the LOCATION instruction as either 0FFFFH (when a LOCATION 0H instruction is executed) or FFFFFH (when a LOCATION 0FH instruction is executed).
Page 81 CHAPTER 3 CPU ARCHITECTURE The internal RAM memory map is shown in Figure 3-6. Figure 3-6 Internal RAM Memory Map 00FEFFH General-Purpose Register Area 00FE80H Short Direct Addressing 1 Permissible Range Note 1 00FE2FH Macro Service Control Word Area 00FE06H 00FE00H Internal High-Speed RAM 00FDFFH...
Page 82: Special Function Register (Sfr) Area
CHAPTER 3 CPU ARCHITECTURE (1) Internal high-speed RAM (IRAM) The internal high-speed RAM (IRAM) allows high-speed accesses to be made. The short direct addressing mode for high- speed accesses can be used on FD20H to FEFFH in this area. There are two kinds of short direct addressing mode, short direct addressing 1 and short direct addressing 2, according to the target address.
Page 83: External Memory Space
CHAPTER 3 CPU ARCHITECTURE 3.5 EXTERNAL MEMORY SPACE The external memory space is a memory space that can be accessed in accordance with the setting of the memory extension mode register (MM). It can store programs, table data, etc., and can have peripheral I/O devices allocated to it. 3.6 µ...
Page 84: Control Registers
CHAPTER 3 CPU ARCHITECTURE 3.7 CONTROL REGISTERS Control registers consist of the program counter (PC), program status word (PSW), and stack pointer (SP). 3.7.1 Program Counter (PC) This is a 20-bit binary counter that holds address information on the next program to be executed (see Figure 3-8). Normally, the PC is incremented automatically by the number of bytes in the fetched instruction.
Page 85 CHAPTER 3 CPU ARCHITECTURE (2) Parity/overflow flag (P/V) The P/V flag performs the following two kinds of operation associated with execution of an operation instruction. The status of the P/V flag can be tested with a conditional branch instruction. • Parity flag operation Set (to 1) when the number of bits set (to 1) as the result of execution of a logical operation instruction, shift/rotate instruction, or a CHKL or CHKLA instruction is even, and reset (to 0) if odd.
Page 86 CHAPTER 3 CPU ARCHITECTURE (5) Register set selection flag (RSS) The RSS flag specifies the general-purpose registers that function as X, A, C, and B, and the general-purpose register pairs (16-bit) that function as AX and BC. This flag is provided to maintain compatibility with the 78K/III Series, and must be set to 0 except when using a 78K/III Series program.
Page 87: Use Of Rss Bit
CHAPTER 3 CPU ARCHITECTURE 3.7.3 Use of RSS Bit Basically, the RSS bit should be fixed at 0 at all times. The following explanation refers to the case where a 78K/III Series program is used, and the program used sets the RSS bit to 1.
Page 88 Registers used other than those mentioned above are always the same irrespective of the value of the RSS bit. With the NEC Electronics assembler (RA78K4), the register operation code generated when the A, X, B, C, AX, and BC registers are described by those names is determined by the assembler RSS pseudo-instruction.
Page 89: Stack Pointer (Sp)
CHAPTER 3 CPU ARCHITECTURE (3) Operating precautions Switching the RSS bit has the same effect as having two register sets. However, when writing a program, care must be taken to ensure that the static program description and dynamic RSS bit changes at the time of program execution always coincide.
Page 90 CHAPTER 3 CPU ARCHITECTURE Figure 3-11 Data Saved to Stack Area PUSH sfr Instruction PUSH sfrp Instruction Stack Stack ↓ ↓ Upper Byte SP – 1 SP – 1 ↓ SP ← SP – 1 SP – 2 Lower Byte SP ←...
Page 91 CHAPTER 3 CPU ARCHITECTURE Figure 3-12 Data Restored from Stack Area POP sfr Instruction POP sfrp Instruction Stack Stack SP ← SP + 1 SP ← SP + 2 SP + 1 Upper Byte SP + 1 ↑ ↑ Lower Byte POP rg Instruction POP PSW Instruction Stack...
Page 92: General Registers
CHAPTER 3 CPU ARCHITECTURE 3.8 GENERAL REGISTERS 3.8.1 Configuration There are sixteen 8-bit general-purpose registers, and two 8-bit general-purpose registers can be used together as a 16-bit general-purpose register. In addition, four of the 16-bit general-purpose registers can be combined with an 8-bit register for address extension, and used as 24-bit address specification registers.
Page 93 CHAPTER 3 CPU ARCHITECTURE Figure 3-14 General-Purpose Register Addresses 8-Bit Processing 16-Bit Processing Note FEFFH RBNK0 H (R15) L (R14) HL (RP7) (FH) (EH) (EH) RBNK1 D (R13) E (R12) DE (RP6) (DH) (CH) (CH) RBNK2 UP (RP5) (BH) (AH) (AH) RBNK3 VP (RP4)
Page 94: Functions
CHAPTER 3 CPU ARCHITECTURE 3.8.2 Functions In addition to being manipulated in 8-bit units, the general-purpose registers can also be manipulated in 16-bit units by pairing two 8-bit registers. Also, four of the 16-bit registers can be combined with an 8-bit register for address extension and manipulated in 24-bit units.
Page 95 CHAPTER 3 CPU ARCHITECTURE VVP (RG4): • Has a pointer function, and operates as the register that specifies the base address in register indirect addressing, based addressing and based indexed addressing. UUP (RG5): • Has a user stack pointer function, and enables a stack separate from the system stack to be implemented by means of the PUSHU and POPU instructions.
Page 96 CHAPTER 3 CPU ARCHITECTURE In addition to the function name that emphasizes the specific function of the register (X, A, C, B, E, D, L, H, AX, BC, VP, UP, DE, HL, VVP, UUP, TDE, WHL), each register can also be described by its absolute name (R0 to R15, RP0 to RP7, RG4 to RG7). The correspondence between these names is shown in Table 3-4.
Page 97: Special Function Registers (Sfrs)
A list of special function registers (SFRs) is given in Table 3-5. The meaning of the items in the table is as explained below. • Symbol ....... Symbol that indicates the incorporated SFR. This is a reserved word in the NEC Electronics assembler (RA78K4).
Page 98 CHAPTER 3 CPU ARCHITECTURE Table 3-5 List of Special Function Registers (SFRs) (1/4) Manipulable Bit Units Note 1 Address Special Function Register (SFR) Name Symbol After Reset 1 Bit 8 Bits 16 Bits √ √ 0FF00H Port 0 — Undefined √...
Page 99 CHAPTER 3 CPU ARCHITECTURE Table 3-5 List of Special Function Registers (SFRs) (2/4) Manipulable Bit Units Note 1 Address Special Function Register (SFR) Name Symbol After Reset 1 Bit 8 Bits 16 Bits √ 0FF36H Capture register (timer/counter 0) CR02 —...
Page 100 CHAPTER 3 CPU ARCHITECTURE Table 3-5 List of Special Function Registers (SFRs) (3/4) Manipulable Bit Units Note 1 After Reset Address Special Function Register (SFR) Name Symbol 1 Bit 8 Bits 16 Bits √ √ 0FF84H Clocked serial interface mode register 1 CSIM1 —...
Page 101 CHAPTER 3 CPU ARCHITECTURE Table 3-5 List of Special Function Registers (SFRs) (4/4) Manipulable Bit Units Note 1 Address Special Function Register (SFR) Name Symbol After Reset 1 Bit 8 Bits 16 Bits √ √ 0FFCDH Refresh area specification register —...
Page 102: Cautions
CHAPTER 3 CPU ARCHITECTURE 3.10 CAUTIONS (1) Program fetches cannot be performed from the internal high-speed RAM area (0FD00H to 0FEFFH when the LOCATION 0H instruction is executed; FFD00H to FFEFFH when the LOCATION 0FH instruction is executed). (2) Special function registers (SFRs) Note Addresses onto which SFRs are not assigned should not be accessed in the area 0FF00H to 0FFFFH .
Page 103 CHAPTER 3 CPU ARCHITECTURE Table 3-6 Limits of Reading Timer Register (√: Can be read, ×: Must not be read) Timer Count Clock √ √ × × √ √ √ × √ √ √ √ Remarks 1. f : Oscillation frequency 2.
Page 104: Chapter 4 Clock Generator
CHAPTER 4 CLOCK GENERATOR 4.1 CONFIGURATION AND FUNCTION The clock generator generates and controls the internal clock and internal system clock supplied to the CPU and on-chip hardware. The clock generator block diagram is shown in Figure 4-1. Figure 4-1 Clock Generator Block Diagram Internal Bus OSTS STBC...
Page 105 CHAPTER 4 CLOCK GENERATOR Figure 4-2 Clock Oscillator External Circuitry (a) Crystal/ceramic resonator oscillation µ PD784038 (b) External clock EXTC bit of .OSTS = 1 EXTC bit of .OSTS = 0 µ µ PD784038 PD784038 Open Cautions 1. The oscillator should be as close as possible to the X1 and X2 pins. 2.
Page 106: Control Registers
Because the operand error interrupt occurs only when the program hangs up (only the correct dedicated instruction is generated with the NEC Electronics assembler RA78K4 when MOV STBC, #byte is described), make sure that the operand error interrupt processing program initializes the system.
Page 107: Oscillation Stabilization Time Specification Register (Osts)
CHAPTER 4 CLOCK GENERATOR 4.2.2 Oscillation Stabilization Time Specification Register (OSTS) OSTS is a register used to specify the operation of the oscillator. The EXTC bit of the OSTS specifies whether a crystal/ ceramic resonator or an external clock is used. The STOP mode can be set during use of external clock input, only when the EXTC bit is set (to 1).
Page 108: Clock Generator Operation
CHAPTER 4 CLOCK GENERATOR 4.3 CLOCK GENERATOR OPERATION 4.3.1 Clock Oscillator (1) When using crystal/ceramic oscillation The clock oscillation circuit starts oscillating when the RESET signal is input, and stops oscillation when the STOP mode is set by the standby control register (STBC). Oscillation is resumed when the STOP mode is released. (2) When using external clock The clock oscillation circuits supplies the clock input from the X1 pin to the internal circuitry when the RESET signal is input.
Page 109: Cautions
CHAPTER 4 CLOCK GENERATOR 4.4 CAUTIONS The following cautions apply to the clock generator. 4.4.1 When an External Clock is Input (1) If the STOP mode is used with external clock input, the EXTC bit of the oscillation stabilization time specification register (OSTS) must be set (to 1).
Page 110: When Crystal/Ceramic Oscillation Is Used
CHAPTER 4 CLOCK GENERATOR 4.4.2 When Crystal/Ceramic Oscillation is Used (1) As the oscillator is a high-frequency analog circuit, considerable care is required. The following points, in particular, require attention. • The wiring should be kept as short as possible. •...
Page 111 CHAPTER 4 CLOCK GENERATOR Figure 4-7 Incorrect Example of Resonator Connection (a) Wiring of connected circuits is too long (b) Crossed signal lines µ µ PD748038 PD784038 (c) Wiring near high alternating current (d) Current flowing through ground line of oscillation circuit (Potentials at points A, B, and C fluctuate) µ...
Page 112 CHAPTER 4 CLOCK GENERATOR (2) When the device is powered on, and when restoring from the STOP mode, sufficient time must be allowed for the oscillation to stabilize. Generally speaking, the time required for oscillation stabilization is several milliseconds when a crystal resonator is used, and several hundred microseconds when a ceramic resonator is used.
Page 113: Chapter 5 Port Functions
CHAPTER 5 PORT FUNCTIONS 5.1 DIGITAL INPUT/OUTPUT PORTS The µ PD784038 is provided with the ports shown in Figure 5-1, enabling various kinds of control to be performed. The function of each port is shown in Table 5-1. For ports 0 to 6, use of an internal pull-up resistor can be specified by software when used as input ports.
Page 114 CHAPTER 5 PORT FUNCTIONS Table 5-1 Port Functions Port Name Pin Names Functions Software Pull-up Specification Port 0 P00 to P07 • Input or output specifiable bit-wise. Input mode pins specified at once • Can also operate as 4-bit real-time output ports (P00 to P03, P04 to P07).
Page 115: Port 0
CHAPTER 5 PORT FUNCTIONS 5.2 PORT 0 Port 0 is an 8-bit input/output port with an output latch, and has direct transistor drive capability. Input/output can be specified bit-wise by means of the port 0 mode register (PM0). Each pin incorporates a software programmable pull-up resistor. P00 to P03 and P04 to P07 can output the buffer register (P0L, P0H) contents at any time interval as 4-bit real-time output ports or one 8-bit real-time output port.
Page 116: I/O Mode/Control Mode Setting
CHAPTER 5 PORT FUNCTIONS 5.2.2 I/O Mode/Control Mode Setting The port 0 input/output mode is set by means of the port 0 mode register (PM0) as shown in Figure 5-3. Figure 5-3 Port 0 Mode Register (PM0) Format Address After Reset PM07 PM06 PM05...
Page 117 CHAPTER 5 PORT FUNCTIONS (2) When set as an input port The port pin level can be loaded into an accumulator by means of a transfer instruction, etc. In this case, too, writes can be performed to the output latch, and data transferred from the accumulator by a transfer instruction, etc., is stored in all output latches irrespective of the port input/output specification.
Page 118: Internal Pull-Up Resistors
CHAPTER 5 PORT FUNCTIONS 5.2.4 Internal Pull-Up Resistors Port 0 incorporates pull-up resistors. Use of these internal resistors when pull-up is necessary enables the number of parts and the mounting area to be reduced. Whether or not an internal pull-up resistor is to be used can be specified for each pin by means of the PUO0 bit of the pull- up resistor option register (PUO) and the port 0 mode register (PM0).
Page 119: Transistor Drive
CHAPTER 5 PORT FUNCTIONS 5.2.5 Transistor Drive In port 0, the output buffer high-level side drive capability has been increased, allowing active-high direct transistor drive. An example of the connection is shown in Figure 5-8. Figure 5-8 Example of Transistor Drive Load User’s Manual U11316EJ4V1UD...
Page 120: Port 1
CHAPTER 5 PORT FUNCTIONS 5.3 PORT 1 Port 1 is an 8-bit input/output port with an output latch. Input/output can be specified bit-wise by means of the port 1 mode register (PM1). Each pin incorporates a programmable pull-up resistor. This port has direct LED drive capability. In addition to their input/output port function, P10 to P14 also have an alternate function as PWM output pins and serial interface pins.
Page 121: Hardware Configuration
CHAPTER 5 PORT FUNCTIONS 5.3.1 Hardware Configuration The port 1 hardware configuration is shown in Figures 5-9 to 5-13. Figure 5-9 Block Diagram of P10 and P11 (Port 1) Pull-Up Resistor Option Register PUO1 ENn (PWMC) Port 1 Mode Register PM1n Output Latch Selector...
Page 122 CHAPTER 5 PORT FUNCTIONS Figure 5-10 Block Diagram of P12 (Port 1) Pull-Up Resistor Option Register PUO1 Port 1 Mode Control Register PM12 PMC1 Port 1 Mode Control Register PMC12 External SCK2 PMC1 SCK2 Internal Output Output Latch Selector ASCK2, SCK2 Input User’s Manual U11316EJ4V1UD...
Page 123 CHAPTER 5 PORT FUNCTIONS Figure 5-11 Block Diagram of P13 (Port 1) Pull-Up Resistor Option Register PUO1 Port 1 Mode Register PM13 Port 1 Mode Control Register PMC1 PMC13 PMC1 Internal Output Latch SI2, RxD2 Input User’s Manual U11316EJ4V1UD...
Page 124 CHAPTER 5 PORT FUNCTIONS Figure 5-12 Block Diagram of P14 (Port 1) Pull-Up Resistor Option Register PUO1 Port 1 Mode Register PM14 Port 1 Mode Control Register PMC1 PMC14 PMC1 TxD2/SO2 Output Internal Selector Output Latch User’s Manual U11316EJ4V1UD...
Page 125 CHAPTER 5 PORT FUNCTIONS Figure 5-13 Block Diagram of P15 to P17 (Port 1) Pull-Up Resistor Option Register PUO1 Port 1 Mode Register PM1n Output Latch Internal n = 5 to 7 User’s Manual U11316EJ4V1UD...
Page 126: I/O Mode/Control Mode Setting
CHAPTER 5 PORT FUNCTIONS 5.3.2 I/O Mode/Control Mode Setting The port 1 input/output mode is set for each pin by means of the port 1 mode register (PM1) as shown in Figure 5-14. In addition to their input/output port function, P10 and P11 also have an alternate function as PWM signal output pins, and the control mode is specified by means of the PWM control register (PWMC) as shown in Table 5-4.
Page 127: Operating Status
CHAPTER 5 PORT FUNCTIONS 5.3.3 Operating Status Port 1 is an input/output port. Pins P10 and P11 have an alternate function as PWM signal output pins, and pins P12 to P14 have an alternate function as serial interface pins. (1) When set as an output port The output latch is enabled, and data transfers between the output latch and accumulator are performed by means of transfer instructions.
Page 128 CHAPTER 5 PORT FUNCTIONS Caution A bit manipulation instruction manipulates one bit as the result, but accesses the port in 8-bit units. Therefore, if a bit manipulation instruction is used on a port that has the I/O mode or port mode and control mode, the contents of the output latch of the pin set in the input mode or control mode become undefined (excluding bits manipulated with a SET1 or CLR1 instruction, etc.).
Page 129: Internal Pull-Up Resistors
CHAPTER 5 PORT FUNCTIONS 5.3.4 Internal Pull-Up Resistors Port 1 incorporates pull-up resistors. Use of these internal resistors when pull-up is necessary enables the number of parts and the mounting area to be reduced. Whether or not an internal pull-up resistor is to be used can be specified for each pin by means of the PUO1 bit of the pull- up resistor option register (PUO) and the port 1 mode register (PM1).
Page 130: Direct Led Drive
CHAPTER 5 PORT FUNCTIONS 5.3.5 Direct LED Drive In port 1, the output buffer low-level side drive capability has been reinforced allowing active-low direct LED drive. An example of such use is shown in Figure 5-21. Figure 5-21 Example of Direct LED Drive µ...
Page 131: Port 2
CHAPTER 5 PORT FUNCTIONS 5.4 PORT 2 Port 2 is an 8-bit input-only port. P22 to P27 incorporate a software programmable pull-up resistor. As well as operating as input ports, port 2 pins also operate as control signal input pins, such as external interrupt signal pins (see Table 5-5). All 8 pins are Schmitt-triggered inputs to prevent malfunction due to noise.
Page 132: Hardware Configuration
CHAPTER 5 PORT FUNCTIONS (iii) CI (Clock Input) The timer/counter 2 external clock input pin. (iv) ASCK (Asynchronous Serial Clock) The external baud rate clock input pin. (v) SCK1 (Serial Clock 1) The serial clock input/output pin (in 3-wire serial I/O 1 mode). (vi) SI0 (Serial Input 0) The serial data input pin (in 3-wire serial I/O 0 mode).
Page 133 CHAPTER 5 PORT FUNCTIONS Figure 5-23 Block Diagram of P25 (Port 2) PU02 SCK1 Output Mode Internal SCK1 Output P25/ASCK/SCK1 ASCK/SCK1 Input Edge INTP4 Input Detection Circuit User’s Manual U11316EJ4V1UD...
Page 134: Input Mode/Control Mode Setting
CHAPTER 5 PORT FUNCTIONS 5.4.2 Input Mode/Control Mode Setting Port 2 is an input-only port, and there is no register for setting the input mode. Also, control signal input is always possible, and therefore the signal to be used is determined by the control registers for individual on-chip hardware items.
Page 135 CHAPTER 5 PORT FUNCTIONS Figure 5-26 Pull-Up Specification (Port 2) Input Internal Buffer PUO2 Pull-Up Resistor Option Register (PUO) Caution As P22 to P26 are not pulled up immediately after a reset, an interrupt request flag may be set depending on the function of the alternate-function pins (INTP1 to INTP5).
Page 136: Port 3
µ PD784038Y Subseries only Note Remark Bit 2 (P32) of port 3 is reserved for the NEC Electronics assembler package as “SCL”. It is also defined as a bit type sfr variable by the #pragma sfr command of the C compiler.
Page 137: Hardware Configuration
CHAPTER 5 PORT FUNCTIONS (iv) SO0 (Serial Output 0)/SDA (Serial Data) SO0 is the serial data output pin (in 3-wire serial I/O 0 mode), and SDA is the serial data input/output pin (in 2-wire Note serial I/O mode/I C bus mode µ...
Page 138 CHAPTER 5 PORT FUNCTIONS Figure 5-28 Block Diagram of P31 and P34 to P37 (Port 3) Pull-Up Resistor Option Register PUO3 Port 3 Mode Register PM3n Port 3 Mode Control Register PMC3 PMC3n PMC3 Internal TO, SO1, TxD Output Selector Output Latch n = 1, 4, 5, 6, 7 User’s Manual U11316EJ4V1UD...
Page 139 CHAPTER 5 PORT FUNCTIONS Figure 5-29 Block Diagram of P32 (Port 3) Pull-Up Resistor Option Register PUO3 Port 3 Mode Register PM32 2-wire serial I/O mode or C bus mode SCK0/SCL Input Port 3 Mode Control Register PMC3 Internal PMC32 PMC3 SCK0/SCL Output Output Latch...
Page 140 CHAPTER 5 PORT FUNCTIONS Figure 5-30 Block Diagram of P33 (Port 3) Pull-Up Resistor Option Register PUO3 Port 3 Mode Register PM33 Port 3 Mode Control Register PMC3 2-wire serial I/O mode or I C bus mode PMC33 PMC3 Note SO0/SDA Input Mode Internal SO0/SDA Output...
Page 141: I/O Mode/Control Mode Setting
CHAPTER 5 PORT FUNCTIONS 5.5.2 I/O Mode/Control Mode Setting The port 3 input/output mode is set for each pin by means of the port 3 mode register (PM3) as shown in Figure 5-31. In addition to their input/output port function, port 3 pins also have an alternate function as various control signal pins, and the control mode is specified by means of the port 3 mode control register (PMC3) as shown in Figure 5-32.
Page 142: Operating Status
CHAPTER 5 PORT FUNCTIONS 5.5.3 Operating Status Port 3 is an input/output port, with an alternate function as various control pins. (1) When set as an output port The output latch is enabled, and data transfers between the output latch and accumulator are performed by means of transfer instructions.
Page 143 When PM3 is reset (to 0), the µ PD784038 internal control signal status can be read by executing a port read instruction. Remark For bit 2 (P32) of port 3, the name “SCL” is a reserved word in the NEC Electronics assembler package. In the C compiler, it is defined as a bit-type sfr variable by the # pragma sfr directive.
Page 144: Internal Pull-Up Resistors
CHAPTER 5 PORT FUNCTIONS 5.5.4 Internal Pull-Up Resistors Port 3 incorporates pull-up resistors. Use of these internal resistors when pull-up is necessary enables the number of parts and the mounting area to be reduced. Whether or not an internal pull-up resistor is to be used can be specified for each pin by means of the PUO3 bit of the pull- up resistor option register (PUO) and the port 3 mode register (PM3).
Page 145: Port 4
CHAPTER 5 PORT FUNCTIONS 5.6 PORT 4 Port 4 is an 8-bit input/output port with an output latch. Input/output can be specified bit-wise by means of the port 4 mode register (PM4). Each pin incorporates a software programmable pull-up resistor. This port has direct LED drive capability. Port 4 also functions as the time division address/data bus (AD0 to AD7) by the memory extension mode register (MM) when external memory or I/Os are extended.
Page 146 CHAPTER 5 PORT FUNCTIONS Figure 5-38 Port 4 Block Diagram Pull-Up Resistor Option Register PUO4 MM0 to MM3 Port 4 Mode Register PM4n Output Latch Internal Data n = 0 to 7 Input/ Output Control Circuit Internal Address User’s Manual U11316EJ4V1UD...
Page 147: I/O Mode/Control Mode Setting
CHAPTER 5 PORT FUNCTIONS 5.6.2 I/O Mode/Control Mode Setting The port 4 input/output mode is set for each pin by means of the port 4 mode register (PM4) as shown in Figure 5-39. When port 4 is used as the address/data bus, it is set by means of the memory extension mode register (MM: See Figure 23-1) as shown in Table 5-8.
Page 148: Operating Status
CHAPTER 5 PORT FUNCTIONS 5.6.3 Operating Status Port 4 is an input/output port, with an alternate function as the address/data bus (AD0 to AD7). (1) When set as an output port The output latch is enabled, and data transfers between the output latch and accumulator are performed by means of transfer instructions.
Page 149 CHAPTER 5 PORT FUNCTIONS (2) When set as an input port The port pin level can be loaded into an accumulator by means of a transfer instruction. In this case, too, writes can be performed to the output latch, and data transferred from the accumulator by a transfer instruction, etc., is stored in all output latches irrespective of the port input/output specification.
Page 150: Internal Pull-Up Resistors
CHAPTER 5 PORT FUNCTIONS 5.6.4 Internal Pull-Up Resistors Port 4 incorporates pull-up resistors. Use of these internal resistors when pull-up is necessary enables the number of parts and the mounting area to be reduced. Whether or not an internal pull-up resistor is to be used can be specified for each pin by means of the PUO4 bit of the pull- up resistor option register (PUO) and the port 4 mode register (PM4).
Page 151: Direct Led Drive
CHAPTER 5 PORT FUNCTIONS 5.6.5 Direct LED Drive In port 4, the output buffer low-level side drive capability has been reinforced, allowing active-low direct LED drive. An example of such use is shown in Figure 5-44. Figure 5-44 Example of Direct LED Drive µ...
Page 152 CHAPTER 5 PORT FUNCTIONS Figure 5-45 Port 5 Block Diagram Pull-Up Resistor Option Register PUO5 MM0 to MM3 Port 5 Mode Register PM5n Internal Output Latch Data n = 0 to 7 Input/ Output Control Circuit Internal Address User’s Manual U11316EJ4V1UD...
Page 153: I/O Mode/Control Mode Setting
CHAPTER 5 PORT FUNCTIONS 5.7.2 I/O Mode/Control Mode Setting The port 5 input/output mode is set for each pin by means of the port 5 mode register (PM5) as shown in Figure 5-46. When port 5 pins can be used as port or address pins in 2-bit units, the setting is performed by means of the memory extension mode register (MM: See Figure 23-1) as shown in Table 5-10.
Page 154: Operating Status
CHAPTER 5 PORT FUNCTIONS 5.7.3 Operating Status Port 5 is an input/output port, with an alternate function as the address bus (A8 to A15). (1) When set as an output port The output latch is enabled, and data transfers between the output latch and accumulator are performed by means of transfer instructions.
Page 155 CHAPTER 5 PORT FUNCTIONS (2) When set as an input port The port pin level can be loaded into an accumulator by means of a transfer instruction. In this case, too, writes can be performed to the output latch, and data transferred from the accumulator by a transfer instruction, etc., is stored in all output latches irrespective of the port input/output specification.
Page 156: Internal Pull-Up Resistors
CHAPTER 5 PORT FUNCTIONS 5.7.4 Internal Pull-Up Resistors Port 5 incorporates pull-up resistors. Use of these internal resistors when pull-up is necessary enables the number of parts and the mounting area to be reduced. Whether or not an internal pull-up resistor is to be used can be specified for each pin by means of the PUO5 bit of the pull- up resistor option register (PUO) and the port 5 mode register (PM5).
Page 157: Direct Led Drive
CHAPTER 5 PORT FUNCTIONS 5.7.5 Direct LED Drive In port 5, the output buffer low-level side drive capability has been reinforced, allowing active-low direct LED drive. An example of such use is shown in Figure 5-51. Figure 5-51 Example of Direct LED Drive µ...
Page 158: Port 6
CHAPTER 5 PORT FUNCTIONS 5.8 PORT 6 • With µ PD784031 P60 to P63 are output port pins and P66 and P67 are input/output port pins with output latch. P64 to P67 incorporate a software programmable pull-up resistor. In addition to the functions as port pins, these pins also have various alternate-function control signal pin functions, as shown in Table 5-11.
Page 159 CHAPTER 5 PORT FUNCTIONS Table 5-12 P60 to P65 Control Pin Specification MM Bits Operating Mode Port (P60 to P65) Port (P60 to P63) Port (a) Port mode • With µ PD784031 Each port not specified as control mode, P66 and P67 serve as output port pins, and P66 and P67 can be specified as input/output bit-wise by means of the port 6 mode register (PM6).
Page 160: Hardware Configuration
CHAPTER 5 PORT FUNCTIONS (vii) REFRQ (Refresh Request) This pin outputs refresh pulses to pseudo-static memory when this memory is connected to it externally. Operates in accordance with the refresh mode register (RFM). 5.8.1 Hardware Configuration The port 6 hardware configuration is shown in Figures 5-52 to 5-55. Figure 5-52 Block Diagram of P60 to P63 (Port 6) Pull-Up Resistor Option Register PUO6...
Page 161 CHAPTER 5 PORT FUNCTIONS Figure 5-53 Block Diagram of P64 and P65 (Port 6) Pull-Up Resistor Option Register PUO6 Port 6 Mode Register PM64 (PM65) External Extension Mode RD Signal (WR Signal) Internal Selector Output Latch (P65) (P65) User’s Manual U11316EJ4V1UD...
Page 162 CHAPTER 5 PORT FUNCTIONS Figure 5-54 Block Diagram of P66 (Port 6) Pull-Up Resistor Option Register PUO6 Port 6 Mode Register PM66 Hold Enabled Mode External Wait Specification Internal Output Latch Wait Input Hold Request Input User’s Manual U11316EJ4V1UD...
Page 163 CHAPTER 5 PORT FUNCTIONS Figure 5-55 Block Diagram of P67 (Port 6) Pull-Up Resistor Option Register PUO6 Port 6 Mode Register PM67 Hold Enabled Mode Refresh Mode Refresh Signal Internal Hold Acknowledge Signal Selector Output Latch User’s Manual U11316EJ4V1UD...
Page 164: I/O Mode/Control Mode Setting
CHAPTER 5 PORT FUNCTIONS 5.8.2 I/O Mode/Control Mode Setting The port 6 input/output mode is set by means of the port 6 mode register (PM6) as shown in Figure 5-56. Operations for operating port 6 as control pins are shown in Table 5-13. With the µ...
Page 165: Operating Status
CHAPTER 5 PORT FUNCTIONS Figure 5-56 Port 6 Mode Register (PM6) Format Address After Reset PM67 PM66 PM65 PM64 PM63 PM62 PM61 PM60 0FF26H P6n Pin Input/Output Mode PM6n Specification (n = 0 to 7) Output mode (output buffer on) Input mode (output buffer off) Remark The lower 4 bits (P60 to P63) of the µ...
Page 166 CHAPTER 5 PORT FUNCTIONS (2) When set as an input port The port pin level can be loaded into an accumulator by means of a transfer instruction. In this case, too, writes can be performed to the output latch, and data transferred from the accumulator by a transfer instruction, etc., is stored in all output latches irrespective of the port input/output specification.
Page 167: Internal Pull-Up Resistors
CHAPTER 5 PORT FUNCTIONS 5.8.4 Internal Pull-Up Resistors P60 to P67 (P64 to P67 with the µ PD784031) incorporate pull-up resistors. Use of these internal resistors when pull-up is necessary enables the number of parts and the mounting area to be reduced. Whether or not an internal pull-up resistor is to be used can be specified for each pin by means of the PUO6 bit of the pull- up resistor option register (PUO) and the port 6 mode register (PM6).
Page 168: Port 7
CHAPTER 5 PORT FUNCTIONS 5.9 PORT 7 Port 7 is an 8-bit input/output port. In addition to operating as an input/output port, it also operates as the A/D converter analog input pins (ANI0 to ANI7). Input/output can be specified bit-wise by means of the port 7 mode register (PM7). Pin levels can be read or tested at any time irrespective of alternate-function pin operations.
Page 169: I/O Mode/Control Mode Setting
CHAPTER 5 PORT FUNCTIONS 5.9.2 I/O Mode/Control Mode Setting The port 7 input/output mode is set for each pin by means of the port 7 mode register (PM7) as shown in Figure 5-62. In addition to the operation of port 7 as an input/output port, analog signal input can be performed at any time. Mode setting is not necessary.
Page 170: Internal Pull-Up Resistors
CHAPTER 5 PORT FUNCTIONS (2) When set as an input port The port pin level can be loaded into an accumulator by means of a transfer instruction. In this case, too, writes can be performed to the output latch, and data transferred from the accumulator by a transfer instruction, etc., is stored in all output latches-irrespective of the port input/output specification.
Page 171: Port Output Check Function
CHAPTER 5 PORT FUNCTIONS 5.10 PORT OUTPUT CHECK FUNCTION The µ PD784038 has a function for reading and testing output port pin levels in order to improve the reliability of application systems. It is therefore possible to check the output data and the actual pin status as required. If there is a mismatch, appropriate action can be taken, such as replacement with another system.
Page 172: Cautions
CHAPTER 5 PORT FUNCTIONS 5.11 CAUTIONS All port pins become high-impedance after RESET signal input (internal pull-up resistors are disconnected from the pins). If there is a problem with pins becoming high-impedance during RESET input, this should be handled with external circuitry.
Page 173: Chapter 6 Real-Time Output Function
CHAPTER 6 REAL-TIME OUTPUT FUNCTION 6.1 CONFIGURATION AND FUNCTION The real-time output function is implemented by hardware, including primarily port 0 and the port 0 buffer registers (P0H, P0L), shown in Figure 6-1. The real-time output function refers to the transfer to the output latch by hardware of data prepared in the P0H and P0L beforehand, simultaneously with the generation of an interrupt from timer/counter 1 or external interrupt, and its output off-chip.
Page 174 Internal Bus RTPC BYTE P0MH EXTR TRGP0 P0ML Port 0 Buffer Registers INTC11 BYTE 4-Bit Real-Time Output (P0H) P0MH INTP0 4-Bit Real-Time Output (P0L) INTC10 Selector Selector 8-Bit Real-Time Output (P0) P0ML EXTR Output Latch TRGP0 P03 P02 P01 P00...
Page 175: Real-Time Output Port Control Register (Rtpc)
CHAPTER 6 REAL-TIME OUTPUT FUNCTION 6.2 REAL-TIME OUTPUT PORT CONTROL REGISTER (RTPC) The RTPC is an 8-bit register that specifies the function of port 0. RTPC can be read or written to by an 8-bit manipulation instruction or bit-manipulation instruction. Figure 6-2 shows the format of RTPC.
Page 176: Real-Time Output Port Accesses
CHAPTER 6 REAL-TIME OUTPUT FUNCTION 6.3 REAL-TIME OUTPUT PORT ACCESSES The port 0 buffer registers (P0H, P0L) are mapped onto mutually independent addresses in the SFR area as shown in Figure 6-3. When the 4-bit × 2-channel real-time output function is specified, data can be set in the P0H, P0L independently of each other.
Page 177 CHAPTER 6 REAL-TIME OUTPUT FUNCTION <Examples of setting data in port 0 buffer registers> • 4-bit × 2-channel operation MOV P0L, #05H ; Sets 0101B in P0L MOV P0H, #0C0H ; Sets 1100B in P0H • 8-bit × 1-channel operation MOV P0L, #0C5H ;...
Page 178: Operation
CHAPTER 6 REAL-TIME OUTPUT FUNCTION 6.4 OPERATION When the port 0 function is specified as the real-time output port, the port 0 buffer register (P0H, P0L) contents are fetched into the output latch and output to the port 0 pins in synchronization with the generation of one of the trigger conditions shown in Table 6-2.
Page 179 CHAPTER 6 REAL-TIME OUTPUT FUNCTION Figure 6-4 Real-Time Output Port Operation Timing CR11 Timer/Counter 1 CR11 CR11 CR11 Timer Start INTC11 Interrupt Request CPU Operation Port 0 Buffer Register Output Latches P07 to P04 Port 0 buffer register and compare register overwrite by software servicing or macro service (see 22.8 MACRO SERVICE FUNCTION ) User’s Manual U11316EJ4V1UD...
Page 180 CHAPTER 6 REAL-TIME OUTPUT FUNCTION Figure 6-5 Real-Time Output Port Operation Timing (2-Channel Independent Control Example) CR10 CR11 Timer/Counter 1 CR10 CR11 CR10 CR11 CR11 Timer Start INTC11 Interrupt Request INTC10 Interrupt Request CPU Operation Port 0 Buffer Register Output Latches P07 to P04 P03 to P00 Port 0 buffer register and compare register overwrite by software servicing or macro...
Page 181: Example Of Use
CHAPTER 6 REAL-TIME OUTPUT FUNCTION 6.5 EXAMPLE OF USE The case in which P00 to P03 are used as a 4-bit real-time output port is shown here. Each time the contents of timer/counter 1 timer register 1 (TM1) and compare register (CR10) match, the contents of port 0 buffer register (P0L) are output to P00 to P03.
Page 182 CHAPTER 6 REAL-TIME OUTPUT FUNCTION Figure 6-7 Real-Time Output Function Control Register Settings RTPC P00 to P03 used as real-time output port Data transfer to output latch from P0L by INTP0 disabled P04 to P07 used as normal output port 4-bit separate real-time output ports selected Figure 6-8 Real-Time Output Function Setting Procedure Real-time output port...
Page 183: Cautions
CHAPTER 6 REAL-TIME OUTPUT FUNCTION Figure 6-9 Interrupt Request Servicing when Real-Time Output Function is Used Timer interrupt Interval time setting Set next value to be output in P0L Return 6.6 CAUTIONS (1) When P0ML and P0MH bits are set (to 1), the corresponding port output buffer is turned on and the port 0 output latch contents are output irrespective of the contents of the port 0 mode register (PM0).
Page 184: Chapter 7 Outline Of Timer/Counter
CHAPTER 7 OUTLINE OF TIMER/COUNTER The µ PD784038 incorporates three timer/counter units and one timer unit. These timer/counter and timer units can be used as seven units of timer/counters because the µ PD784038 supports seven interrupt requests. Table 7-1 Operations of Timer/Counters Name Timer/Counter 0 Timer/Counter 1...
Page 185 CHAPTER 7 OUTLINE OF TIMER/COUNTER Figure 7-1 Timer/Counter Block Diagram Timer/Counter 0 Clear Control Software Trigger Prescaler Timer Register 0 Selector (TM0) Match Compare Register (CR00) Pulse Output Match Compare Register Control (CR01) Capture Register INTC00 INTP3 Edge Detection (CR02) INTC01 INTP3 Timer/Counter 1...
Page 186: Chapter 8 Timer/Counter 0
CHAPTER 8 TIMER/COUNTER 0 8.1 FUNCTIONS Timer/counter 0 is a 16-bit timer/counter. In addition to its basic functions of interval timer, programmable square-wave output, pulse width measurement and event counter, timer/counter 0 can be used for the following functions. • PWM output •...
Page 187 CHAPTER 8 TIMER/COUNTER 0 (2) Programmable square-wave output Outputs square waves independently to the timer output pins (TO0, TO1). Table 8-2 Timer/Counter 0 Programmable Square-Wave Output Setting Range Minimum Pulse Width Maximum Pulse Width × 8/f (0.25 µ s) (16.40 ms) ×...
Page 188 CHAPTER 8 TIMER/COUNTER 0 (3) Pulse width measurement Detects the pulse width of the signal input to the external interrupt request input pin (INTP3). Table 8-3 Timer/Counter 0 Pulse Width Measurement Range Note Measurable Pulse Width Resolution × 8/f (0.25 µ s) (0.25 µ...
Page 189: Configuration
CHAPTER 8 TIMER/COUNTER 0 (5) External event counter Counts the clock pulses input from the external interrupt request input pin (INTP3). The clocks that can be input to timer/counter 0 are shown in Table 8-4. Table 8-4 Timer/Counter 0 Pulse Width Measurement Time When Counting One Edge When Counting Both Edges Maximum frequency...
Page 190 Internal Bus Capture/Compare Control 8/16 Register 0 (CRC0) Timer Output External Interrupt Compare Register ES31 ES30 MOD1 MOD0 CLR01 ENT01 ALV1 ENT00 ALV0 Control Register Mode Register 1 (CR00) (TOC) (INTM1) Edge PWM/PPG P24/INTP3 Detection Output Control Match Output Circuit Control P34/TO0 Circuit...
Page 191 CHAPTER 8 TIMER/COUNTER 0 (1) Timer register 0 (TM0) TM0 is a timer register that counts up using the count clock specified by the low-order 4 bits of prescaler mode register 0 (PRM0). The count operation is stopped or enabled by means of timer control register 0 (TMC0). TM0 can be read only with a 16-bit manipulation instruction.
Page 192 CHAPTER 8 TIMER/COUNTER 0 (5) Output control circuit It is possible to invert the timer output when the compare register (CR00, CR01) register contents and the contents of the timer register (TM0) match. A square wave can be output from the timer output pins (TO0/TO1) in accordance with the setting of the low-order 4 bits of the timer output control register (TOC).
Page 193: Timer/Counter 0 Control Registers
CHAPTER 8 TIMER/COUNTER 0 8.3 TIMER/COUNTER 0 CONTROL REGISTERS (1) Timer control register 0 (TMC0) The timer/counter 0 TM0 count operation is controlled by the low-order 4 bits in the TMC0 (the high-order 4 bits control the count operation of the TM3/TM3W of the timer 3). TMC0 can be read or written to with an 8-bit manipulation instruction or bit manipulation instruction.
Page 194 CHAPTER 8 TIMER/COUNTER 0 (2) Prescaler mode register 0 (PRM0) The count clock of the timer/counter 0, TM0, is specified by the low-order 4 bits of the PRM0 (the high-order 4 bits specify the count clock of the timer 3, TM3/TM3W). PRM0 can be read/written with an 8-bit manipulation instruction.
Page 195 CHAPTER 8 TIMER/COUNTER 0 (3) Capture/compare control register 0 (CRC0) The CRC0 specifies the enabling conditions for the TM0 clear operation by a match signal between the contents of the compare register (CR01) and the timer register 0 (TM0) counter value, and the timer outputs (TO0/TO1) mode. CRC0 can be read/written with an 8-bit manipulation instruction.
Page 196 CHAPTER 8 TIMER/COUNTER 0 (4) Timer output control register (TOC) TOC is an 8-bit register that controls the active level of timer output and output enabling/disabling. The operation of the timer output pins (TO0 and TO1) by the timer/counter 0 is controlled by the low-order 4 bits (the high- order 4 bits control the operation of the timer output pins (TO2 and TO3 by the timer/counter 2).
Page 197 CHAPTER 8 TIMER/COUNTER 0 (5) One-shot pulse output control register (OSPC) The OSPC is an 8-bit register that specifies enabling/disabling of one-shot pulse output by a software trigger and the output level, etc. OSPC can be read or written to with an 8-bit manipulation instruction or bit manipulation instruction. The format of the OSPC is shown in Figure 8-6.
Page 198: 16-Bit Timer Register 0 (Tm0) Operation
CHAPTER 8 TIMER/COUNTER 0 8.4 16-BIT TIMER REGISTER 0 (TM0) OPERATION 8.4.1 Basic Operation In the timer/counter 0 count operation, an up-count is performed using the count clock specified by the low-order 4 bits of prescaler mode register 0 (PRM0). Count operation enabling/disabling is controlled by bit 3 (CE0) of timer control register 0 (TMC0).
Page 199 CHAPTER 8 TIMER/COUNTER 0 Figure 8-7 Basic Operation of Timer Register 0 (TM0) (a) Count started → count stopped → count started Count Clock 100H 101H Count Started Count Stopped Count Started CE0 ← 1 CE0 ← 0 CE0 ← 1 (b) When “1”...
Page 200: Clear Operation
CHAPTER 8 TIMER/COUNTER 0 8.4.2 Clear Operation (1) Clear operation after a match with the compare register The timer register 0 (TM0) can be cleared automatically after a match with the compare register (CR01). When a clearance source arises, TM0 is cleared to 0000H on the next count clock. Therefore, even if a clearance source arises, the value at the point at which the clearance source arose is retained until the next count clock arrives.
Page 201 CHAPTER 8 TIMER/COUNTER 0 Figure 8-9 Clear Operation When CE0 Bit is Cleared (0) (a) Basic operation Count Clock n - 1 (b) Restart before count clock input after clearance Count Clock n - 1 If the CE0 bit is set (to 1) before this count clock, the count starts from 0 on the count clock. (c) Restart after count clock input after clearance Count Clock n - 1...
Page 202: External Event Counter Function
CHAPTER 8 TIMER/COUNTER 0 8.5 EXTERNAL EVENT COUNTER FUNCTION The timer/counter 0 can count clock pulses input from the external interrupt request input pin (INTP3). No special selection method is needed for the external event counter operating mode. When the timer register 0 (TM0) count clock is specified as external clock input by the setting of the low-order 4 bits of prescaler mode register 0 (PRM0), TM0 operates as an external event counter.
Page 203 CHAPTER 8 TIMER/COUNTER 0 Figure 8-10 Timer/Counter 0 External Event Count Timing (2/2) (2) Counting both edges (maximum frequency = f (MIN.) (MIN.) (MIN.) INTP3 3 to 4/f Dn + 1 Dn + 2 Dn + 3 Dn + 4 Dn + 5 Remark ICI: INTP3 input signal after passing through edge detection circuit The TM0 count operation is controlled by the CE0 bit of the timer control register 0 (TMC0) in the same way as with basic...
Page 204 CHAPTER 8 TIMER/COUNTER 0 Figure 8-12 Methods of Enabling the External Event Counter to Distinguish No Valid Edge Input (a) Processing when count is started Start count Clear INTP3 interrupt ; Clear PIF3 to 0 request flag PIF3 ← 0 Start count ;...
Page 205: Compare Register And Capture Register Operation
CHAPTER 8 TIMER/COUNTER 0 8.6 COMPARE REGISTER AND CAPTURE REGISTER OPERATION 8.6.1 Compare Operations Timer/counter 0 performs compare operations in which the value set in compare registers (CR00, CR01) are compared with the timer register 0 (TM0) count value. If the count value of TM0 matches the preset CR0n (n = 0, 1) value as the result of the count operation, a match signal is sent to the output control circuit, and at the same time an interrupt request (INTC00/INTC01) is generated.
Page 206 CHAPTER 8 TIMER/COUNTER 0 Figure 8-14 TM0 Clearance After Match Detection CR01 CR01 CR00 CR00 Count Value Count Start Clear Clear CE0 ← 1 INTC00 Interrupt Request INTC01 Interrupt Request Remark CLR01 = 0 User’s Manual U11316EJ4V1UD...
Page 207: Capture Operations
CHAPTER 8 TIMER/COUNTER 0 8.6.2 Capture Operations Timer/counter 0 performs capture operations in which the timer register 0 (TM0) count value is fetched into the capture register in synchronization with an external trigger, and retained there. A valid edge detected from the input of the external interrupt request input pin (INTP3) is used as the external trigger (capture trigger).
Page 208: Basic Operation Of Output Control Circuit
CHAPTER 8 TIMER/COUNTER 0 8.7 BASIC OPERATION OF OUTPUT CONTROL CIRCUIT The output control circuit controls the timer output pin (TO0/TO1) levels by means of overflow signals or match signals from the compare registers (CR00, CR01). The operation of the output control circuit is determined by the timer output control register (TOC), capture/compare control register 0 (CRC0), and the one-shot pulse output control register (OSPC) (see Table 8-6).
Page 210: Basic Operation
CHAPTER 8 TIMER/COUNTER 0 8.7.1 Basic Operation Setting (to 1) the ENTOn (n = 0, 1) bit of the timer output control register (TOC) enables timer output (TOn: n = 0, 1) to be varied at a timing in accordance with the settings of MOD0, MOD1, and CLR01 bits of capture/compare control register 0 (CRC0) and the one-shot pulse output control register (OSPC).
Page 211: Pwm Output
CHAPTER 8 TIMER/COUNTER 0 Table 8-7 TO0, TO1 Toggle Output (f = 32 MHz) Count Clock Minimum Pulse Width Maximum Interval Time 0.25 µ s 16.40 ms 0.50 µ s 16/f 32.80 ms 1.00 µ s 32/f 65.50 ms 2.00 µ s 64/f 131 ms 4.00 µ...
Page 212 CHAPTER 8 TIMER/COUNTER 0 Table 8-8 TO0, TO1 PWM Cycle (f = 32 MHz) Minimum Pulse Width [ µ s] Count Clock PWM Cycle [s] PWM Frequency [Hz] 0.25 0.02 61.0 0.50 0.03 30.5 1.00 0.07 15.3 2.00 0.13 /128 4.00 0.26 /256...
Page 213 CHAPTER 8 TIMER/COUNTER 0 Figure 8-19 Example of PWM Output When CR00 = FFFFH FFFFH FFFFH FFFFH FFFEH FFFEH Count Clock Cycle T Count Value INTC00 OVF Flag Pulse Width 65,535 × 100 = 99.998 (%) Duty = 65,536 Pulse Cycle = 65,536T Remarks 1.
Page 214 CHAPTER 8 TIMER/COUNTER 0 (2) Rewriting compare registers (CR00, CR01) The output level of the timer output (TOn: n = 0, 1) does not change even if the CR0n (n = 0, 1) value matches the timer register 0 (TM0) value more than once during one PWM output cycle. Figure 8-20 Example of Compare Register (CR00) Rewrite FFFFH FFFFH...
Page 215 CHAPTER 8 TIMER/COUNTER 0 If a value smaller than that of the TM0 is set as the CR0n value, a 100% duty PWM signal will be output. CR0n rewriting should be performed by the interrupt due to a match between TM0 and the CR0n on which the rewrite is performed. Figure 8-21 Example of 100% Duty With PWM Output FFFFH FFFFH...
Page 216 CHAPTER 8 TIMER/COUNTER 0 (3) Stopping PWM output If timer/counter 0 is stopped by clearing (to 0) the CE0 bit of the timer control register 0 (TMC0) during PWM signal output, the active level is output. Figure 8-22 When Timer/Counter 0 is Stopped During PWM Signal Output FFFFH FFFFH CR00...
Page 217: Ppg Output
CHAPTER 8 TIMER/COUNTER 0 8.7.4 PPG Output (1) Basic Operation of PPG Output This function outputs a square-wave with the time determined by compare register CR01 value as one cycle, and the time determined by compare register CR00 value as the pulse width. The PWM cycle output by the PWM is made variable. This signal can only be output from the timer output (TO0).
Page 218 CHAPTER 8 TIMER/COUNTER 0 Table 8-9 TO0 PPG Output (f = 32 MHz) Count Clock Minimum Pulse Width PPG Cycle PPG Frequency 0.25 µ s 0.50 µ s to 16.40 ms 2,000 kHz to 61.0 Hz 0.50 µ s 1.00 µ s to 32.80 ms 1,000 kHz to 30.5 Hz 1.00 µ...
Page 219 CHAPTER 8 TIMER/COUNTER 0 (2) Rewriting compare register (CR00) The output level of the timer output (TO0) does not change even if the CR00 value matches the timer register 0 (TM0) value more than once during one PPG output cycle. Figure 8-25 Example of Compare Register (CR00) Rewrite CR01 CR01...
Page 220 CHAPTER 8 TIMER/COUNTER 0 If a value equal to or less than the TM0 value is written to CR00 before the CR00 and TM0 match, the duty of the PPG cycle will be 100%. CR00 rewriting should be performed by the interrupt due to a match between TM0 and CR00. Figure 8-26 Example of 100% Duty With PPG Output CR01 CR01...
Page 221 CHAPTER 8 TIMER/COUNTER 0 (3) Rewriting compare register (CR01) If the current value of the CR01 is changed to a smaller value, and the CR01 value is made smaller than the timer register 0 (TM0) value, the PPG cycle at that time will be extended to the time equivalent to a full-count by TM0. If CR01 is rewritten after the compare register (CR00) and TM0 match, the output level at this time will be the inactive level until TM0 overflows and becomes 0, and will then return to normal PPG output.
Page 222 CHAPTER 8 TIMER/COUNTER 0 Caution If the PPG cycle is extremely short as compared with the time required to acknowledge an interrupt, the value of CR01 cannot be rewritten by interrupt processing that is performed on coincidence between the timer register (TM0) and compare register (CR01). Use another method (for example, to poll the interrupt request flags by software with all the interrupts masked).
Page 223: Software Triggered One-Shot Pulse Output
CHAPTER 8 TIMER/COUNTER 0 8.7.5 Software Triggered One-Shot Pulse Output In the software triggered one-shot pulse output mode, a one-shot pulse is output by software. When the STn (n = 0/1) bit of the one-shot pulse output control register (OSPC) is set (to 1), timer output pin (TOn: n = 0, 1) is set to the active level.
Page 224: Examples Of Use
CHAPTER 8 TIMER/COUNTER 0 8.8 EXAMPLES OF USE 8.8.1 Operation as Interval Timer (1) When timer register 0 (TM0) is made free-running and a fixed value is added to the compare register (CR0n: n = 0, 1) in the interrupt service routine, TM0 operates as an interval timer with the added fixed value as the cycle (see Figure 8-30). This interval timer can count within the range shown in Table 8-1 (internal system clock f = 32 MHz).
Page 225 CHAPTER 8 TIMER/COUNTER 0 Figure 8-31 Control Register Settings for Interval Timer Operation (1) Capture/compare control register 0 (CRC0) CRC0 TM0 clearing disabled TO0 & TO1 both toggle outputs Figure 8-32 Interval Timer Operation (1) Setting Procedure Interval timer (1) Set count value in CR00 CR00 ←...
Page 226: Operation As Interval Timer (2)
CHAPTER 8 TIMER/COUNTER 0 8.8.2 Operation as Interval Timer (2) TM0 operates as an interval timer that generates interrupts repeatedly with the preset count time as the interval (see Figure 8-34). This interval timer can count within the range shown in Table 8-1 (internal system clock f = 32 MHz).
Page 227 CHAPTER 8 TIMER/COUNTER 0 Figure 8-35 Control Register Settings for Interval Timer Operation (2) Capture/compare control register 0 (CRC0) CRC0 TM0 cleared by match of CR01 & TM0 contents TO0 & TO1 both toggle outputs Figure 8-36 Interval Timer Operation (2) Setting Procedure Interval timer (2) Set count value in CR01 CR01 ←...
Page 228: Pulse Width Measurement Operation
CHAPTER 8 TIMER/COUNTER 0 8.8.3 Pulse Width Measurement Operation In pulse width measurement, the high-level or low-level width of external pulses input to the external interrupt request input pin (INTP3) is measured. Both the high-level and low-level widths of pulses input to the INTP3 pin must be at least 3 system clocks (0.19 µ s: f = 16 MHz);...
Page 229 CHAPTER 8 TIMER/COUNTER 0 Figure 8-38 Control Register Settings for Pulse Width Measurement (a) Capture/compare control register 0 (CRC0) CRC0 TM0 clearing disabled TO0 & TO1 both toggle outputs (b) External interrupt mode register 1 (INTM1) × × × × INTM1 Both rising &...
Page 230: Operation As Pwm Output
CHAPTER 8 TIMER/COUNTER 0 Figure 8-40 Interrupt Request Servicing that Calculates Pulse Width INTP3 interrupt Calculate pulse width = CR02 – X Store capture value in memory ← CR02 n + 1 RETI 8.8.4 Operation as PWM Output In PWM output, pulses with the duty ratio determined by the value set in the compare register (CR0n: n = 0, 1) are output (see Figure 8-41).
Page 231 CHAPTER 8 TIMER/COUNTER 0 Figure 8-42 Control Register Settings for PWM Output Operation (a) Capture/compare control register 0 (CRC0) CRC0 TM0 clearing disabled TO0 & TO1 both PWM outputs (b) Timer output control register (TOC) × × × × × ×...
Page 232 CHAPTER 8 TIMER/COUNTER 0 Figure 8-43 PWM Output Setting Procedure PWM output Set CRC0 CRC0 ← 90H Set TOC Set P34 pin to control mode PMC3.4 ← 1 Set initial value in CR00, CR01 Start count ; Set bit 3 of TMC0 CE0 ←...
Page 233 CHAPTER 8 TIMER/COUNTER 0 Figure 8-44 Changing PWM Output Duty Duty change preprocessing Clear INTC00 interrupt request flag ; Clear bit 7 of CIC00 CIF00 ← 0 Enable INTC00 interrupts ; Clear bit 4 of MK0L CMK00 ← 0 INTC00 Interrupt Duty change processing Set duty value in CR00 Disable INTC00 interrupts...
Page 234: Operation As Ppg Output
CHAPTER 8 TIMER/COUNTER 0 8.8.5 Operation as PPG Output In PPG output, pulses with the cycle and duty ratio determined by the values set in the compare registers (CR0n: n = 0, 1) are output (see Figure 8-45). The control register settings are shown in Figure 8-46, the setting procedure in Figure 8-47, and the procedure for varying the duty in Figure 8-48.
Page 235 CHAPTER 8 TIMER/COUNTER 0 Figure 8-46 Control Register Settings for PPG Output Operation (a) Capture/compare control register 0 (CRC0) CRC0 TM0 cleared by match of TM0 & CR01 TO0 = PPG output (b) Timer output control register (TOC) × × ×...
Page 236 CHAPTER 8 TIMER/COUNTER 0 Figure 8-47 PPG Output Setting Procedure PPG output Set CRC0 CRC0 ← D8H Set TOC Set P34 pin to control mode PMC3.4 ← 1 Set cycle in CR01 Set duty in CR00 Start count ; Set bit 3 of TMC0 CE0 ←...
Page 237 CHAPTER 8 TIMER/COUNTER 0 Figure 8-48 Changing PPG Output Duty Duty change preprocessing Clear INTC00 interrupt request flag ; Clear bit 7 of CIC00 CIF00 ← 0 Enable INTC00 interrupts ; Clear bit 4 of MK0L CMK00 ← 0 INTC00 Interrupt Duty change processing Set duty value in CR00 Disable INTC00 interrupts...
Page 238: Example Of Software Triggered One-Shot Pulse Output
CHAPTER 8 TIMER/COUNTER 0 8.8.6 Example of Software Triggered One-Shot Pulse Output In the software triggered one-shot pulse output mode, a one-shot pulse is output in response to a trigger activated by software (see Figure 8-49). The control register settings are shown in Figure 8-50, and the setting procedure in Figure 8-51. Figure 8-49 Example of Timer/Counter 0 One-Shot Pulse Output FFFFH FFFFH...
Page 239 CHAPTER 8 TIMER/COUNTER 0 Figure 8-50 Control Register Settings for One-Shot Pulse Output (a) One-shot pulse output control register (OSPC) × OSPC TO0 = one-shot pulse output (b) Capture/compare control register 0 (CRC0) CRC0 TM0 clearing disabled TO0 & TO1 both toggle outputs (c) Timer output control register (TOC) ×...
Page 240 CHAPTER 8 TIMER/COUNTER 0 Figure 8-51 One-Shot Pulse Output Setting Procedure One-shot pulse output Set OSPC ; Set to one-shot pulse output mode OS0 ← 1 Set CRC0 CRC0 ← 10H Set P34 pin to control mode PMC 3.4 ← 1 Set pulse width in CR00 Start count ;...
Page 241: Cautions
CHAPTER 8 TIMER/COUNTER 0 8.9 CAUTIONS (1) While timer/counter 0 is operating (while the CE0 bit of the timer control register 0 (TMC0) is set), malfunctioning may occur if the contents of the following registers are rewritten. This is because it is undefined which takes precedence in a contention the change in the hardware functions due to rewriting the register, or the change in the status because of the function before rewriting.
Page 242 CHAPTER 8 TIMER/COUNTER 0 (3) Up to 1 count clock is required after an operation to start timer/counter 0 (CE0 ← 1) has been performed before timer/counter 0 actually starts (refer to Figure 8-52). For example, when using timer/counter 0 as an interval timer, the first interval time is delayed by up to 1 clock. The second and those that follow are at the specified interval.
Page 243 CHAPTER 8 TIMER/COUNTER 0 (7) The output level of the TOn (n = 0, 1) when the timer output is disabled (ENTOn = 0: n = 0, 1) is the reverse value of the value set to the ALVn (n = 0, 1) bit. Note, therefore, that an active level is output when the timer output is disabled with the PWM output function or PPG output function selected.
Page 244 CHAPTER 8 TIMER/COUNTER 0 Figure 8-54 To Distinguish Whether One or No Valid Edge Has Been Input with External Event Counter (a) Processing on starting counting Start count Clear INTP3 ; Clear PIF3 to 0 interrupt request flag PIF3 ← 0 Start count ;...
Page 245 CHAPTER 8 TIMER/COUNTER 0 (10) If the count operation of TM0 stops at the timing at which compare register (CR00) and timer register 0 (TM0) match, the CR00/TM0 match interrupt may not be generated after timer/counter 0 is next started. If the TM0 count operation is stopped within 1.5 count clocks after a match between CR00 and TM0, the first match interrupt after timer/counter 0 is next started will not be generated.
Page 246: Chapter 9 Timer/Counter 1
CHAPTER 9 TIMER/COUNTER 1 9.1 FUNCTIONS Timer/counter 1 is 16-bit or 8-bit timer/counter. In addition to its basic functions of interval timer, pulse width measurement and event counter, timer/counter 1 can be used as a real-time output port output trigger generation timer. (1) Interval timer Generates internal interrupts at preset intervals.
Page 247 CHAPTER 9 TIMER/COUNTER 1 (2) Pulse width measurement Detects the pulse width of the signal input to the external interrupt request input pin INTP0. Table 9-2 Timer/Counter 1 Pulse Width Measurement Range Note Measurable Pulse Width Resolution × 8/f (0.25 µ s) (0.25 µ...
Page 248: Configuration
CHAPTER 9 TIMER/COUNTER 1 (3) External event counter Counts the clock pulses input from the external interrupt request input pin (INTP0). The clocks that can be input to timer/counter 1 are shown in Table 9-3. Table 9-3 Timer/Counter 1 Pulse Width Measurement Time ( ): When f = 16 MHz and f = 32 MHz...
Page 249 Internal Bus 8/16 External Interrupt Capture/Compare Compare Register ES01 ES00 CLR11 CM CLR10 Mode Register 0 Control Register 1 (CRC1) (CR10/CR10W) (INTM0) 8/16 Match Edge P21/INTP0 Detection INTC10 Selector Match Circuit INTP0 Capture/Compare Clear Register Real-Time Output Port (CR11/CR11W) RESET Match f××/1,024 Selector...
Page 250 CHAPTER 9 TIMER/COUNTER 1 (1) Timer register 1 (TM1/TM1W) TM1//TM1W is a timer register that counts up using the count clock specified by the low-order 4 bits of prescaler mode register 1 (PRM1). The count operation can be specified to stop or enable, and an 8-bit operation mode (TM1)/16-bit operation mode (TM1W) can be selected, by means of timer control register 1 (TMC1).
Page 251 CHAPTER 9 TIMER/COUNTER 1 (b) When specified as capture register CR11/CR11W functions as an 8/16-bit register that captures the contents of TM1/TM1W in synchronization with the input of a valid edge (capture trigger) on the external interrupt request input pin (INTP0). The contents of the CR11/CR11W are retained until the next capture trigger is generated.
Page 252: Timer/Counter 1 Control Registers
CHAPTER 9 TIMER/COUNTER 1 9.3 TIMER/COUNTER 1 CONTROL REGISTERS (1) Timer control register 1 (TMC1) TMC1 controls the timer/counter 1, TM1/TM1W, count operation by the low-order 4 bits (the high-order 4 bits control the count operation of timer/counter 2, TM2/TM2W). TMC1 can be read or written to with an 8-bit manipulation instruction or bit manipulation instruction.
Page 253 CHAPTER 9 TIMER/COUNTER 1 (2) Prescaler mode register 1 (PRM1) The count clock of PRM1 to timer/counter 1, TM1/TM1W, is specified by the low-order 4 bits (the high-order 4 bits specify the count clock to timer/counter 2, TM2/TM2W). PRM1 can be read or written to with an 8-bit manipulation instruction. The format of the PRM1 is shown in Figure 9-3. RESET input sets PRM1 to 11H.
Page 254 CHAPTER 9 TIMER/COUNTER 1 (3) Capture/compare control register 1 (CRC1) The CRC1 specifies the operation of the capture/compare register (CR11/CR11W) and the enabling condition for a timer register 1 (TM1/TM1W) clear operation. CRC1 can be read or written to with an 8-bit manipulation instruction. The format of the CRC1 is shown in Figure 9-4. RESET input clears CRC1 to 00H.
Page 255 CHAPTER 9 TIMER/COUNTER 1 <Operation> Because the timer register is cleared at the next count if the capture request signal is generated when the value of timer register is “N” when the value “N + 1” is set to the compare register, no interrupt request is generated by the compare register. Actually, however, the timer register momentarily counts “N + 1”...
Page 256: Timer Register 1 (Tm1) Operation
CHAPTER 9 TIMER/COUNTER 1 9.4 TIMER REGISTER 1 (TM1) OPERATION 9.4.1 Basic Operation 8-bit operating mode/16-bit operating mode control can be performed for timer/counter 1 by means of bit 0 (BW1) of timer Note control register 1 (TMC1). In the timer/counter 1 count operation, an up-count is performed using the count clock specified by the low-order 4 bits of prescaler mode register 1 (PRM1).
Page 257 CHAPTER 9 TIMER/COUNTER 1 Figure 9-6 Basic Operation in 8-Bit Operating Mode (BW1 = 0) (a) Count started → count disabled → count started Count Clock Count Started Count Stopped Count Started CE1 ← 1 CE1 ← 0 CE1 ← 1 (b) When “1”...
Page 258 CHAPTER 9 TIMER/COUNTER 1 Figure 9-7 Basic Operation in 16-Bit Operating Mode (BW1 = 1) (a) Count started → count disabled → count started Count Clock TM1W FFH 100H 101H Count Started Count Stopped Count Started CE1 ← 1 CE1 ← 0 CE1 ←...
Page 259: Clear Operation
CHAPTER 9 TIMER/COUNTER 1 9.4.2 Clear Operation (1) Clear operation after match with compare register and after capture operation Timer register 1 (TM1) can be cleared automatically after a match with the compare register (CR1n: n = 0, 1) and a capture operation.
Page 260 CHAPTER 9 TIMER/COUNTER 1 Figure 9-10 Clear Operation When CE1 Bit is Cleared (0) (a) Basic operation Count Clock n - 1 (b) Restart before count clock is input after clearance Count Clock n - 1 If the CE1 bit is set (to 1) before this count clock, this count clock starts counting from 0. (c) Restart after count clock is input after clearance Count Clock n - 1...
Page 261: External Event Counter Function
CHAPTER 9 TIMER/COUNTER 1 9.5 EXTERNAL EVENT COUNTER FUNCTION Timer/counter 1 can count clock pulses input from the external interrupt request input pin (INTP0) pin. No special selection method is needed for the external event counter operating mode. When the timer register 1 (TM1) count clock is specified as external clock input by the setting of the low-order 4 bits of prescaler mode register 1 (PRM1), TM1 operates as an external event counter.
Page 262 CHAPTER 9 TIMER/COUNTER 1 (2) Counting both edges (maximum frequency = f (MIN.) (MIN.) (MIN.) INTP0 3 to 4/f Dn + 1 Dn + 2 Dn + 3 Dn + 4 Dn + 5 Remarks 1. ICI: INTP0 input signal after passing through edge detection circuit 2.
Page 263 CHAPTER 9 TIMER/COUNTER 1 Figure 9-13 Methods of Enabling the External Event Counter to Distinguish No Valid Edge Input (a) Processing when count is started Start count Clear INTP0 interrupt ; Clear PIF0 to 0 request flag PIF0 ← 0 Start count ;...
Page 264: Compare Register, Capture/Compare Register, And Capture Register Operation
CHAPTER 9 TIMER/COUNTER 1 9.6 COMPARE REGISTER, CAPTURE/COMPARE REGISTER, AND CAPTURE REGISTER OPERATION 9.6.1 Compare Operations Timer/counter 1 performs compare operations in which the value set in a compare register (CR10), capture/compare register (CR11), specified for compare operation is compared with the timer register 1 (TM1) count value. If the count value of TM1 matches the preset value of the CR10, or the CR11 as the result of the count operation, an interrupt request signal (INTC10 or INTC11) is generated.
Page 265 CHAPTER 9 TIMER/COUNTER 1 Figure 9-15 Compare Operation in 16-Bit Operating Mode FFFFH FFFFH TM1W Count Value CR11W Value CR11W Value CR10W Value CR10W Value Match Match Match Match Count Start CE1 ← 1 INTC10 Interrupt Request INTC11 Interrupt Request OVF1 Cleared by Software Remark CLR10 = 0, CLR11 = 0, BW1 = 1...
Page 266: Capture Operations
CHAPTER 9 TIMER/COUNTER 1 9.6.2 Capture Operations Timer/counter 1 performs capture operations in which the timer register 1 (TM1) count value is fetched into the capture register in synchronization with an external trigger, and retained there. A valid edge detected from the input of the external interrupt request input pin (INTP0) is used as the external trigger (capture trigger).
Page 267 CHAPTER 9 TIMER/COUNTER 1 Figure 9-18 Capture Operation in 16-Bit Operating Mode FFFFH TM1W Count Value Count Start CE1 ← 1 INTP0 Pin Input INTP0 Interrupt Request Capture Register (CR12W) OVF1 Remark Dn: TM1W count value (n = 0, 1, 2, ...) CLR10 = 0, CLR11 = 0, CM = 1, BW1 = 1 User’s Manual U11316EJ4V1UD...
Page 268 CHAPTER 9 TIMER/COUNTER 1 Figure 9-19 TM1 Clearance after Capture Operation Count Value Capture Capture Capture Capture Capture INTP0 Pin Input INTP0 Interrupt Request Capture/Compare Register (CR11) Remark NI: TM1 count value (n = 0, 1, 2, ...) CLR10 = 0, CLR11 = 1, CM = 1 Caution Even if an attempt is made to clear the timer register by inputting the capture request signal when the capture function of the timer is used, the timer register momentarily counts up immediately before it is cleared.
Page 269 CHAPTER 9 TIMER/COUNTER 1 <Operation> Because the timer register is cleared at the next count if the capture request signal is generated when the value of timer register is “N” when the value “N + 1” is set to the compare register, no interrupt request is generated by the compare register. Actually, however, the timer register momentarily counts “N + 1”...
Page 270: Examples Of Use
CHAPTER 9 TIMER/COUNTER 1 9.7 EXAMPLES OF USE 9.7.1 Operation as Interval Timer (1) When timer register 1 (TM1) is made free-running and a fixed value is added to the compare register (CR1n: n = 0, 1) in the interrupt service routine, TM1 operates as an interval timer with the added fixed value as the cycle (see Figure 9-21). Since TM1 has two compare registers, two interval timers with different intervals can be constructed.
Page 271 CHAPTER 9 TIMER/COUNTER 1 Figure 9-22 Control Register Settings for Interval Timer Operation (1) (a) Prescaler mode register 1 (PRM1) × × × × PRM1 PRS13 PRS12 PRS11 PRS10 Count clock specification (x/f ; x = 8, 16, 32, 64, 128, 256, 512, 1,024, 2,048) (b) Capture/compare control register 1 (CRC1) CRC1...
Page 272 CHAPTER 9 TIMER/COUNTER 1 Figure 9-23 Interval Timer Operation (1) Setting Procedure Interval timer (1) Set PRM1 Set count value in CR10 CR10 ← n Set CRC1 CRC1 ← 00H Start count ; Set 1 in bit 3 of TMC1 CE1 ←...
Page 273: Operation As Interval Timer (2)
CHAPTER 9 TIMER/COUNTER 1 9.7.2 Operation as Interval Timer (2) TM1 operates as an interval timer that generates interrupts repeatedly with the preset count time as the interval (see Figure 9-25). The control register settings are shown in Figure 9-26, and the setting procedure in Figure 9-27. Figure 9-25 Interval Timer Operation (2) Timing (When CR11 is Used as Compare Register) Count Value Count Start...
Page 274 CHAPTER 9 TIMER/COUNTER 1 Figure 9-26 Control Register Settings for Interval Timer Operation (2) (a) Prescaler mode register 1 (PRM1) × × × × PRM1 PRS13 PRS12 PRS11 PRS10 Count clock specification (x/f ; x = 8, 16, 32, 64, 128, 256, 512, 1,024, 2,048) (b) Capture/compare control register 1 (CRC1) CRC1...
Page 275: Pulse Width Measurement Operation
CHAPTER 9 TIMER/COUNTER 1 9.7.3 Pulse Width Measurement Operation In pulse width measurement, the high-level or low-level width of external pulses input to the external interrupt request input pin (INTP0) is measured. Both the high-level and low-level widths of pulses input to the INTP0 pin must be at least 3 sampling clocks selected by SCS0;...
Page 276 CHAPTER 9 TIMER/COUNTER 1 Figure 9-29 Control Register Settings for Pulse Width Measurement (a) Prescaler mode register 1 (PRM1) × × × × PRM1 PRS13 PRS12 PRS11 PRS10 Count clock specification (x/f ; x = 8, 16, 32, 64, 128, 256, 512, 1,024, 2,048) (b) Capture/compare control register 1 (CRC1) CRC1...
Page 277 CHAPTER 9 TIMER/COUNTER 1 Figure 9-30 Pulse Width Measurement Setting Procedure Pulse width measurement Set PRM1 Set CRC1 CRC1 ← 04H ; Specify both edges as INTP0 Set INTM0 input valid edges, release Set MK0L interrupt masking Initialize capture value buffer memory ←...
Page 278: Cautions
CHAPTER 9 TIMER/COUNTER 1 9.8 CAUTIONS (1) While timer/counter 1 is operating (while the CE1 bit of the timer control register 1 (TMC1) is set), malfunctioning may occur if the contents of the following registers are rewritten. This is because it is undefined which takes precedence in a contention, the change in the hardware functions due to rewriting the register, or the change in the status because of the function before rewriting.
Page 279 CHAPTER 9 TIMER/COUNTER 1 (3) Up to 1 count clock is required after an operation to start timer/counter 1 (CE1 ← 1) has been performed before timer/counter 1 actually starts (refer to Figure 9-32). For example, when using timer/counter 1 as an interval timer, the first interval time is delayed by up to 1 clock. The second and those that follow are at the specified interval.
Page 280 CHAPTER 9 TIMER/COUNTER 1 (7) When timer/counter 0 is used as an external event counter, it is not possible to distinguish between the case where there is no valid edge input at all and the case where there is a single valid edge input, using the timer register 0 (TM0) alone (refer to Figure 9-33), since the contents of TM0 are 0 in both cases.
Page 281 CHAPTER 9 TIMER/COUNTER 1 Figure 9-34 To Distinguish Whether One or No Valid Edge Has Been Input with External Event Counter (a) Processing on starting counting Start count Clear INTP0 ; Clear PIF0 to 0 interrupt request flag PIF0 ← 0 Start count ;...
Page 282 CHAPTER 9 TIMER/COUNTER 1 (8) Even if an attempt is made to clear the timer register by inputting the capture request signal when the capture function of the timer is used, the timer register momentarily counts up immediately before it is cleared. Consequently, if a value greater than the value of the timer register by 1 is set to the compare register when the capture request signal is input, the values of the compare register and timer register coincide, and an unnecessary interrupt will be generated (refer to Figure 9-35).
Page 283 CHAPTER 9 TIMER/COUNTER 1 (9) If the count operation of TM1 stops at the timing at which compare register (CR10) and timer register 1 (TM1) match, the CR10/TM1 match interrupt may not be generated after timer/counter 1 is next started. If the TM1 count operation is stopped within 1.5 count clocks after a match between CR10 and TM1, the first match interrupt after timer/counter 1 is next started will not be generated.
Page 284: Chapter 10 Timer/Counter 2
CHAPTER 10 TIMER/COUNTER 2 10.1 FUNCTIONS Timer/counter 2 is 16-bit or 8-bit timer/counter, and has the following function which the other three timer/counters do not have: Note • One-shot timer Note The one-shot timer function is a count operation of timer/counter 2 (TM2/TM2W), and is thus different in nature from the one-shot pulse output function of timer/counter 0.
Page 285 CHAPTER 10 TIMER/COUNTER 2 (2) Programmable square-wave output Outputs square waves independently to the timer output pins (TO2 and TO3). Table 10-2 Timer/Counter 2 Programmable Square-Wave Output Setting Range Minimum Pulse Width Maximum Pulse Width × 8/f (0.25 µ s) (16.40 ms) ×...
Page 286 CHAPTER 10 TIMER/COUNTER 2 (3) Pulse width measurement Detects the pulse width of the signal input to an external interrupt request input pins (INTP1/INTP2). Table 10-3 Timer/Counter 2 Pulse Width Measurement Range Note Measurable Pulse Width Resolution × 8/f (0.25 µ s) (0.25 µ...
Page 287: Configuration
CHAPTER 10 TIMER/COUNTER 2 10.2 CONFIGURATION Timer/counter 2 consists of the following registers. • Timer register (TM2/TM2W) × 1 • Compare register (CR20/CR20W) × 1 • Capture/compare register (CR21/CR21W) × 1 • Capture register (CR22/CR22W) × 1 The block diagram of timer/counter 2 is shown in Figure 10-1. User’s Manual U11316EJ4V1UD...
Page 288 Internal Bus 8/16 Capture/Compare Control Register 2 (CRC2) Timer Output External Interrupt Compare Register ES21 ES20 ES11 ES10 MOD1 MOD0 CLR22 CLR21 CM21 ENT03 ALV3 ENT02 ALV2 Control Register Mode Register 0 (CR20/CR20W) (TOC) (INTM0) 8/16 PWM/PPG Match Edge Output Control P22/INTP1 Detection Selector...
Page 289 CHAPTER 10 TIMER/COUNTER 2 (1) Timer register 2 (TM2/TM2W) TM2/TM2W is a timer register that counts up the count clock specified by the high-order 4 bits of prescaler mode register 1 (PRM1). An internal clock or external clock can be selected as the count clock. The count operation can be stopped or enabled by means of timer control register 1 (TMC1).
Page 290 CHAPTER 10 TIMER/COUNTER 2 (b) When specified as capture register CR21/CR21W functions as an 8/16-bit register that captures the contents of TM2/TM2W in synchronization with the input of a valid edge on the external interrupt input pin (INTP2) (capture trigger). The contents of the CR21/CR21W register are retained until the next capture trigger is generated.
Page 291: Timer/Counter 2 Control Registers
CHAPTER 10 TIMER/COUNTER 2 10.3 TIMER/COUNTER 2 CONTROL REGISTERS (1) Timer control register 1 (TMC1) In TMC1 the timer/counter 2, TM2/TM2W, count operation is controlled by the high-order 4 bits (the low-order 4 bits control the count operation of timer/counter 1, TM1/TM1W). TMC1 can be read or written to with an 8-bit manipulation instruction or bit manipulation instruction.
Page 292 CHAPTER 10 TIMER/COUNTER 2 (2) Prescaler mode register 1 (PRM1) In PRM1 the count clock to timer/counter 2, TM2/TM2W, is specified by the high-order 4 bits (the low-order 4 bits specify the count clock to timer/counter 1, TM1/TM1W). PRM1 can be read or written with an 8-bit manipulation instruction. The format of the PRM1 is shown in Figure 10-3.
Page 293 CHAPTER 10 TIMER/COUNTER 2 (3) Capture/compare control register 2 (CRC2) The CRC2 specifies the enabling condition for a timer register 2 (TM2/TM2W) clear operation by the capture/compare register (CR21/CR21W) or the capture register (CR22/CR22W) and the timer output (TO2/TO3) mode. CRC2 can be read or written with an 8-bit manipulation instruction.
Page 294 CHAPTER 10 TIMER/COUNTER 2 <Operation> Because the timer register is cleared at the next count if the capture request signal is generated when the value of timer register is “N” when the value “N + 1” is set to the compare register, no interrupt request is generated by the compare register. Actually, however, the timer register momentarily counts “N + 1”...
Page 295 CHAPTER 10 TIMER/COUNTER 2 (4) Timer output control register (TOC) TOC is an 8-bit register that controls output enabling/disabling of the active level of timer output. The operation of the timer output pins (TO2 and TO3) by timer/counter 2 is controlled by the high-order 4 bits (the low- order 4 bits control the operation of the timer output pins (TO0 and TO1) by timer/counter 0).
Page 296: Timer Register 2 (Tm2) Operation
CHAPTER 10 TIMER/COUNTER 2 10.4 TIMER REGISTER 2 (TM2) OPERATION 10.4.1 Basic Operation 8-bit operating mode/16-bit operating mode control can be performed for timer/counter 2 by means of bit 0 (BW2) of Note timer control register 2 (TMC2). In the timer/counter 2 count operation, an up-count is performed using the count clock specified by the high-order 4 bits of prescaler mode register 1 (PRM1).
Page 297 CHAPTER 10 TIMER/COUNTER 2 Figure 10-7 Basic Operation in 8-Bit Operating Mode (BW2 = 0) (a) Count started → → → → → count disabled → → → → → count started Count Clock 10H 11H Count Started Count Stopped Count Started CE2 ←...
Page 298 CHAPTER 10 TIMER/COUNTER 2 Figure 10-8 Basic Operation in 16-Bit Operating Mode (BW2 = 1) (a) Count started → → → → → count disabled → → → → → count started Count Clock TM2W FFH 100H 101H Count Started Count Stopped Count Started CE2 ←...
Page 299: Clear Operation
CHAPTER 10 TIMER/COUNTER 2 10.4.2 Clear Operation (1) Clear operation after match with compare register and capture operation Timer register 2 (TM2) can be cleared automatically after a match with the compare register (CR2n: n = 0, 1) and a capture operation.
Page 300 CHAPTER 10 TIMER/COUNTER 2 Figure 10-11 Clear Operation When CE2 Bit is Cleared (to 0) (a) Basic operation Count Clock n - 1 (b) Restart before count clock is input after clearance Count Clock n - 1 If the CE2 bit is set (to 1) before this count clock, this count clock starts counting from 0.
Page 301: External Event Counter Function
CHAPTER 10 TIMER/COUNTER 2 10.5 EXTERNAL EVENT COUNTER FUNCTION Timer/counter 2 can count clock pulses input from external interrupt request input pin (INTP2/CI). No special selection method is needed for the external event counter operating mode. When the timer register 2 (TM2) count clock is specified as external clock input by the setting of the high-order 4 bits of prescaler mode register 1 (PRM1), TM2 operates as an external event counter.
Page 302 CHAPTER 10 TIMER/COUNTER 2 Figure 10-12 Timer/Counter 2 External Event Count Timing (2/2) (2) Counting both edges (maximum frequency = f (MIN.) 4/f (MIN.) (MIN.) 3 to 4/f Dn + 1 Dn + 2 Dn + 3 Dn + 4 Dn + 5 Remark ICI: CI input signal after passing through edge detection circuit The TM2 count operation is controlled by the CE2 bit of the timer control register 1 (TMC1) in the same way as with...
Page 303 CHAPTER 10 TIMER/COUNTER 2 Figure 10-14 Methods of Enabling the External Event Counter to Distinguish No Valid Edge Input (a) Processing when count is started Start count Clear INTP2 interrupt ; Clear PIF2 to 0 request flag PIF2 ← 0 Start count ;...
Page 304: One-Shot Timer Function
CHAPTER 10 TIMER/COUNTER 2 10.6 ONE-SHOT TIMER FUNCTION Timer/counter 2 has an operating mode in which it stops automatically when a full count value is reached (FFH/FFFFH) as a result of counting by timer register 2 (TM2/TM2W). Figure 10-15 One-Shot Timer Operation FFH or FFFFH TM2/TM2W Count Value...
Page 305: Compare Register, Capture/Compare Register, And Capture Register Operation
CHAPTER 10 TIMER/COUNTER 2 10.7 COMPARE REGISTER, CAPTURE/COMPARE REGISTER, AND CAPTURE REGISTER OPERATION 10.7.1 Compare Operations Timer/counter 2 performs compare operations in which the value set in the compare register (CR20) and the capture/ compare register (CR21) specified for compare operation is compared with the timer register 2 (TM2) count value. If the count value of TM2 matches the preset value of the CR20, and CR21 when a compare operation is performed, as the result of the count operation, a match signal is sent to the output control circuit, and an interrupt request signal (INTC20 or INTC21) is generated at the same time.
Page 306 CHAPTER 10 TIMER/COUNTER 2 Figure 10-17 Compare Operation in 16-Bit Operating Mode FFFFH FFFFH TM2W Count Value CR21W Value CR21W Value CR20W Value CR20W Value Match Match Match Match Count Start CE2 ← 1 INTC20 Interrupt Request INTC21 Interrupt Request TO2 Pin Output ENTO2 = 1 Inactive Level...
Page 307: Capture Operations
CHAPTER 10 TIMER/COUNTER 2 Figure 10-18 TM2 Clearance after Match Detection CR20 CR21 CR21 CR21 Count Value Count Start Count Disabled Count Start Clear Clear CE2 ← 1 CE2 ← 0 CE2 ← 1 CLR21 ← 0 CLR21 ← 1 INTC20 Interrupt Request INTC21...
Page 308 CHAPTER 10 TIMER/COUNTER 2 Figure 10-19 Capture Operation in 8-Bit Operating Mode Count Value Count Starts CE ← 1 INTP2 Pin Input INTP2 Interrupt Request Capture Register (CR21) INTP1 Pin Input INTP1 Interrupt Request Capture Register (CR22) OVF2 Remark Dn: TM2 count value (n = 0, 1, 2, ...) CM21 = 1, CLR21 = 0, CLR22 = 0, BW2 = 0 User’s Manual U11316EJ4V1UD...
Page 309 CHAPTER 10 TIMER/COUNTER 2 Figure 10-20 Capture Operation in 16-Bit Operating Mode FFFFH TM2W Count Value Count Starts CE ← 1 INTP2 Pin Input INTP2 Interrupt Request Capture Register (CR21W) INTP1 Pin Input INTP1 Interrupt Request Capture Register (CR22W) OVF2 Remark Dn: TM2W count value (n = 0, 1, 2, ...) CM21 = 1, CLR21 = 0, CLR22 = 0, BW2 = 0 User’s Manual U11316EJ4V1UD...
Page 310 CHAPTER 10 TIMER/COUNTER 2 Figure 10-21 TM2 Clearance after Capture Operation Count Value Capture Capture Capture Capture Capture INTP1 Pin Input INTP1 Interrupt Request Capture/Compare Register (CR22) Remark CLR21 = 0, CLR22 = 1 Caution Even if an attempt is made to clear the timer register by inputting the capture request signal when the capture function of the timer is used, the timer register momentarily counts up immediately before it is cleared.
Page 311 CHAPTER 10 TIMER/COUNTER 2 <Operation> Because the timer register is cleared at the next count if the capture request signal is generated when the value of timer register is “N” when the value “N + 1” is set to the compare register, no interrupt request is generated by the compare register. Actually, however, the timer register momentarily counts “N + 1”...
Page 312: Basic Operation Of Output Control Circuit
CHAPTER 10 TIMER/COUNTER 2 10.8 BASIC OPERATION OF OUTPUT CONTROL CIRCUIT The output control circuit controls the timer output pins (TO2/TO3) level by means of match signals from the compare register (CR22). The operation of the output control circuit is determined by the timer output control register (TOC) and capture/compare control register 2 (CRC2) (see Table 10-6).
Page 314: Basic Operation
CHAPTER 10 TIMER/COUNTER 2 10.8.1 Basic Operation Setting (to 1) the ENTOn (n = 2, 3) bit of the timer output control register (TOC) enables timer output (TOn: n = 2, 3) to be varied at a timing in accordance with the settings of MOD0, MOD1, and CLR21 bits of capture/compare control register 2 (CRC2).
Page 315 CHAPTER 10 TIMER/COUNTER 2 Table 10-7 TO2/TO3 Toggle Output (f = 32 MHz) Count Clock Minimum Pulse Width Maximum Pulse Width × 8/f (0.25 µ s) (16.40 ms) × 16/f 16/f (0.50 µ s) (32.80 ms) × 32/f 32/f (1.00 µ s) (65.50 ms) ×...
Page 316: Pwm Output
CHAPTER 10 TIMER/COUNTER 2 10.8.3 PWM Output (1) Basic operation of PWM output In this mode, a PWM signal with the period in which timer register 2 (TM2) reaches a full count used as one cycle is output. The timer output (TO2) pulse width is determined by the value of compare register (CR20), and the timer output (TO3) pulse width is determined by the value of compare register (CR21).
Page 317 CHAPTER 10 TIMER/COUNTER 2 Figure 10-24 PWM Pulse Output (BW2 = 0) CR20 CR20 CR20 Count Value Count Start Interrupt Pulse Width Pulse Width Pulse Cycle Pulse Cycle Remark ALV2 = 0 Table 10-8 TO2/TO3 PWM Cycle (f = 32 MHz, BW2 = 0) Minimum Pulse Width [ µ...
Page 318 CHAPTER 10 TIMER/COUNTER 2 Figure 10-25 PWM Pulse Output (BW2 = 1) FFFFH FFFFH FFFFH CR20 CR20 CR20 Count Value Count Start Interrupt Pulse Width Pulse Width Pulse Cycle Pulse Cycle Remark ALV2 = 0 Table 10-9 TO2/TO3 PWM Cycle (f = 32 MHz, BW2 = 1) Minimum Pulse Width [ µ...
Page 319 CHAPTER 10 TIMER/COUNTER 2 Figure 10-26 shows an example of 2-channel PWM output, and Figure 10-27 shows the case where FFFFH is set in the CR20W. Figure 10-26 Example of PWM Output Using TM2W FFFFH FFFFH FFFFH CR21W CR21W CR20W TM2W CR20W Count Value...
Page 320 CHAPTER 10 TIMER/COUNTER 2 (2) Rewriting compare registers (CR20, CR21) The output level of the timer output (TOn + 2: n + 2 = 2, 3) is not inverted even if the CR2n (n = 0, 1) value matches the timer register 2 (TM2) value more than once during one PWM output cycle. Figure 10-28 Example of Compare Register (CR20W) Rewrite FFFFH FFFFH...
Page 321 CHAPTER 10 TIMER/COUNTER 2 If a value smaller than that of the TM2 is set as the CR2n value, a 100% duty PWM signal will be output. CR2n rewriting should be performed by the interrupt due to a match between TM2 and the CR2n on which the rewrite is performed. Figure 10-29 Example of 100% Duty With PWM Output Count Value CR20...
Page 322 CHAPTER 10 TIMER/COUNTER 2 (3) Stopping PWM output If timer/counter 2 is stopped by clearing (to 0) the CE2 bit of the timer control register 1 (TMC1) during PWM signal output, the active level is output. Figure 10-30 When Timer/Counter 2 is Stopped During PWM Signal Output FFFFH FFFFH CR20W...
Page 323: Ppg Output
CHAPTER 10 TIMER/COUNTER 2 10.8.4 PPG Output (1) Basic operation of PPG output This function outputs a square-wave with the time determined by compare register CR21 value as one cycle, and the time determined by compare register CR20 value as the pulse width. The PWM output PWM cycle is made variable. This signal can only be output from timer output (TO2).
Page 324 CHAPTER 10 TIMER/COUNTER 2 Figure 10-31 Example of PPG Output Using TM2 CR21 CR21 CR21 Count Value CR20 CR20 CR20 Count Start INTC20 INTC21 (PPG Output) Pulse Width (Timer Output) Pulse Cycle Remark ALV2 = 0, ALV3 = 0 Table 10-10 TO2 PPG Output (f = 32 MHz) Count Clock Minimum Pulse Width...
Page 325 CHAPTER 10 TIMER/COUNTER 2 Figure 10-32 Example of PPG Output When CR20 = CR21 n - 1 Count Cycle T Count Value INTC20 INTC21 Pulse Width = nT Pulse Cycle = (n + 1)T Remark ALV2 = 0 T = x/f (x = 8, 16, 32, 64, 128, 256, 512, 1,024, 2,048) User’s Manual U11316EJ4V1UD...
Page 326 CHAPTER 10 TIMER/COUNTER 2 (2) Rewriting compare register (CR20) The output level of the timer output (TO2) is not changed even if the CR20 value matches the timer register 2 (TM2) value more than once during one PPG output cycle. Figure 10-33 Example of Compare Register Rewrite CR21 CR21...
Page 327 CHAPTER 10 TIMER/COUNTER 2 If a value equal to or less than the TM2 value is written to CR20 before the CR20 and TM2 match, the duty of that PPG cycle will be 100%. CR20 rewriting should be performed by the interrupt due to a match between TM2 and CR20. Figure 10-34 Example of 100% Duty With PPG Output CR21 CR21...
Page 328 CHAPTER 10 TIMER/COUNTER 2 (3) Rewriting compare register (CR21) If the current value of the CR21 is changed to a smaller value, and the CR21 value is made smaller than the register 2 (TM2) value, the PPG cycle at that time will be extended to the time equivalent to a full-count by TM2. If CR21 is rewritten after the compare register (CR20) and TM2 match, the output level at this time will be the inactive level until TM2 overflows and becomes 0, and will then return to normal PPG output.
Page 329 CHAPTER 10 TIMER/COUNTER 2 (4) Stopping PPG output If timer/counter 2 is stopped by clearing (to 0) the CE2 bit of the timer control register 1 (TMC1) during PPG signal output, the active level is output irrespective of the output level at the time timer/counter 2 was stopped. Figure 10-36 When Timer/Counter 2 is Stopped During PPG Signal Output CR21 CR21...
Page 330: Examples Of Use
CHAPTER 10 TIMER/COUNTER 2 10.9 EXAMPLES OF USE 10.9.1 Operation as Interval Timer (1) When timer register 2 (TM2) is made free-running and a fixed value is added to the compare register (CR2n: n = 0, 1) in the interrupt service routine, TM2 operates as an interval timer with the added fixed value as the cycle (see Figure 10-37).
Page 331 CHAPTER 10 TIMER/COUNTER 2 Figure 10-38 Control Register Settings for Interval Timer Operation (1) (a) Prescaler mode register 1 (PRM1) × × × PRM1 PRS23 PRS22 PRS21 PRS20 Count clock specification (x/f ; x = 8, 16, 32, 64, 128, 256, 512, 1,024, 2,048 or external clock) (b) Capture/compare control register 2 (CRC2) CRC2...
Page 332 CHAPTER 10 TIMER/COUNTER 2 Figure 10-39 Interval Timer Operation (1) Setting Procedure Interval timer (1) Set PRM1 Set count value in CR20 CR20 ← n Set CRC2 CRC2 ← 10H Set TMC1 ; Set 1 in bit 7 of TMC1 CE2 ←...
Page 333: Operation As Interval Timer (2)
CHAPTER 10 TIMER/COUNTER 2 10.9.2 Operation as Interval Timer (2) TM2 operates as an interval timer that generates interrupts repeatedly with the preset count time as the interval (see Figure 10-41). The control register settings are shown in Figure 10-42, and the setting procedure in Figure 10-43. Figure 10-41 Interval Timer Operation (2) Timing Count Value Count Start...
Page 334 CHAPTER 10 TIMER/COUNTER 2 Figure 10-42 Control Register Settings for Interval Timer Operation (2) (a) Prescaler mode register 1 (PRM1) × × × PRM1 PRS23 PRS22 PRS21 PRS20 Count clock specification (x/f ; x = 8, 16, 32, 64, 128, 256, 512, 1,024, 2,048 or external clock) (b) Capture/compare control register 2 (CRC2) CRC2...
Page 335 CHAPTER 10 TIMER/COUNTER 2 Figure 10-43 Interval Timer Operation (2) Setting Procedure Interval timer Set PRM1 Set count value in CR21 CR21 ← n Set CRC2 CRC2 ← 18H Set TMC1 ; Set 1 in bit 7 of TMC1 CE2 ← 1 Set normal mode (CMD2 = 0) CMD2 ←...
Page 336: Pulse Width Measurement Operation
CHAPTER 10 TIMER/COUNTER 2 10.9.3 Pulse Width Measurement Operation In pulse width measurement, the high-level or low-level width of external pulses input to the external interrupt request input pin (INTP1) pin are measured. Both the high-level and low-level widths of pulses input to the INTP1 pin must be at least 3 system clocks (0.19 µ s: f = 16 MHz);...
Page 337 CHAPTER 10 TIMER/COUNTER 2 Figure 10-45 Control Register Settings for Pulse Width Measurement (a) Prescaler mode register 1 (PRM1) × × × PRM1 PRS23 PRS22 PRS21 PRS20 Count clock specification (x/f ; x = 8, 16, 32, 64, 128, 256, 512, 1,024, 2,048 or external clock) (b) Capture/compare control register 2 (CRC2) CRC2...
Page 338 CHAPTER 10 TIMER/COUNTER 2 Figure 10-46 Pulse Width Measurement Setting Procedure Pulse width measurement Set CRC2 CRC2 ← 10H ; Specify both edges as INTP1 input Set INTM0 valid edges, release interrupt masking Set MK0L Initialize capture value buffer memory X0 ←...
Page 339: Operation As Pwm Output
CHAPTER 10 TIMER/COUNTER 2 10.9.4 Operation as PWM Output In PWM output, pulses with the duty ratio determined by the value set in the compare register (CR2n: n = 0, 1) are output (see Figure 10-48). This PWM output duty ratio can be varied in the range 1/256 to 255/256 in 1/256 units. The control register settings are shown in Figure 10-49, the setting procedure in Figure 10-50, and the procedure for varying the duty in Figure 10-51.
Page 340 CHAPTER 10 TIMER/COUNTER 2 Figure 10-49 Control Register Settings for PWM Output Operation (a) Timer control register 1 (TMC1) × × TMC1 Normal mode Overflow flag TM2 count enabled (b) Prescaler mode register 1 (PRM1) × × × × PRM1 PRS23 PRS22 PRS21...
Page 341 CHAPTER 10 TIMER/COUNTER 2 Figure 10-50 PWM Output Setting Procedure PWM output Set CRC2 CRC2 ← 90H Set TOC Set P37 pin to control mode PMC3.7 ← 1 Set count clock in PRM1 Set initial value in CR21 Start count ;...
Page 342 CHAPTER 10 TIMER/COUNTER 2 Figure 10-51 Changing PWM Output Duty Duty change preprocessing Clear INTC21 interrupt request flag ; Clear bit 7 of CIC21 CIF21 ← 0 Enable INTC21 interrupts ; Clear bit 1 of MK0H CMK21 ← 0 INTC21 Interrupt Duty change processing Set duty value in CR21 Disable INTC21 interrupts...
Page 343: Operation As Ppg Output
CHAPTER 10 TIMER/COUNTER 2 10.9.5 Operation as PPG Output In PPG output, pulses with the cycle and duty ratio determined by the value set in the compare register (CR2n: n = 0, 1) are output (see Figure 10-52). The control register settings are shown in Figure 10-53, the setting procedure in Figure 10-54, and the procedure for varying the duty in Figure 10-55.
Page 344 CHAPTER 10 TIMER/COUNTER 2 Figure 10-53 Control Register Settings for PPG Output Operation (a) Timer control register 1 (TMC1) × × TMC1 Normal mode Overflow flag TM2 count enabled (b) Prescaler mode register 1 (PRM1) × × × × PRM1 PRS23 PRS22 PRS21...
Page 345 CHAPTER 10 TIMER/COUNTER 2 Figure 10-54 PPG Output Setting Procedure PPG output Set CRC2 CRC2 ← D8H Set TOC Set P36 pin to control mode PMC3.6 ← 1 Set count clock in PRM1 Set cycle in CR21 Set duty in CR21 Start count ;...
Page 346 CHAPTER 10 TIMER/COUNTER 2 Figure 10-55 Changing PPG Output Duty Duty change preprocessing Clear INTC20 interrupt request flag ; Clear bit 7 of CIC20 CIF20 ← 0 Enable INTC20 interrupts ; Clear bit 0 of MK0H CMK20 ← 0 INTC20 Interrupt Duty change processing Set duty value in CR20 Disable INTC20 interrupts...
Page 347: Operation As External Event Counter
CHAPTER 10 TIMER/COUNTER 2 10.9.6 Operation as External Event Counter An external event counter counts clock pulses (CI pin input pulses) input from off-chip. As shown in Figure 10-56, the value of timer register 2 (TM2) is incremented in synchronization with a CI pin input valid edge (specified as rising edge only).
Page 348 CHAPTER 10 TIMER/COUNTER 2 Figure 10-57 Control Register Settings for External Event Counter Operation (a) Prescaler mode register 1 (PRM1) × × × PRM1 External clock input (C1) specified (b) External interrupt mode register 0 (INTM0) × × × × ×...
Page 349: Operation As One-Shot Timer
CHAPTER 10 TIMER/COUNTER 2 10.9.7 Operation as One-Shot Timer After timer register 2 (TM2) is started, it operates as a one-shot pulse that generates a single interrupt after the preset count time (see Figure 10-59). The second and subsequent one-shot timer operations can be started by clearing the OVF2 bit of timer control register 1 (TMC1).
Page 350 CHAPTER 10 TIMER/COUNTER 2 Figure 10-60 Control Register Settings for One-Shot Timer Operation (a) Timer control register 1 (TMC1) × × × × TMC1 OVF2 One-shot timer mode (b) Prescaler mode register 1 (PRM1) × × × PRM1 PRS23 PRS22 PRS21 PRS20 Count clock specification...
Page 351 CHAPTER 10 TIMER/COUNTER 2 Figure 10-61 One-Shot Timer Operation Setting Procedure One-shot timer Set one-shot timer mode ; Set 1 in bit 5 of TMC1 CMD2 ← 1 Set PRM1 Set count value in CR21 CR21 ← n Set CRC2 CRC2 ←...
Page 352: Cautions
CHAPTER 10 TIMER/COUNTER 2 10.10 CAUTIONS (1) While timer/counter 2 is operating (while the CE2 bit of the timer control register 1 (TMC1) is set), malfunctioning may occur if the contents of the following registers are rewritten. This is because it is undefined which takes precedence, the change in the hardware functions due to rewriting the register, or the change in the status because of the function before rewriting.
Page 353 CHAPTER 10 TIMER/COUNTER 2 (3) Up to 1 count clock is required after an operation to start timer/counter 2 (CE2 ← 1) has been performed before timer/ counter 2 actually starts (refer to Figure 10-63). For example, when using timer/counter 2 as an interval timer, the first interval time is delayed by up to 1 clock. The second and those that follow are at the specified interval.
Page 354 CHAPTER 10 TIMER/COUNTER 2 (6) During PPG output, if the PPG cycle is extremely short as compared with the time required to acknowledge an interrupt, the value of the compare register (CR2n: n = 0, 1) cannot be rewritten by interrupt processing that is performed on match between timer register (TM2) and compare register (CR2n).
Page 355 CHAPTER 10 TIMER/COUNTER 2 Figure 10-65 To Distinguish Whether One or No Valid Edge Has Been Input with External Event Counter (a) Processing on starting counting Start count Clear INTP2 interrupt request flag ; Clear PIF2 to 0 PIF2 ← 0 Start count ;...
Page 356 CHAPTER 10 TIMER/COUNTER 2 (10) Even if an attempt is mode to clear the timer register by inputting the capture request signal when the capture function of the timer is used, the timer register momentarily counts up immediately before it is cleared. Consequently, if a value greater than the value of the timer register by 1 is set to the compare register when the capture request signal is input, the values of the compare register and timer register coincide, and an unnecessary interrupt will be generated (refer to Figure 10-66).
Page 357 CHAPTER 10 TIMER/COUNTER 2 (11) If the count operation of TM2 stops at the timing at which compare register (CR20) and timer register 2 (TM2) match, the CR20/TM2 match interrupt may not be generated after timer/counter 2 is next started. If the TM2 count operation is stopped within 1.5 count clocks after a match between CR20 and TM2, the first match interrupt after timer/counter 2 is next started will not be generated.
Page 358: Chapter 11 Timer 3
CHAPTER 11 TIMER 3 11.1 FUNCTION Timer 3 is a 16- or 8-bit timer. In addition to its function as an interval timer, it can be used as a counter for clocked serial interface (CSI) clock generation. The interval timer generates internal interrupts at pre-set intervals. The interval setting range is shown in Table 11.1. Table 11-1 Timer 3 Intervals Minimum Interval Maximum Interval...
Page 359: Configuration
CHAPTER 11 TIMER 3 11.2 CONFIGURATION Timer 3 consists of the following registers: • Timer register (TM3/TM3W) × 1 • Compare register (CR30/CR30W) × 1 The block diagram of timer 3 is shown in Figure 11-1. Figure 11-1 Timer 3 Block Diagram Internal Bus 8/16 8/16...
Page 360 CHAPTER 11 TIMER 3 (1) Timer register 3 (TM3/TM3W) TM3/TM3W are timer registers that count up using the count clock specified by the high-order 4 bits of prescaler mode register 0 (PRM0). The count operation is stopped or enabled by the timer control register 0 (TMC0). In addition, an 8-bit mode (TM3) or 16-bit mode (TM3W) can be selected.
Page 361: Timer 3 Control Registers
CHAPTER 11 TIMER 3 11.3 TIMER 3 CONTROL REGISTERS (1) Timer control register 0 (TMC0) TMC0 controls the timer 3, TM3/TM3W, count operation by the high-order 4 bits (the low-order 4 bits control the count operation of timer/counter 0, TM0). TMC0 can be read or written to with an 8-bit manipulation instruction.
Page 362 CHAPTER 11 TIMER 3 (2) Prescaler mode register 0 (PRM0) PRM0 specifies the count clock to timer/counter 3 TM3/TM3W by the high-order 4 bits (the low-order 4 bits specify the count clock to timer/counter 0, TM0). PRM0 can be read and written with an 8-bit manipulation instruction. The format of the PRM0 is shown in Figure 11-3.
Page 363: Timer Register 3 (Tm3) Operation
CHAPTER 11 TIMER 3 11.4 TIMER REGISTER 3 (TM3) OPERATION 11.4.1 Basic Operation Timer 3 can operate in an 8-bit or 16-bit mode. These operation modes are selected by bit 4 (BW3) of timer control Note register 0 (TMC0) In the timer 3 count operation, an up-count is performed using the count clock specified by the high-order 4 bits of prescaler mode register 0 (PRM0).
Page 364 CHAPTER 11 TIMER 3 Figure 11-4 Basic Operation in 8-Bit Operating Mode (BW3 = 0) (a) Count started → → → → → count stopped → → → → → count started Count Clock 0FH 10H 11H Count Started Count Started Count Stopped CE3 ←...
Page 365 CHAPTER 11 TIMER 3 Figure 11-5 Basic Operation in 16-Bit Operating Mode (BW3 = 1) (a) Count started → → → → → count stopped → → → → → count started Count Clock TM3W FFH 100H 101H Count Started Count Started Count Stopped CE3 ←...
Page 366: Clear Operation
CHAPTER 11 TIMER 3 11.4.2 Clear Operation (1) Clear operation by match with compare register (CR30) 16-bit timer 3 (TM3) is cleared automatically after a match with the compare register (CR30). When a clearance source arises, TM3 is cleared to 0H on the next count clock. Therefore, even if a clearance source arises, the value at the point at which the clearance source arose is retained until the next count clock arrives.
Page 367 CHAPTER 11 TIMER 3 Figure 11-7 Clear Operation When CE3 Bit is Cleared (to 0) (a) Basic operation Count Clock n - 1 (b) Restart before count clock is input after clearance Count Clock n - 1 If the CE3 bit is set (to 1) before this count clock, the count starts from 0 on this count clock (c) Restart when count clock is input after clearance Count Clock...
Page 368: Compare Register Operation
CHAPTER 11 TIMER 3 11.5 COMPARE REGISTER OPERATION Timer 3 performs compare operations in which the value set in the compare register (CR30) is compared with the timer register 3 (TM3) count value. If the count value of TM3 matches the preset CR30 value as the result of the count operation, an interrupt request (INTC30) is generated.
Page 369: Example Of Use
CHAPTER 11 TIMER 3 11.6 EXAMPLE OF USE Operation as interval timer: TM3 operates as an interval timer that generates interrupts repeatedly with the pre-set count time as the interval (see Figure 11-9). TM3 can also be used for baud rate generation. This interval timer can count up to a maximum of 16.40 ms at the minimum resolution of 0.25 µ...
Page 370 CHAPTER 11 TIMER 3 Figure 11-10 Control Register Settings for Interval Timer Operation Prescaler mode register 0 (PRM0) PRM0 PRS3 PRS2 PRS1 PRS0 Count clock specification (x/f ; x = 8, 16, 32, 64, 128, 256, 512, 1,024, 2,048) Figure 11-11 Interval Timer Operation Setting Procedure Interval timer Set PRM0 Set count value in CR30...
Page 371: Cautions
CHAPTER 11 TIMER 3 11.7 CAUTIONS (1) There is a possibility of malfunction if the contents of prescaler mode register 0 (PRM0) are rewritten while the timer 3 is running (when the CE3 bit of the timer control register 0 (TMC0) is set). The malfunction occurs as there is no defined order of priority in the event of contention between the timings at which the hardware function changes due to a register rewrite and the status changes in the function prior to the rewrite.
Page 372 CHAPTER 11 TIMER 3 (3) There is a delay of up to one count clock between the operation that starts a timer 3 (CE3 ← 1) and the actual start of the timer/counter (see Figure 11-23). For example, if a timer/counter is used as an interval timer, the first interval will be extended by up to one clock. The second and subsequent intervals will be as specified.
Page 373: Chapter 12 Watchdog Timer Function
CHAPTER 12 WATCHDOG TIMER FUNCTION The watchdog timer is a timer that detects inadvertent program loops. Watchdog timer interrupts are used to detect system or program errors. For this purpose, instructions that clear the watchdog timer (start the count) within a given period are inserted at various places in a program. If an instruction that clears the watchdog timer is not executed within the set time and the watchdog timer overflows, a watchdog timer interrupt (INTWDT) is generated and a program error is reported.
Page 374: Watchdog Timer Mode Register (Wdm)
If recovery from an operand error is simply performed by means of an RETB instruction, an endless loop will result. As an operand error interrupt is only generated in the event of an inadvertent program loop (with the NEC Electronics assembler, RA78K4, only the correct dedicated instruction is generated when MOV WDM, #byte is written), system initialization should be performed by the program.
Page 375 CHAPTER 12 WATCHDOG TIMER FUNCTION Figure 12-2 Watchdog Timer Mode Register (WDM) Format Address After Reset WDI2 WDI1 FFC2H Overflow Time [ms] WDI2 WDI2 = 16 MHz (8.19) (32.77) (65.54) (131.07) Remark f : Internal System Clock Frequency Watchdog Timer Interrupt Request Priority Specification Watchdog timer interrupt request <...
Page 376: Operation
CHAPTER 12 WATCHDOG TIMER FUNCTION 12.3 OPERATION 12.3.1 Count Operation The watchdog timer is cleared, and the count started, by setting (to 1) the RUN bit of the watchdog timer mode register (WDM). When overflow time specified by the WDM2 and WDM1 bits of WDM has elapsed after the RUN bit has been set (to 1), a non-maskable interrupt (INTWDT) is generated.
Page 377: Cautions
CHAPTER 12 WATCHDOG TIMER FUNCTION 12.4 CAUTIONS 12.4.1 General Cautions on Use of Watchdog Timer (1) The watchdog timer is one means of detecting inadvertent program loops, but it cannot detect all inadvertent program loops. Therefore, in equipment that requires a high level of reliability, you should not rely on the on-chip watchdog timer alone, but should use external circuitry for early detection of inadvertent program loops, to enable processing to be performed that will restore the normal state or establish a stable state and then stop the operation.
Page 378: Chapter 13 Pwm Output Unit
CHAPTER 13 PWM OUTPUT UNIT The µ PD784038 incorporates two 12-bit resolution PWM (pulse width modulation) output circuit channels. The active level of the PWM output pulses can be selected as high or low. The PWM output ports have a dual function as pins P10 and P11.
Page 379: Pwm Output Unit Control Registers
CHAPTER 13 PWM OUTPUT UNIT 13.2 PWM OUTPUT UNIT CONTROL REGISTERS 13.2.1 PWM Control Register (PWMC) The PWMC is an 8-bit register that controls the operating status of the PWM output pins (PWMn: n = 0, 1). The PWMC can be read or written to with an 8-bit manipulation instruction or bit manipulation instruction. Its format is shown in Figure 13-2.
Page 380: Pwm Prescaler Register (Pwpr)
CHAPTER 13 PWM OUTPUT UNIT 13.2.2 PWM Prescaler Register (PWPR) The PWPR is an 8-bit register that selects the PWM output circuit operating clock (f PWMC The PWPR can be read or written to with an 8-bit manipulation instruction. Its format is shown in Figure 13-3. When RESET is input, PWPR is cleared to 00H, and f is selected as f for both channels.
Page 381: Pwm Output Unit Operation
CHAPTER 13 PWM OUTPUT UNIT 13.3 PWM OUTPUT UNIT OPERATION 13.3.1 Basic PWM Output Operation The PWM pulse output duty is determined by the value set in bits 4 to 15 of the PWM modulo register (PWMn: n = 0, 1) as shown below.
Page 382: Pwm Pulse Output Enabling/Disabling
CHAPTER 13 PWM OUTPUT UNIT 13.3.2 PWM Pulse Output Enabling/Disabling When PWM pulses are output, the ENn (n = 0, 1) bits of the PMC register are set (to 1) after data is set in the PWM prescaler register (PWPR) and PWM modulo register (PWMn: n = 0, 1). As a result, PWM pulses with the active level specified by ALVn (n = 0, 1) bit of the PWM control register (PWMC) are output from the PWM output pin.
Page 383: Pwm Pulse Width Rewrite Cycle Specification
CHAPTER 13 PWM OUTPUT UNIT 13.3.4 PWM Pulse Width Rewrite Cycle Specification The start of PWM output and pulse width changes are performed in synchronization either with every 16 PWM pulse cycles (2 ) or with every PWM pulse cycle (2 ).
Page 384: Caution
CHAPTER 13 PWM OUTPUT UNIT Figure 13-7 PWM Output Timing Example 2 (PWM Pulse Width Rewrite Cycle = 2 PWMC 1 PWM Pulse Cycle Output Pin PWMn Contents PWMn PWMn PWMn Output Rewrite Rewrite Rewrite PWM Pulse Width Enabled Switching Timing Cautions 1.
Page 385: Chapter 14 A/D Converter
CHAPTER 14 A/D CONVERTER The µ PD784038 incorporates an analog/digital (A/D) converter with 8 multiplexed analog inputs (ANI0 to ANI7). The successive approximation conversion method is used, and the conversion result is held in the 8-bit A/D conversion result register (ADCR). This allows fast, high-precision conversion to be performed (conversion time of 7.5 µ s when f = 16 MHz and high-speed conversion is used).
Page 386 ANI0 Series Resistor String ANI1 Sample & Hold Circuit ANI2 REF1 ANI3 Input Selector ANI4 ANI5 Voltage Comparator ANI6 ANI7 selector Successive Approximation Register (SAR) Edge Detection Conversion Trigger INTP5 Circuit Control Circuit INTAD Trigger Enable A/D Converter Mode A/D Conversion Result RESET Register (ADM) Register (ADCR)
Page 387 CHAPTER 14 A/D CONVERTER Cautions 1. A capacitor should be connected between the analog input pins (ANI0 to ANI7) and AV between the reference voltage input pin (AV ) and AV to prevent malfunction due to noise. Be sure to connect the capacitor as closely to ANI0 through ANI7 and AV as possible.
Page 388 CHAPTER 14 A/D CONVERTER (5) SAR: Successive Approximation Register The SAR is an 8-bit register in which the data for which the series resistor string voltage tap value matches the analog input voltage value is set bit by bit starting from the most significant bit (MSB). When data has been set up to the least significant bit (LSB) of the SAR (when A/D conversion is completed), the SAR contents (conversion result) are stored in the A/D conversion result register (ADCR).
Page 389: A/D Converter Mode Register (Adm)
CHAPTER 14 A/D CONVERTER 14.2 A/D CONVERTER MODE REGISTER (ADM) ADM is an 8-bit register that controls A/D converter operations. The ADM register can be read or written to with an 8-bit manipulation instruction or bit manipulation instruction. Its format is shown in Figure 14-3.
Page 390 CHAPTER 14 A/D CONVERTER Figure 14-3 A/D Converter Mode Register (ADM) Format Address After Reset SCMD ANIS2 ANIS1 ANIS0 0FF68H A/D Conversion Operating ANIS2 ANIS1 ANIS0 Mode Setting Scan ANI0 input scanned mode Input ANI0 & ANI1 scanned (0/1) Input ANI0 to ANI2 scanned Input ANI0 to ANI3 scanned Input ANI0 to ANI4 scanned Input ANI0 &...
Page 391 CHAPTER 14 A/D CONVERTER Caution Once the A/D converter starts operating, conversion operations are performed repeatedly until the CS bit of the A/D converter mode register (ADM) is cleared (to 0). Therefore, a superfluous interrupt may be generated if ADM setting is performed after interrupt-related registers, etc., when A/D converter mode conversion, etc., is performed.
Page 392: Operation
CHAPTER 14 A/D CONVERTER 14.3 OPERATION 14.3.1 Basic A/D Converter Operation (1) A/D Conversion Operation procedure A/D conversion is performed by means of the following procedure: (a) Analog pin selection and operating mode specification are set with the A/D converter mode register (ADM). (b) Bit 7 (CS) of the ADM is set (to 1), and A/D conversion is started.
Page 393 CHAPTER 14 A/D CONVERTER (h) When comparison of the 8 bits is completed, a valid digital result is left in the SAR, and that value is transferred to the A/D conversion result register (ADCR) and latched. An A/D conversion operation end interrupt request (INTAD) can be generated at the same time. Figure 14-4 Basic A/D Converter Operation Conversion Time Sampling Time...
Page 394 CHAPTER 14 A/D CONVERTER (2) Input voltage and conversion result The relationship between the analog input voltage input to an analog input pin (ANI0 to ANI7) and the A/D conversion result (value stored in ADCR) is shown by the following expression: ×...
Page 395 CHAPTER 14 A/D CONVERTER (3) A/D conversion time The A/D conversion time is determined by the system clock frequency (f ) and the FR bit of the A/D converter mode register (ADM). The A/D conversion time includes the entire time required for one A/D conversion operation, and the sampling time is also included in the A/D conversion time.
Page 396: Select Mode
CHAPTER 14 A/D CONVERTER 14.3.2 Select Mode One analog input is specified by bits 1 to 3 (ANIS0 to ANIS2) of the A/D converter mode register (ADM), and A/D conversion of the specified analog input pin is started. The conversion result is stored in the A/D conversion result register (ADCR).
Page 397: Scan Mode
CHAPTER 14 A/D CONVERTER 14.3.3 Scan Mode Two scan modes, 1 and 0, are available. In scan mode 0, delay control that takes delay in reading the A/D conversion result by the CPU into consideration can be performed. In scan mode 1, no delay control is performed but the A/D conversion interval is fixed.
Page 398 CHAPTER 14 A/D CONVERTER (2) Scan mode 1 (bit 5 (SCMD) of A/D converter mode register (ADM) = 1) When bit 5 of the ADM is set (to 1), the analog input pins specified by bits 1 to 3 (ANIS0 to ANIS2) are selected, and subjected to conversion, in order.
Page 399: A/D Conversion Operation Start By Software
CHAPTER 14 A/D CONVERTER 14.3.4 A/D Conversion Operation Start by Software An A/D conversion operation start by software is performed by writing a value to the A/D converter mode register (ADM) that sets the TRG bit of the ADM register to 0 and the CS bit to 1. If a value is written to the ADM during an A/D conversion operation (CS bit = 1) such that the TRG bit is set to 0 and the CS bit to 1 again, the A/D conversion operation being performed at that time is suspended, and A/D conversion is started immediately in accordance with the written value.
Page 400 CHAPTER 14 A/D CONVERTER (2) Scan mode A/D conversion operation When conversion operation is started, an A/D conversion operation is started on the ANI0 pin input. When the A/D conversion operation ends, an A/D conversion operation is started on the next analog input pin. An A/D conversion end interrupt request (INTAD) is generated at the end of each A/D conversion operation.
Page 401: A/D Conversion Operation Start By Hardware
CHAPTER 14 A/D CONVERTER 14.3.5 A/D Conversion Operation Start by Hardware An A/D conversion operation start by hardware is made possible by setting both the TRG bit and the CS bit of the A/D converter mode register (ADM) to 1. When the TRG bit and the CS bit of the ADM are both set to 1, external signals are placed in the standby state, and an A/D conversion operation is started when a valid edge is input to the INTP5 pin (P26 pin).
Page 402 CHAPTER 14 A/D CONVERTER (1) Select mode A/D conversion operation An A/D conversion operation is started on the analog input pin set by the A/D converter mode register (ADM). As soon as the A/D conversion operation ends, another A/D conversion operation is performed on the same analog input pin. An A/D conversion end interrupt request (INTAD) is generated at the end of each A/D conversion operation.
Page 403 INTP5 Pin Input (Rising Edge Valid) A/D Conversion (ANI0 to ANII2 Standby State ANI1 ANI2 ANI0 ANI1 ANI0 ANI0 ANI1 ANI2 Standby State ANI0 ANI1 ANI2 ANI0 ANI0 Scanned) ADM Rewrite ADM Rewrite CS ← 1, TRG ← 1 CS ← 1, TRG ← 1 ADCR ANI0 ANI1...
Page 404: External Circuit Of A/D Converter
CHAPTER 14 A/D CONVERTER 14.4 EXTERNAL CIRCUIT OF A/D CONVERTER The A/D converter is provided with a sample & hold circuit to stabilize its conversion operation. This sample & hold circuit outputs sampling noise during sampling immediately after an A/D conversion channel has been changed. To absorb this sampling noise, an external capacitor must be connected.
Page 405 CHAPTER 14 A/D CONVERTER Figure 14-13 Example of Capacitor Connection on A/D Converter Pins µ PD784038 Analog ANI0 to ANI7 Input 100 to 500 pF Reference REF1 Voltage Input (4) When the STOP mode or IDLE mode is used, the power consumption should be reduced by clearing (to 0) the CS bit before entering the STOP or IDLE mode.
Page 406: Chapter 15 D/A Converter
CHAPTER 15 D/A CONVERTER The µ PD784038 incorporates an 8-bit resolution voltage output type digital/analog (D/A) converter, which uses the R- 2R resistor ladder type. 15.1 CONFIGURATION The D/A converter block diagram is shown in Figure 15-1. Figure 15-1 D/A Converter Block Diagram ANOn REF2 Selector...
Page 407: D/A Converter Mode Register (Dam)
CHAPTER 15 D/A CONVERTER • D/A conversion value setting registers (DACS0, DACS1) These registers are used to set the voltage values to be output to the ANOn pins (n = 0, 1). The voltage value output to the ANOn pin is given by the following expression: –...
Page 408: D/A Converter Operation
CHAPTER 15 D/A CONVERTER 15.3 D/A CONVERTER OPERATION 15.3.1 Basic Operation When the value to be output is written to the D/A conversion value setting register (DACSn, n = 0, 1) while the D/A conversion enable bit (DACEn, n = 0, 1) of the D/A converter mode register (DAM) is set (to 1), an analog voltage corresponding to the value written is output from the ANOn pin (n = 0, 1).
Page 409: Cautions
CHAPTER 15 D/A CONVERTER 15.4 CAUTIONS (1) As the D/A converter output impedance is high, a current cannot be taken from the ANOn pin (n = 0, 1). If the load input impedance is low, a buffer amplifier should be inserted between the load and the ANOn pin. Also, the wiring to the buffer amp and load should be kept as short as possible (since the output impedance is high).
Page 410: Chapter 16 Outline Of Serial Interface
CHAPTER 16 OUTLINE OF SERIAL INTERFACE The µ PD784038 Subseries is provided with three independent serial interface channels. Therefore, communication with an external system and local communication within the system can be simultaneously executed by using these three channels. • Asynchronous serial interface (UART)/3-wire serial I/O (IOE) × 2 channels →...
Page 411 CHAPTER 16 OUTLINE OF SERIAL INTERFACE Figure 16-1 shows an example of the serial interface. Figure 16-1 Example of Serial Interface (1) UART + I µ PD784038Y (master) EEPROM [UART] RS-232-C driver/ receiver Port Microcontroller (slave) [UART] RxD2 RS-232-C TxD2 driver/ receiver Port...
Page 412: Chapter 17 Asynchronous Serial Interface/3-Wire Serial I/O
CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O The µ PD784038 incorporates two serial interface channels for which asynchronous serial interface (UART) mode or 3-wire serial I/O (IOE) mode can be selected. The two UART/IOE channels have completely identical functions. In this chapter, therefore, unless stated otherwise, UART/IOE1 will be described as representative of both UART/IOEs.
Page 413: Switching Between Asynchronous Serial Interface Mode And 3-Wire Serial I/O Mode
CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O 17.1 SWITCHING BETWEEN ASYNCHRONOUS SERIAL INTERFACE MODE AND 3-WIRE SERIAL I/O MODE The asynchronous serial interface mode and 3-wire serial I/O mode cannot be used simultaneously. Switching between these modes is performed in accordance with the settings of the asynchronous serial interface mode register (ASIM/ASIM2) and the clocked serial interface mode register (CSIM1/CSIM2) as shown in Figure 17-1.
Page 414: Asynchronous Serial Interface Mode
CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O 17.2 ASYNCHRONOUS SERIAL INTERFACE MODE A UART (Universal Asynchronous Receiver Transmitter) is incorporated as the asynchronous serial interface. With this method, one byte of data is transmitted following a start bit, and full-duplex operation is possible. A baud rate generator is incorporated, enabling communication to be performed at any of a wide range of baud rates.
Page 415 Internal Bus ASIM, ASIM2 ISRM RXB, RXB2 Receive Buffer RESET TXE2 RXE2 PS21 PS20 ISRM2 SCK2 ASIS, ASIS2 P30/R Transmit Shift Register RESET P13/R Shift Register TXS2 OVE2 P31/T P14/T Transmission Reception INTSER, INTST, Control Parity Control INTSER2 INTST2 Addition Parity Check INTSR, INTSR2 Baud Rate Generator...
Page 416 CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O (1) Receive buffer (RXB/RXB2) This is the register that holds the receive data. Each time one byte of data is received, the receive data is transferred from the shift register. If a 7-bit data length is specified, receive data is transferred to bits 0 to 6 of RXB/RXB2, and the MSB of RXB/RXB2 is always “0”.
Page 417: Asynchronous Serial Interface Control Registers
CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O 17.2.2 Asynchronous Serial Interface Control Registers (1) Asynchronous serial interface mode register (ASIM), Asynchronous serial interface mode register 2 (ASIM2) The ASIM and ASIM2 are 8-bit registers that specify the UART mode operation. These registers can be read or written to with an 8-bit manipulation instruction or bit manipulation instruction.
Page 418 CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O Figure 17-3 Format of Asynchronous Serial Interface Mode Register (ASIM) and Asynchronous Serial Interface Mode Register 2 (ASIM2) Address After Reset ASIM ISRM 0FF88H ASIM2 TXE2 RXE2 PS21 PS20 ISRM2 SCK2 0FF89H Specification of Input Clock to Baud Rate Generator SCK2 External clock input (ASCK, ASCK2)
Page 419 CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O Note To disable the reception completion interrupt on occurrence of a reception error, insert wait cycles of two clocks that serve as the reference of the baud rate clock after occurrence of the reception error and before the receive buffers (RXB and RXB2) are read.
Page 420 CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O (2) Asynchronous serial interface status register (ASIS) Asynchronous serial interface status register 2 (ASIS2) The ASIS and ASIS2 contain flags that indicate the error contents when a receive error occurs. Flags are set (to 1) when a receive error occurs, and cleared (to 0) when data is read from the receive buffer (RXB/RXB2).
Page 421: Data Format
CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O 17.2.3 Data Format Serial data transmission/reception is performed in full-duplex asynchronous mode. The transmit/receive data format is shown in Figure 17-5. One data frame is made up of a start bit, character bits, parity bit, and stop bit(s).
Page 422: Parity Types And Operations
CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O 17.2.4 Parity Types and Operations The parity bit is used to detect a bit error in the communication data. Normally, the same kind of parity bit is used on the transmission side and the reception side. With even parity and odd parity, 1 bit (odd number) errors can be detected. With 0 parity and no parity, errors cannot be detected.
Page 423: Transmission
CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O 17.2.5 Transmission The µ PD784038’s asynchronous serial interface is set to the transmission enabled state when the TXE bit of the asynchronous serial interface mode register (ASIM) is set (to 1). A transmit operation is started by writing transmit data to the transmit shift register (TXS) when transmission is enabled.
Page 424: Reception
CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O 17.2.6 Reception When the RXE bit of the asynchronous serial interface mode register (ASIM) is set (to 1), receive operations are enabled and sampling of the RxD input pin is performed. RxD input pin sampling is performed using the serial clock (divide-by-m counter input clock) specified by ASIM and band rate generator control register (BRGC).
Page 425: Receive Errors
CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O 17.2.7 Receive Errors Three kinds of errors can occur in a receive operation: parity errors, framing errors and overrun errors. As the result of data reception, an error flag is raised in the asynchronous serial interface status register (ASIS) and a receive error interrupt (INTSER) is generated.
Page 426 CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O Cautions 1. The contents of the asynchronous serial interface status register (ASIS) are cleared (to 0) by reading the receive buffer (RXB) or by reception of the next data. If you want to find the details of an error, therefore, ASIS must be read before reading RXB.
Page 427: 3-Wire Serial I/O Mode
CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O 17.3 3-WIRE SERIAL I/O MODE The 3-wire serial I/O mode is used to communicate with devices that incorporate a conventional clocked serial interface. Basically, communication is performed using three lines: the serial clock (SCK), serial data output (SO), and serial data input (SI).
Page 428 Internal Bus CTXE1 CRXE1 DIR1 CSCK1 RESET Direction Control Circuit CTXE2 CRXE2 DIR2 CSCK2 SO Latch P30/SI1, Shift Register P13/SI2 P31/SO1, P14/SO2 Interrupt Signal P25/SCK1, INTCSI1, INTCSI2 Serial Clock Counter Generator P12/SCK2 Baud Rate Generator Selector Serial Clock Control Circuit CSCK1, CSCK2 CSCK1, CSCK2...
Page 429 CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O (1) Shift register (SIO1/SIO2) The SIO1 and SIO2 converts 8-bit serial data to 8-bit parallel data, and vice versa. SIO1/SIO2 is used for both transmission and reception. Actual transmit/receive operations are controlled by writing to/reading from SIO1/SIO2. Reading/writing can be performed with an 8-bit manipulation instruction.
Page 430: Clocked Serial Interface Mode Registers (Csim1, Csim2)
CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O 17.3.2 Clocked Serial Interface Mode Registers (CSIM1, CSIM2) The CSIM1 and CSIM2 are 8-bit registers that specify operations in the 3-wire serial I/O mode. These registers can be read or written to with an 8-bit manipulation instruction or bit manipulation instruction. The CSIM1 and CSIM2 format is shown in Figure 17-11.
Page 431: Basic Operation Timing
CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O 17.3.3 Basic Operation Timing In the 3-wire serial I/O mode, data transmission/reception is performed in 8-bit units. Data is transmitted/received bit by bit in MSB-first or LSB-first order in synchronization with the serial clock. MSB/LSB switching is specified by the DIRn bit of the clock serial interface mode register (CSIMn).
Page 432 CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O Figure 17-12 3-Wire Serial I/O Mode Timing (2/2) (b) LSB-first Note SCKn SIn (Input) DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 SOn (Output) INTCSIn Transfer End Interrupt Generation Start of transfer synchronized with fall of SCKn Note Master CPU: Output Slave CPU: Input Execution of instruction that writes to SIOn...
Page 433: Operation When Transmission Only Is Enabled
CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O 17.3.4 Operation When Transmission Only is Enabled A transmit operation is performed when the CTXEn bit of clocked serial interface mode register (CSIMn) is set (to 1). The transmit operation starts when a write to the shift register (SIOn) is performed while the CTXEn bit is set (to 1). When the CTXEn bit is cleared (to 0), the SOn pin is in the output high level.
Page 434: Operation When Transmission/Reception Is Enabled
CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O 17.3.6 Operation When Transmission/Reception is Enabled When the CTXEn bit and CRXEn bit of the clocked serial interface mode register (CSIMn) register are both set (to 1), a transmit operation and receive operation can be performed simultaneously (transmit/receive operation). The transmit/ receive operation is started when the CRXEn bit is changed from “0”...
Page 435: Corrective Action In Case Of Slippage Of Serial Clock And Shift Operations
CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O 17.3.7 Corrective Action in Case of Slippage of Serial Clock and Shift Operations When an external clock is selected as the serial clock, there may be slippage between the number of serial clocks and shift operations due to noise, etc.
Page 436 Start Bit Detection Internal Bus RESET CSIM1, CSIM2 ASIM1, ASIM2 BRGC, BRGC2 Asynchronous Serial Clock Serial Baud Rate Generator 5-Bit Counter Interface Mode Interface Mode RESET Control Register Registers 1 & 2 Registers 1 & 2 Clear Start Bit Detection Match UART Reception Sampling Clock...
Page 437: Baud Rate Generator Control Register (Brgc, Brgc2)
CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O (1) 5-bit counter Counter that counts the clock (f ) by which the output from the frequency divider is selected. Generates a signal with the frequency selected by the low-order 4 bits of the baud rate generator control registers (BRGC/BRGC2). (2) Frequency divider Scales the internal clock (f /2) or, in asynchronous serial interface mode, a clock that is twice the external baud rate...
Page 438 CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O Figure 17-15 Baud Rate Generator Control Register (BRGC) Format and Baud Rate Generator Control Register 2 (BRGC2) Format Address After Reset BRGC TPS3 TPS2 TPS1 TPS0 MDL3 MDL2 MDL1 MDL0 0FF90H BRGC2 0FF91H TPS23 TPS22 TPS21 TPS20 MDL23 MDL22 MDL21 MDL20 : Prescaler output selection clock MDL3...
Page 439: Baud Rate Generator Operation
CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O 17.4.3 Baud Rate Generator Operation The baud rate generator only operates when UART/IOE transmit/receive operations are enabled. The generated baud rate clock is a signal scaled from the internal clock (f /2) or a signal scaled from the clock input from the external baud rate input (ASCK) pin.
Page 440 CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O (2) Serial clock generation in 3-wire serial I/O mode Selected when the CSCK1 bit of the clocked serial interface mode register (CSIM1) is set (to 1) and SCK1 is output. (a) Normal mode The internal clock (f /2) is scaled by the frequency divider, this signal (f ) is scaled by the 5-bit counter, and...
Page 441: Baud Rate Setting In Asynchronous Serial Interface Mode
CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O 17.4.4 Baud Rate Setting in Asynchronous Serial Interface Mode There are two methods of setting the baud rate, as shown in Table 17-3. This table shows the range of baud rates that can be generated, the baud rate calculation expression and selection method for each case.
Page 443 CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O (2) Examples of settings when external baud rate input (ASCK) is used Table 17-5 shows an example of setting when external baud rate input (ASCK) is used. When using the ASCK input, clear the SCK bit of the asynchronous serial interface mode register (ASIM) to 0, and set the corresponding pin in the control mode by using PMC3 or PMC1.
Page 444: Cautions
CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O 17.5 CAUTIONS (1) An asynchronous serial interface mode register (ASIM) rewrite should not be performed during a transmit operation. If an ASIM rewrite is performed during a transmit operation, subsequent transmit operations may not be possible (normal operation is restored by RESET input).
Page 445 CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O (8) When data is successively transmitted from the transmission side in 3-wire serial I/O mode, the second and subsequent receive data may be undefined under the following conditions <1> and <2>. <1> Read from the shift register (SIOn) is not completed in the period from reception completion (a in the figure below) to the next fall of the serial clock (SCKn) (b in the figure below) (n = 1 or 2) <2>...
Page 446: Chapter 18 3-Wire/2-Wire Serial I/O Mode
CHAPTER 18 3-WIRE/2-WIRE SERIAL I/O MODE 18.1 FUNCTIONS (1) 3-wire serial I/O mode (MSB/LSB first) In this mode, 8-bit data are transferred by using three lines, a serial clock line (SCK0) and two serial bus lines (SO0 and SI0). This mode is useful when connecting a peripheral I/O or display controller having the conventional clocked serial interface.
Page 447 CHAPTER 18 3-WIRE/2-WIRE SERIAL I/O MODE Figure 18-1 Block Diagram of Clocked Serial Interface (in 3-wire/2-wire serial mode) Internal Bus CSIM IICC Direction Control RESET RESET Circuit CTXE CRXE MOD1 MOD0 CLS1 CLS0 SPT STT CLEAR P27/SI0 Selector Shift Register (SIO) SO Latch P33/SO0/SDA RESET...
Page 448 CHAPTER 18 3-WIRE/2-WIRE SERIAL I/O MODE (1) Shift register (SIO) The SIO converts 8-bit serial data to 8-bit parallel data, and vice versa. SIO is used for both transmission and reception. Actual transmit/receive operations are controlled by writing to/reading from SIO. SIO can be read or written to with an 8-bit manipulation instruction.
Page 449: Control Registers
CHAPTER 18 3-WIRE/2-WIRE SERIAL I/O MODE 18.3 CONTROL REGISTERS 18.3.1 Clocked Serial Interface Mode Register (CSIM) The CSIM is an 8-bit register that specifies the serial interface operating mode, serial clock, etc. This register can be read or written to with an 8-bit manipulation instruction or bit manipulation instruction. The CSIM format is shown in Figure 18-2.
Page 450: Prescaler Mode Register For Serial Clock (Sprm)
CHAPTER 18 3-WIRE/2-WIRE SERIAL I/O MODE Caution When changing from “CTXE = 0, CRXE = 1” to “CTXE = 1, CRXE = 0”, and when changing from “CTXE = 1, CRXE = 0” to “CTXE = 0, CRXE = 1”, ensure that this is not done with a single instruction, as this will result in malfunction of the serial clock counter, and the first communication after the change will finish in fewer than 8 bits.
Page 451: C Bus Control Register (Iicc)
CHAPTER 18 3-WIRE/2-WIRE SERIAL I/O MODE 18.3.3 I C Bus Control Register (IICC) IICC is an 8-bit register composed of bits which control the SO latch status. IICC is read or written with 8-bit manipulation instructions and bit manipulation instructions. When a read is performed, IICC is read as “00”.
Page 452: Basic Operation Timing
CHAPTER 18 3-WIRE/2-WIRE SERIAL I/O MODE 18.4.1 Basic Operation Timing In the 3-wire serial I/O mode, data transmission/ reception is performed in 8-bit units. Data is transmitted/received bit by bit in MSB-first or LSB-first order in synchronization with the serial clock. MSB first/LSB first switching is specified by the MOD 0 bit of the clocked serial interface mode register (CSIM).
Page 453 CHAPTER 18 3-WIRE/2-WIRE SERIAL I/O MODE Figure 18-6 3-Wire Serial I/O Mode Timing (2/2) (b) LSB-first Note SCK0 SI0 (Input) DO1 DO2 DO3 DO4 DO5 DO6 DO7 SO0 (Output) INTCSI Transfer End Interrupt Generation Note Master CPU: Output Slave CPU: Input Transfer starts after execution of a write instruction to SIO In the 3-wire serial I/O mode, the SO0 pin functions as a CMOS push-pull output.
Page 454 CHAPTER 18 3-WIRE/2-WIRE SERIAL I/O MODE 18.4.2 Operation When Transmission Only is Enabled A transmit operation is performed when the CTXE bit of the clocked serial interface mode register (CSIM) is set (to 1). The transmit operation starts when a write to the shift register (SIO) is performed while the CTXE1 bit is set (to 1). When the CTXE bit is cleared (to 0), the SO0 pin is in the output high impedance state.
Page 455 CHAPTER 18 3-WIRE/2-WIRE SERIAL I/O MODE 18.4.4 Operation When Transmission/Reception is Enabled When the CTXE bit and CRXE bit of the clocked serial interface mode register (CSIM) are both set (to 1), a transmit operation and receive operation can be performed simultaneously (transmit/receive operation). The transmit/receive operation is started when the CRXE bit is changed from “0”...
Page 456 CHAPTER 18 3-WIRE/2-WIRE SERIAL I/O MODE 18.5 2-WIRE SERIAL I/O MODE The 2-wire serial I/O mode an support any communication format depending on the program. Basically, communication is performed by using two lines, a serial clock line (SCL) and a serial data input/output line (SDA).
Page 457 CHAPTER 18 3-WIRE/2-WIRE SERIAL I/O MODE 18.5.1 Basic Operation Timing In the 2-wire serial I/O mode, data are transferred/received in 8-bit units. Data are transferred/received in synchronization with the serial clock in 1-bit units with the MSB first. Transmit data is output at the falling edge of SCL. Receive data is sampled at the rising edge of SCL. An interrupt request (INTCSI) is generated at the eighth rising edge of SCL.
Page 458 CHAPTER 18 3-WIRE/2-WIRE SERIAL I/O MODE 18.5.2 Operation When Transmission Only is Enabled A transmit operation is performed when the CTXE bit of the clocked serial interface mode register (CSIM) is set (to 1). The transmit operation starts when a write to the shift register (SIO) is performed while the CTXE1 bit is set (to 1). When the CTXE bit is cleared (to 0), the SDA pin is in the output high impedance state.
Page 459 CHAPTER 18 3-WIRE/2-WIRE SERIAL I/O MODE 18.5.4 Operation When Transmission/Reception is Enabled When the CTXE bit and CRXE bit of the clocked serial interface mode register (CSIM) are both set (to 1), a transmit operation and receive operation can be performed simultaneously (transmit/receive operation). The transmit/receive operation is started when the CRXE bit is changed from “0”...
Page 460 CHAPTER 18 3-WIRE/2-WIRE SERIAL I/O MODE 18.6 CAUTIONS (1) When changing from “CTXE = 0, CRXE = 1” to “CTXE = 1, CRXE = 0”, and when changing from “CTXE = 1, CRXE = 0” to “CTXE = 0, CRXE = 1”, ensure that this is not done with a single instruction, as this will result in malfunction of the serial clock counter, and the first communication after the change will finish in fewer than 8 bits.
Page 461 CHAPTER 18 3-WIRE/2-WIRE SERIAL I/O MODE (4) When master transmission and slave reception are executed alternately in 3-wire serial I/O mode, an invalid serial clock may be output from the SCK0 pin. (Not applicable to SCK1 and SCK2 pins) Set SCK0 to high-level output port mode in the period in which the invalid clock (1 system clock max.) indicated in attachment 2 may be generated when alternately executing master transmission and slave reception.
Page 462 CHAPTER 18 3-WIRE/2-WIRE SERIAL I/O MODE (5) When data is successively transmitted from the transmission side in 3-wire serial I/O mode, the second and subsequent receive data may be undefined under the following conditions <1> and <2>. <1> Read from the shift register (SIO) is not completed in the period from reception completion (a in the figure below) to the next fall of the serial clock (SCK0) (b in the figure below) <2>...
Page 463 C BUS MODE ( µ PD784038Y SUBSERIES ONLY) CHAPTER 19 I 19.1 OUTLINE OF FUNCTIONS • I C (INTER IC) bus mode (MSB First) The I C bus mode is an interface for communicating with devices that conform with the I C bus format.
Page 464 Internal bus CSIM IICC Slave address RESET RESET RESET CTXE WUP CLS1 CLS0 register (SVA) SPT STT SPD STD ACKE ACKD WREL WTIM match signal CLEAR SO latch P33/SO0/SDA Shift register (SIO) DHT0 Data hold time RESET correction circuit DHT1 N-ch open drain output Acknowledge detection circuit...
Page 465 C BUS MODE ( µ PD784038Y SUBSERIES ONLY) CHAPTER 19 I (1) Shift register (SIO) The SIO register converts 8-bit serial data to 8-bit parallel data or vice versa. It is used both for transmission and reception. Actual transmission and reception is controlled by writing/reading to/from the SIO register. Reading and writing is performed with 8-bit manipulation instructions.
Page 466 C BUS MODE ( µ PD784038Y SUBSERIES ONLY) CHAPTER 19 I 19.3 CONTROL REGISTER 19.3.1 Clocked Serial Interface Mode Register (CSIM) CSIM is an 8-bit register used to specify the serial interface operation mode, serial clock, wakeup function, and so on. It is read/written with 8-bit manipulation instructions.
Page 467 C BUS MODE ( µ PD784038Y SUBSERIES ONLY) CHAPTER 19 I Figure 19-4 I C Bus Control Register (IICC) Format (1/2) Address After Reset IICC WTIM WREL ACKD ACKE 0FF80H Wait Timing Setting Bit (R/W) This bit controls the interrupt generation timing and wait timing control during data reception. Rewrite this bit only when transmission/reception is prohibited (CTXE = 0).
Page 468 The level of SDA can be checked by using the P33/SDA pin as an input pin (PM33 = 1) and reading SDA 2. SCL and SDA are defined as reserved words when using an NEC Electronics assembler, and as sfr variables using the #pragma sfr command in C compiler.
Page 469 C BUS MODE ( µ PD784038Y SUBSERIES ONLY) CHAPTER 19 I 19.3.3 Prescaler Mode System for Serial Clock (SPRM) SPRM is an 8-bit register used to specify the serial clock and duty when the data hold time in relation to the falling edge of SCL and the serial clock are specified for the internal clock (CLS1 bit = 1, CLS0 bit 0).
Page 470 C BUS MODE ( µ PD784038Y SUBSERIES ONLY) CHAPTER 19 I 19.3.4 Slave Address Register (SVA) SVA is an 8-bit register used to specify the microcomputer’s address when it is used as a slave device. Bit 0 of SVA (TRE bit) can be used to check whether transmission or reception is performed. Bits 1 to 7 are read/written with an 8-bit manipulation instruction.
Page 471 C BUS MODE ( µ PD784038Y SUBSERIES ONLY) CHAPTER 19 I 19.4 I C BUS MODE FUNCTION 19.4.1 Pin Configuration The serial clock pin (SCL) and serial data bus pin (SDA) are configured as follows: (1) SCL ······ Pin that inputs/outputs serial clock •...
Page 472 C BUS MODE ( µ PD784038Y SUBSERIES ONLY) CHAPTER 19 I 19.4.2 Functions C bus mode of µ PD784038Y. The following function is available in the I (1) Automatic identification of serial data The “start condition”, “data” and “stop condition” on the serial data bus are automatically detected. (2) Chip select by address The master can select specific slave device from those connected to the I C bus by transmitting a slave address and...
Page 473 C BUS MODE ( µ PD784038Y SUBSERIES ONLY) CHAPTER 19 I 19.5 DEFINITION AND CONTROL METHOD OF THE I C BUS The following describes the serial data communication format of the I C bus and the meanings of the signals used. Figure 19-8 shows the transfer timing of the “start condition”, “data”, and “stop condition”...
Page 474 C BUS MODE ( µ PD784038Y SUBSERIES ONLY) CHAPTER 19 I 19.5.2 Addresses The 7-bit data following the start condition is defined to be an address. An address is 7 bit of data output by the master to select a specific slave from those connected to the bus line. Therefore, all the slaves on the bus line must have a different address.
Page 475 C BUS MODE ( µ PD784038Y SUBSERIES ONLY) CHAPTER 19 I 19.5.3 Transfer Direction Specification The master transmits the 1-bit data to specify the transfer direction following 7-bit address. The transfer direction specification bit 0 indicates data transmission from the master to the slave. On the other hand, the transfer specification bit 1 indicates data reception from the slave to the master.
Page 476 C BUS MODE ( µ PD784038Y SUBSERIES ONLY) CHAPTER 19 I 19.5.4 Acknowledge Signal (ACK) The acknowledge signal is used to confirm that serial data has been received at transmission and reception sides. The reception side returns the acknowledge signal each time it has received 8 bits of data. However, do not return ACK on receiving the last data when a start condition or stop condition is to be issued while the master receives data (refer to Figure 19-16).
Page 477 C BUS MODE ( µ PD784038Y SUBSERIES ONLY) CHAPTER 19 I 19.5.5 Stop Condition The stop condition is set when the SDA pin goes high while the SCL pin is high. The stop condition is output by the master to the slave when serial transfer has been completed. Figure 19-13 Stop Condition The Stop condition is generated by setting SPT (to 1).
Page 478 C BUS MODE ( µ PD784038Y SUBSERIES ONLY) CHAPTER 19 I 19.5.6 Wait Signal (WAIT) The wait signal is output by a slave to the master to indicate that the slave is waiting to send/receive data (wait status). The slave informs the master that it is the wait status by making SCL pin low. When the slave is released from the wait status, the master can start the next transfer.
Page 479 C BUS MODE ( µ PD784038Y SUBSERIES ONLY) CHAPTER 19 I Figure 19-14 Wait Signal (2/2) (2) When nine clocks wait for master and slave (Master: Transmission, Slave: reception, ACKE = 1) Master Both master and slave wait after the 9th clock has been output. SIO ←...
Page 480 C BUS MODE ( µ PD784038Y SUBSERIES ONLY) CHAPTER 19 I 19.5.7 Interrupt Request (INTCSI) Generation Timing and Wait Control The interrupt request is generated when the combination of the WUP bit of the clock synchronous serial interface (CSIM) and the WTIM bit of the I C bus control register (IICC) are correspond with the timings shown in Figure 19-1 and also wait is controlled by the same manner.
Page 481 C BUS MODE ( µ PD784038Y SUBSERIES ONLY) CHAPTER 19 I 19.5.8 Interrupt Request Generation Timing INTSPC is generated at the detection of the stop condition. Processing to wait the generation of the next start condition is required in the INTSPC interrupt routine. This is applied when used as a slave or WUP = 0.
Page 482 C BUS MODE ( µ PD784038Y SUBSERIES ONLY) CHAPTER 19 I Figure 19-15 Example of Communication from Master to Slave (with 9-clock wait selected for both master and slave. Slave: WUP = 0) (1/3) (1) Start condition = address Processing in Master Device SIO ←...
Page 483 C BUS MODE ( µ PD784038Y SUBSERIES ONLY) CHAPTER 19 I Figure 19-15 Example of Communication from Master to Slave (with 9-clock wait both selected for master and slave. Slave: WUP = 0) (2/3) (2) Data Processing in Master Device SIO ←...
Page 484 C BUS MODE ( µ PD784038Y SUBSERIES ONLY) CHAPTER 19 I Figure 19-15 Example of Communication from Master to Slave (with 9-clock wait both selected for master and slave. Slave: WUP = 0) (3/3) (3) Stop condition Processing in Master Device SIO ←...
Page 485 C BUS MODE ( µ PD784038Y SUBSERIES ONLY) CHAPTER 19 I Figure 19-16 Example of Communication from Slave to Master (When selecting the 9th clock wait both master and slave) (1/3) (1) Start condition = address Processing in Master Device SIO ←...
Page 486 C BUS MODE ( µ PD784038Y SUBSERIES ONLY) CHAPTER 19 I Figure 19-16 Example of Communication from Slave to Master (When selecting the 9th clock wait both master and slave) (2/3) (2) Data Processing in Master Device SIO ← FFH SIO ←...
Page 487 C BUS MODE ( µ PD784038Y SUBSERIES ONLY) CHAPTER 19 I Figure 19-16 Example of Communication from Slave to Master (When selecting the 9th clock wait both master and slave) (3/3) (3) Stop Condition Processing in Master Device SIO ← FFH SIO ←...
Page 488 C BUS MODE ( µ PD784038Y SUBSERIES ONLY) CHAPTER 19 I 19.7 SIGNAL AND FLAGS Table 19-2 lists the relationship between kinds of signals and flags in I C bus mode. Table 19-2 Relationship between Signals and Flags Outputting Conditions for Signal Definition Effect to Flag...
Page 489 CHAPTER 20 CLOCK OUTPUT FUNCTION The µ PD784038 has a clock function that outputs a signal scaled from the system clock. The clock output function can output the system clock directly, or a 1/2, 1/4, 1/8 or 1/16 system clock signal. In addition, it can be used as a 1-bit output port.
Page 490 CHAPTER 20 CLOCK OUTPUT FUNCTION (1) Clock output mode register (CLOM) Register that controls the operation of the clock output function. (2) Selector 1 Selector that selects the frequency of the clock to be output. (3) Output control Controls the output signal in accordance with the contents of the clock output mode register (CLOM). (4) Selector 2 Selects either the ASTB signal or the CLKOUT signal as the signal to be output to the ASTB/CLKOUT pin.
Page 491 CHAPTER 20 CLOCK OUTPUT FUNCTION 20.2 CLOCK OUTPUT MODE REGISTER (CLOM) The CLOM controls the clock output function. CLOM can be read or written to with an 8-bit manipulation instruction or bit manipulation instruction. The CLOM format is shown in Figure 20-2. RESET input clears the CLOM register to 00H.
Page 492 CHAPTER 20 CLOCK OUTPUT FUNCTION 20.3 OPERATION 20.3.1 Clock Output A signal with the clock output frequency selected by bits FS0 to FS2 is selected by selector 1 and output. The output signal has the same level as the LV bit when the CLE bit is cleared (to 0), and is output from the clock signal immediately after the CLE bit is set (to 1).
Page 493 CHAPTER 20 CLOCK OUTPUT FUNCTION 20.3.2 One-Bit Output Port When the CLE bit is cleared (to 0), the contents of the LV bit are output from the CLKOUT pin. The CLKOUT pin changes as soon as the contents of the LV bit change. Figure 20-4 One-Bit Output Port Operation CLKOUT SET1 LV Instruction Executed...
Page 494 CHAPTER 21 EDGE DETECTION FUNCTION P20 to P26 have an edge detection function that allows a rising edge/falling edge to be set programmably, and the detected edge is sent to internal hardware. The relation between pins P20 to P26 and the use of the detected edge is shown in Table 21-1.
Page 495 CHAPTER 21 EDGE DETECTION FUNCTION Figure 21-1 External Interrupt Mode Register 0 (INTM0) Format Address After Reset 0FFA0H INTM0 ES21 ES20 ES11 ES10 ES01 ES00 ESNMI P20 (NMI) Pin Input Detected Edge ESNMI Specification Falling edge Rising edge P21 (INTP0, CR11/CR11W Capture Trigger, TM1/TM1W Count Clock, ES01 ES00...
Page 496 CHAPTER 21 EDGE DETECTION FUNCTION Figure 21-2 External Interrupt Mode Register 1 (INTM1) Format Address After Reset 0FFA1H INTM1 ES51 ES50 ES41 ES40 ES31 ES30 P24 (INTP3, CR02 Capture Trigger, ES31 ES30 TM0 Count Clock) Pin Input Detected Edge Specification Falling edge Rising edge Setting prohibited...
Page 497 CHAPTER 21 EDGE DETECTION FUNCTION 21.1.2 Sampling Clock Selection Register (SCS0) The SCS0 specifies the sampling clock (f ) for digital noise elimination performed on pin P21. The SCS0 can be read or written to with an 8-bit manipulation instruction. The format of SCS0 is shown in Figure 21- RESET input clears the SCS0 register to 00H.
Page 498 CHAPTER 21 EDGE DETECTION FUNCTION 21.2 EDGE DETECTION FOR PINS P20, P25 AND P26 On pins P20, P25 and P26, noise elimination is performed by means of analog delay before edge detection. Therefore, an edge cannot be detected unless the pulse width is a given time (10 µ s) or longer. The width of the pulse eliminated as noise varies depending on the characteristics and ambient temperature of the device used.
Page 499 CHAPTER 21 EDGE DETECTION FUNCTION 21.3 EDGE DETECTION FOR PIN P21 In P21 edge detection, digital noise elimination is performed using the clock (f ) specified by the sampling clock selection register (SCS0). In digital noise elimination, input is sampled using the f clock, and if the input level is not the same at least four times in succession (if it is the same only three or fewer times in succession), it is eliminated as noise.
Page 500 CHAPTER 21 EDGE DETECTION FUNCTION 21.4 EDGE DETECTION FOR PINS P22 TO P24 Edge detection for pins P22 to P24 is performed after digital noise elimination by means of clock sampling. Unlike the P21 pin, f is used as the sampling clock. In digital noise elimination, input is sampled using the f clock, and if the input level is not the same at least four times in succession (if it is the same only three or fewer times in succession), it is eliminated as noise.
Page 501 CHAPTER 21 EDGE DETECTION FUNCTION 21.5 CAUTIONS (1) Valid edge detection cannot be performed when the valid edge is changed by a write to the external interrupt mode register (INTMn: n = 0, 1). Also, if an edge is input during a change of the valid edge, that edge may or may not be judged to be a valid edge.
Page 502 CHAPTER 22 INTERRUPT FUNCTIONS The µ PD784038 is provided with three interrupt request service modes (see Table 22-1). These three service modes can be set as required in the program. However interrupt service by macro service can only be selected for interrupt request sources provided with the macro service processing mode shown in Table 22-2.
Page 503 CHAPTER 22 INTERRUPT FUNCTIONS Table 22-2 Interrupt Request Sources (2/2) Macro Interrupt Type of Service Vector Default Interrupt Request Generating Control Context Macro Interrupt Control Table Priority Generating Source Unit Register Switching Service Request Word Address Name Address Maskable INTP0 (pin input edge detection) Edge PIC0 Possible...
Page 504 CHAPTER 22 INTERRUPT FUNCTIONS Remarks 1. The default priority is a fixed number. This indicates the order of priority when interrupt requests specified as having the same priority are generated simultaneously, 2. The INTSR and INTCSI1 interrupts are generated by the same hardware (they cannot both be used simultaneously).
Page 505 CHAPTER 22 INTERRUPT FUNCTIONS 22.2 INTERRUPT SERVICE MODES There are three µ PD784038 interrupt service modes, as follows: • Vectored interrupt service • Macro service • Context switching 22.2.1 Vectored Interrupt Service When an interrupt is acknowledged, the program counter (PC) and program status word (PSW) are automatically saved to the stack, a branch is made to the address indicated by the data stored in the vector table, and the interrupt service routine is executed.
Page 506 CHAPTER 22 INTERRUPT FUNCTIONS 22.3 INTERRUPT SERVICE CONTROL REGISTERS µ PD784038 interrupt service is controlled for each interrupt request by various control registers that perform interrupt service specification. The interrupt control registers are listed in Table 22-3. Table 22-3 Control Registers Register Name Symbol Function...
Page 507 CHAPTER 22 INTERRUPT FUNCTIONS Table 22-4 Interrupt Control Register Flags Corresponding to Interrupt Sources Interrupt Control Registers Interrupt Default Request Interrupt Interrupt Macro Service Priority Speci- Context Switching Priority Signal Request Flag Mask Flag Enable Flag fication Flag Enable Flag INTP0 PIC0 PIF0...
Page 508 CHAPTER 22 INTERRUPT FUNCTIONS 22.3.1 Interrupt Control Registers An interrupt control register is allocated to each interrupt source, and performs priority control, mask control, etc. for the corresponding interrupt request. The interrupt control register format is shown in Figure 22-1. ××...
Page 509 CHAPTER 22 INTERRUPT FUNCTIONS ×× ×× ×× ××ICn) (1/3) Figure 22-1 Interrupt Control Registers (×× Address After Reset PMK0 0FFE0H PIC0 PIF0 PISM0 PCSE0 PPR01 PPR00 0FFE1H PIC1 PIF1 PMK1 PISM1 PCSE1 PPR11 PPR10 0FFE2H PIC2 PIF2 PMK2 PISM2 PCSE2 PPR21 PPR20 PMK3...
Page 510 CHAPTER 22 INTERRUPT FUNCTIONS ×× ×× ××ICn) (2/3) ×× Figure 22-1 Interrupt Control Registers (×× Address After Reset CIC20 CIF20 CMK20 CISM20 CCSE20 CPR201 CPR200 0FFE8H 0FFE9H CIC21 CIF21 CMK21 CISM21 CCSE21 CPR211 CPR210 CIC30 CIF30 CMK30 CISM30 CCSE30 CPR301 CPR300 0FFEAH 0FFEBH PIC4...
Page 511 CHAPTER 22 INTERRUPT FUNCTIONS ×× ×× ×× ××ICn) (3/3) Figure 22-1 Interrupt Control Registers (×× Address After Reset 0FFEFH CSIIC1 CSIIF1 CSIMK1 CSIISM1 CSICSE1 CSIPR11 CSIPR10 STIC STIF STMK STISM STCSE STPR1 STPR0 0FFF0H 0FFF1H CSIIC CSIIF CSIMK CSIISM CSICSE CSIPR1 CSIPR0 SERIC2 SERIF2...
Page 512 CHAPTER 22 INTERRUPT FUNCTIONS 22.3.2 Interrupt Mask Registers (MK0/MK1L) The MK0 and MK1L are composed of interrupt mask flags. MK0 is a 16-bit register which can be manipulated as 8- bit units, MK0L and MK0H, as well as being manipulated as a 16-bit unit. MK1L is an 8-bit register that can be manipulated as an 8-bit unit.
Page 513 CHAPTER 22 INTERRUPT FUNCTIONS 22.3.3 In-Service Priority Register (ISPR) The ISPR shows the priority level of the maskable interrupt currently being serviced and the non-maskable interrupt being serviced. When a maskable interrupt request is acknowledged, the bit corresponding to the priority of that interrupt request is set (to 1), and remains set until the service program ends.
Page 514 CHAPTER 22 INTERRUPT FUNCTIONS 22.3.4 Interrupt Mode Control Register (IMC) The IMC contains the PRSL flag. The PRSL flag specifies enabling/disabling of nesting of maskable interrupts for which the lowest priority level (level 3) is specified. When the IMC is manipulated, the interrupt disabled state (DI state) should be set first to prevent malfunction. The IMC can be read or written to with an 8-bit manipulation instruction or bit manipulation instruction.
Page 515 If recovery from an operand error is simply performed by means of an RETB instruction, an endless loop will result. As an operand error interrupt is only generated in the event of an inadvertent program loop (with the NEC Electronics assembler, RA78K4, only the correct dedicated instruction is generated when MOV WDM, #byte is written), system initialization should be performed by the program.
Page 516 CHAPTER 22 INTERRUPT FUNCTIONS 22.3.6 Program Status Word (PSW) The PSW is a register that holds the current status regarding instruction execution results and interrupt requests. The IE flag that sets enabling/disabling of maskable interrupts is mapped in the low-order 8 bits of the PSW (PSWL). PSWL can be read or written to with an 8-bit manipulation instruction, and can also be manipulated with a bit manipulation instruction or dedicated instruction (EI/DI).
Page 517 CHAPTER 22 INTERRUPT FUNCTIONS 22.4.2 BRKCS Instruction Software Interrupt (Software Context Switching) Acknowledgment Operation The context switching function can be initiated by executing a BRKCS instruction. The register bank to be used after context switching is specified by the BRKCS instruction operand. When a BRKCS instruction is executed, the program branches to the start address of the interrupt service program (which must be in the base area) stored beforehand in the specified register bank, and the contents of the program status word (PSW) and program counter (PC) are saved in the register bank.
Page 518 CHAPTER 22 INTERRUPT FUNCTIONS Figure 22-8 Return from BRKCS Instruction Software Interrupt (RETCSB Instruction Operation) Register Bank n (n = 0 to 7) 19-16 15-0 1 Restoration RETCSB Instruction Operand 2 Restoration 3 Transfer 4 Restoration (To Original Register Bank) 22.5 OPERAND ERROR INTERRUPT ACKNOWLEDGMENT OPERATION An operand error interrupt is generated when the data obtained by inverting all the bits of the 3rd byte of the operand of an MOV STBC, #byte instruction or LOCATION instruction or an MOV WDM,#byte instruction does not match the 4th...
Page 519 CHAPTER 22 INTERRUPT FUNCTIONS 22.6 NON-MASKABLE INTERRUPT ACKNOWLEDGMENT OPERATION Non-maskable interrupts are acknowledged even in the interrupt disabled state. Non-maskable interrupts can be acknowledged at all times except during execution of the service program for an identical non-maskable interrupt or a non- maskable interrupt of higher priority.
Page 520 CHAPTER 22 INTERRUPT FUNCTIONS Figure 22-9 Non-Maskable Interrupt Request Acknowledgment Operations (1/2) (a) When a new NMI request is generated during NMI service program execution Main Routine (NMIS = 1) NMI Request NMI request held pending since NMIS = 1 NMI Request Pending NMI request is serviced (b) When a watchdog timer interrupt request is generated during NMI service program execution (when the...
Page 521 CHAPTER 22 INTERRUPT FUNCTIONS Figure 22-9 Non-Maskable Interrupt Request Acknowledgment Operations (2/2) (c) When a watchdog timer interrupt request is generated during NMI service program execution (when the NMI interrupt priority is higher (when PRC in the WDM = 0)) Main Routine Watchdog Watchdog timer interrupt is kept...
Page 522 CHAPTER 22 INTERRUPT FUNCTIONS Cautions 1. Macro service requests are acknowledged and serviced even during execution of a non-maskable interrupt service program. If you do not want macro service processing to be performed during a non-maskable interrupt service program, you should manipulate the interrupt mask register in the non-maskable interrupt service program to prevent macro service generation.
Page 523 CHAPTER 22 INTERRUPT FUNCTIONS 22.7 MASKABLE INTERRUPT ACKNOWLEDGMENT OPERATION A maskable interrupt can be acknowledged when the interrupt request flag is set (to 1) and the mask flag for that interrupt is cleared (to 0). When servicing is performed by macro service, the interrupt is acknowledged and serviced by macro service immediately.
Page 524 CHAPTER 22 INTERRUPT FUNCTIONS Figure 22-10 Interrupt Acknowledgment Processing Algorithm ××IF = 1 Interrupt Request? ××MK = 0 Interrupt Mask Released? ××ISM = 1 Macro Service? Highest default priority among IE = 1 macro service Interrupt Enabled State? requests? Higher priority Macro service than interrupt currently processing execution...
Page 525 CHAPTER 22 INTERRUPT FUNCTIONS 22.7.1 Vectored Interruption When a vectored interruption maskable interrupt request is acknowledged, the program status word (PSW) and program counter (PC) are saved in that order to the stack, the IE flag is cleared (to 0) (the interrupt disabled state is set), and the in-service priority register (ISPR) bit corresponding to the priority of the acknowledged interrupt is set (to 1).
Page 526 CHAPTER 22 INTERRUPT FUNCTIONS The RETCS instruction is used to return from an interrupt that uses the context switching function. The RETCS instruction must specify the start address of the interrupt service program to be executed when that interrupt is acknowledged next. This interrupt service program start address must be in the base area.
Page 527 CHAPTER 22 INTERRUPT FUNCTIONS 22.7.3 Maskable Interrupt Priority Levels The µ PD784038 performs multiple interrupt servicing in which an interrupt is acknowledged during servicing of another interrupt. Multiple interrupts can be controlled by priority levels. There are two kinds of priority control, control by default priority and programmable priority control in accordance with the setting of the priority specification flag.
Page 528 CHAPTER 22 INTERRUPT FUNCTIONS Figure 22-13 Examples of Servicing When Another Interrupt Request is Generated During Interrupt Service (1/3) Main routine a Servicing b Servicing Interrupt Request a Interrupt (Level 3) Request b Since interrupt request b has a higher (Level 2) priority than interrupt request a, and interrupts are enabled, interrupt...
Page 529 CHAPTER 22 INTERRUPT FUNCTIONS Figure 22-13 Examples of Servicing When Another Interrupt Request is Generated During Interrupt Service (2/3) Main routine i Servicing Interrupt Request i Macro Service j Macro Service (Level 1) Request j The macro service request is (Level 2) serviced irrespective of interrupt enabling/disabling and priority.
Page 530 CHAPTER 22 INTERRUPT FUNCTIONS Figure 22-13 Examples of Servicing When Another Interrupt Request is Generated During Interrupt Service (3/3) Main routine q Servicing r Servicing s Servicing Interrupt Interrupt Request q t Servicing Request r Interrupt Level 3) Interrupt (Level 2) Request s Request t Multiple acknowledgment of levels 3 to 0.
Page 531 CHAPTER 22 INTERRUPT FUNCTIONS Figure 22-14 Examples of Servicing of Simultaneously Generated Interrupts Main Routine Interrupt Request a (Level 2) Macro Service Request b Servicing • When requests are generated Macro Service Request b (Level 3) simultaneously, they are Macro Service Request c (Level 1) Macro Service Request c Servicing acknowledged in order starting with macro service.
Page 532 CHAPTER 22 INTERRUPT FUNCTIONS Figure 22-15 Differences in Level 3 Interrupt Acknowledgment According to IMC Register Setting Main Routine The PRSL bit of the IMC is set to 1, and nesting between level 3 interrupts is IMC ← 80H disabled. a Servicing Interrupt Request a (Level 3)
Page 533 CHAPTER 22 INTERRUPT FUNCTIONS 22.8 MACRO SERVICE FUNCTION 22.8.1 Outline of Macro Service Function Macro service is one method of servicing interrupts. With a normal interrupt, the program counter (PC) and program status word (PSW) are saved, and the start address of the interrupt service program is loaded into the PC, but with macro service, different processing (mainly data transfers) is performed instead of this processing.
Page 534 CHAPTER 22 INTERRUPT FUNCTIONS Table 22-6 Interrupts for Which Macro Service Can be Used Default Macro Service Control Interrupt Request Generation Source Generating Unit Priority Word Address INTP0 (pin input edge detection) Edge detection 0FE06H INTP1 (pin input edge detection) 0FE08H INTP2 (pin input edge detection) 0FE0AH...
Page 535 CHAPTER 22 INTERRUPT FUNCTIONS There are four kinds of macro service, as shown below. (1) Type A One byte or one word of data is transferred between a special function register (SFR) and memory each time an interrupt request is generated, and a vectored interrupt request is generated when the specified number of transfers have been performed.
Page 536 CHAPTER 22 INTERRUPT FUNCTIONS 22.8.3 Basic Macro Service Operation Interrupt requests for which the macro service processing generated by the algorithm shown in Figure 22-10 can be specified are basically serviced in the sequence shown in Figure 22-17. Interrupt requests for which macro service processing can be specified are not affected by the status of the IE flag, but are disabled by setting (to 1) an interrupt mask flag in the interrupt mask register (MK0).
Page 537 CHAPTER 22 INTERRUPT FUNCTIONS 22.8.4 Operation at End of Macro Service In macro service, processing is performed the number of times specified during execution of another program. Macro service ends when the processing has been performed the specified number of times (when the macro service counter (MSC) reaches 0).
Page 538 CHAPTER 22 INTERRUPT FUNCTIONS Figure 22-18 Operation at End of Macro Service When VCIE = 0 Main Routine Macro Service Request Macro Service Processing Last Macro Service Request Macro Service Processing At the end of macro service (MSC = 0), an interrupt Servicing of Interrupt Request request is generated and due to End of Macro Service...
Page 539 CHAPTER 22 INTERRUPT FUNCTIONS (2) When VCIE bit is 1 In this mode, an interrupt is not generated after macro service ends. Figure 22-19 shows an example of macro service and interrupt acknowledgment operations when the VCIE bit is 1. This mode is used when the final operation is to be started by the last macro service processing performed, for instance.
Page 540 CHAPTER 22 INTERRUPT FUNCTIONS 22.8.5 Macro Service Control Registers (1) Macro service control word The µ PD784038’s macro service function is controlled by the macro service control mode register and macro service channel pointer. The macro service processing mode is set by means of the macro service mode register, and the macro service channel address is indicated by the macro service channel pointer.
Page 541 CHAPTER 22 INTERRUPT FUNCTIONS (2) Macro service mode register The macro service mode register is an 8-bit register that specifies the macro service operation. This register is written in internal RAM as part of the macro service control word (see Figure 22-20). The format of the macro service mode register is shown in Figure 22-21.
Page 542 CHAPTER 22 INTERRUPT FUNCTIONS Figure 22-21 Macro Service Mode Register Format (2/2) VCIE MOD2 MOD1 MOD0 CHT3 CHT2 CHT1 CHT0 CHT0 CHT1 CHT2 CHT3 MOD2 MOD1 MOD0 Type C Decrements MPD Increments MPD Retains MPT Decrements MPT Retains MPT Increments MPT Data size for timer No automatic No ring control...
Page 543 CHAPTER 22 INTERRUPT FUNCTIONS 22.8.6 Macro Service Type A (1) Operation Data transfers are performed between buffer memory in the macro service channel and an SFR specified in the macro service channel. With type A, the data transfer direction can be selected as memory-to-SFR or SFR-to-memory. Data transfers are performed the number of times set beforehand in the macro service counter.
Page 544 CHAPTER 22 INTERRUPT FUNCTIONS Figure 22-22 Macro Service Data Transfer Processing Flow (Type A) Macro Service Request Acknowledgment Read contents of macro service mode register Other Determine Channel Type To Other Macro Service Processing TYPE A Read channel pointer contents (m) Read MSC contents (n) Note 1-byte transfer: m –...
Page 545 CHAPTER 22 INTERRUPT FUNCTIONS (2) Macro service channel configuration The channel pointer and 8-bit macro service counter (MSC) indicate the buffer address in internal RAM (FE00H to FEFFH when the LOCATION 0H instruction is executed, or FFE00H to FFEFFH when the LOCATION 0FH instruction is executed) which is the transfer source or transfer destination (see Figure 22-23).
Page 546 CHAPTER 22 INTERRUPT FUNCTIONS Figure 22-23 Type A Macro Service Channel (a) 1-byte transfers  High Addresses Macro Service Counter (MSC)   SFR Pointer (SFRP)   Macro Service Buffer 1  MCS = 1  Macro Service  Macro Service Buffer 2 MCS = 2 Channel...
Page 547 CHAPTER 22 INTERRUPT FUNCTIONS (3) Example of use of type A An example is shown below in which data received via the asynchronous serial interface is transferred to a buffer area in on-chip RAM. Figure 22-24 Asynchronous Serial Reception (Internal RAM) –1 0FE7FH MSC 0EH...
Page 548 CHAPTER 22 INTERRUPT FUNCTIONS 22.8.7 Macro Service Type B (1) Operation Data transfers are performed between a data area in memory and an SFR specified by the macro service channel. With type B, the data transfer direction can be selected as memory-to-SFR or SFR-to-memory. Data transfers are performed the number of times set beforehand in the macro service counter.
Page 549 CHAPTER 22 INTERRUPT FUNCTIONS Figure 22-25 Macro Service Data Transfer Processing Flow (Type B) Macro Service Request Acknowledgment Read contents of macro service mode register Other Determine Channel Type To Other Macro Service Processing TYPE B Read channel pointer contents (m) SFR →...
Page 550 CHAPTER 22 INTERRUPT FUNCTIONS (2) Macro service channel configuration The macro service pointer (MP) indicates the data buffer area in the 1-Mbyte memory space that is the transfer destination or transfer source. The low-order 8 bits of the SFR that is the transfer destination or transfer source is written to the SFR pointer (SFRP). The macro service counter (MSC) is a 16-bit counter that specifies the number of data transfers.
Page 551 CHAPTER 22 INTERRUPT FUNCTIONS (3) Example of use of type B An example is shown below in which parallel data is input from port 3 in synchronization with an external signal. The INTP4 external interrupt pin is used for synchronization with the external signal. Figure 22-27 Parallel Data Input Synchronized with External Interrupts Macro Service Control Word, Macro Service Channel...
Page 552 CHAPTER 22 INTERRUPT FUNCTIONS Figure 22-28 Parallel Data Input Timing Port 3 INTP4 Data Fetch (Macro Service) 22.8.8 Macro Service Type C (1) Operation In type C macro service, data in the memory specified by the macro service channel is transferred to two SFRs, for timer use and data use, specified by the macro service channel in response to a single interrupt request (the SFRs can be freely selected).
Page 553 CHAPTER 22 INTERRUPT FUNCTIONS Figure 22-29 Macro Service Data Transfer Processing Flow (Type C) (1/2) Macro Service Request Acknowledgment Read contents of macro service mode register Other Determine Channel Type To Other Macro Service Processing TYPE C Read channel pointer contents (m) Read memory addressed by MPT Automatic Addition Specified? Transfer data to compare register...
Page 554 CHAPTER 22 INTERRUPT FUNCTIONS Figure 22-29 Macro Service Data Transfer Processing Flow (Type C) (2/2) Ring Control? Decrement ring counter Ring Counter = 0? Increment MPD? Subtract modulo register Add modulo register contents contents from data macro to data macro service pointer service pointer (MPD), and (MPD), and return pointer to return pointer to start address...
Page 555 CHAPTER 22 INTERRUPT FUNCTIONS Macro service channel configuration There are two kinds of type C macro service channel, as shown in Figure 22-30. The timer macro service pointer (MPT) mainly indicates the data buffer area in the 1-Mbyte memory space to be transferred or added to the timer/counter compare register.
Page 556 CHAPTER 22 INTERRUPT FUNCTIONS Figure 22-30 Type C Macro Service Channel (2/2) (b) With ring control High Addresses TSFR (Bits 8 to 15) Macro Service Counter (MSC) (Bits 0 to 7) DSFR Timer SFR Pointer (TSFRP) Note (Bits 16 to 23) Timer Buffer Area Timer Macro Service (Bits 8 to 15)
Page 557 CHAPTER 22 INTERRUPT FUNCTIONS Figure 22-31 Stepping Motor Open Loop Control by Real-Time Output Port Macro Service Control Word, Macro Service Channel 1M Memory Space (Internal RAM) –1 123411H 0FE5EH TSFRP Low-Order 8 Bits Output Timing of CR10 Address Data Area 123409H 123408H Low-Order 8 Bits...
Page 558 CHAPTER 22 INTERRUPT FUNCTIONS Figure 22-32 Data Transfer Control Timing Count Value INTC10 Timer Interrupt Compare Register (CR10) Buffer Register User’s Manual U11316EJ4V1UD...
Page 559 CHAPTER 22 INTERRUPT FUNCTIONS (b) Examples of use of automatic addition control and ring control Automatic addition control The output timing data (∆t) specified by the macro service pointer (MPT) is added to the contents of the compare register, and the result is written back to the compare register. Use of this automatic addition control eliminates the need to calculate the compare register setting value in the program each time.
Page 560 CHAPTER 22 INTERRUPT FUNCTIONS Figure 22-33 Single-Phase Excitation of 4-Phase Stepping Motor Phase A Phase B Phase C Phase D 1 Cycle (4 Patterns) Figure 22-34 1-2-Phase Excitation of 4-Phase Stepping Motor Phase A Phase B Phase C Phase D 1 Cycle (8 Patterns) User’s Manual U11316EJ4V1UD...
Page 561 CHAPTER 22 INTERRUPT FUNCTIONS Figure 22-35 Automatic Addition Control + Ring Control Block Diagram 1 (When Output Timing Varies with 1-2-Phase Excitation) Macro Service Control Word, Macro Service Channel (Internal RAM) 1M Memory Space t512 1237FEH 0FE5AH TSFRP Low-Order 8 Bits of CR10 Address Output Timing: 123400H 123007H DSFRP...
Page 562 CHAPTER 22 INTERRUPT FUNCTIONS Figure 22-36 Automatic Addition Control + Ring Control Timing Diagram 1 (When Output Timing Varies with 1-2-Phase Excitation) FFFFH ∆t7 ∆t6 ∆t5 ∆t4 TM1W ∆t3 Count Value ∆t2 ∆t1 ∆t9 ∆t8 Count Start INTC10 Compare Register T0 + ∆t1 T1 + ∆t2 T2 + ∆t3...
Page 563 CHAPTER 22 INTERRUPT FUNCTIONS Figure 22-37 Automatic Addition Control + Ring Control Block Diagram 2 (1-2-Phase Excitation Constant-Velocity Operation) Macro Service Control Word, Macro Service Channel (Internal RAM) 1M Memory Space Output Timing: 1233FFH 0FE7AH TSFRP Low-Order 8 Bits of CR10 Address 123007H Output Data (8 Items) DSFRP...
Page 564 CHAPTER 22 INTERRUPT FUNCTIONS Figure 22-38 Automatic Addition Control + Ring Control Timing Diagram 2 (1-2-Phase Excitation Constant-Velocity Operation) FFFFH Count Value ∆t Count Start INTC10 Compare Register T0 + ∆t T1 + ∆t T2 + ∆t T3 + ∆t T4 + ∆t T5 + ∆t T6 + ∆t...
Page 565 CHAPTER 22 INTERRUPT FUNCTIONS 22.8.9 Counter Mode (1) Operation MSC is decremented the number of times set in advance to the macro service counter (MSC). Because the number of times an interrupt occurs can be counted, this function can be used as an event counter where the interrupt generation cycle is long.
Page 566 CHAPTER 22 INTERRUPT FUNCTIONS (2) Configuration of macro service channel The macro service channel consists of only a 16-bit macro service counter. The low-order 8 bits of the address of the MSC are written to the channel pointer. Figure 22-40 Counter Mode ...
Page 567 CHAPTER 22 INTERRUPT FUNCTIONS 22.9 WHEN INTERRUPT REQUESTS AND MACRO SERVICE ARE TEMPORARILY HELD PENDING When the following instructions are executed, interrupt acknowledgment and macro service processing is deferred for 8 system clock cycles. However, software interrupts are not deferred. BRKCS RETCS RETCSB !addr16...
Page 568 CHAPTER 22 INTERRUPT FUNCTIONS Cautions 1. When an interrupt related register is polled using a BF instruction, etc., the branch destination of that BR instruction, etc., should not be that instruction. If a program is written in which a branch is made to that instruction itself, all interrupts and macro service requests will be held pending until a condition whereby a branch is not made by that instruction arises.
Page 569 CHAPTER 22 INTERRUPT FUNCTIONS 22.10 INSTRUCTIONS WHOSE EXECUTION IS TEMPORARILY SUSPENDED BY AN INTERRUPT OR MACRO SERVICE Execution of the following instructions is temporarily suspended by an acknowledgeable interrupt request or macro service request, and the interrupt or macro service request is acknowledged. The suspended instruction is resumed after completion of the interrupt service program or macro service processing.
Page 570 CHAPTER 22 INTERRUPT FUNCTIONS 22.11.1 Interrupt Acknowledge Processing Time The time shown in Table 22-7 is required to acknowledge an interrupt request. After the time shown in this table has elapsed, execution of the interrupt processing program is started. Table 22-7 Interrupt Acknowledge Processing Time (Unit: Clock = 1/f Vector Table IROM...
Page 571 CHAPTER 22 INTERRUPT FUNCTIONS 22.11.2 Processing Time of Macro Service Macro service processing time differs depending on the type of the macro service, as shown in Table 22-8. Table 22-8 Macro Service Processing Time (Units: Clock = 1/f Data Area Processing Type of Macro Service IRAM Others...
Page 572 CHAPTER 22 INTERRUPT FUNCTIONS 22.12 RESTORING INTERRUPT FUNCTION TO INITIAL STATE If an inadvertent program loop or system error is detected by means of an operand error interrupt, the watchdog timer, NMI pin input, etc., the entire system must be restored to its initial state. In the µ PD784038, interrupt acknowledgment related priority control is performed by hardware.
Page 573 CHAPTER 22 INTERRUPT FUNCTIONS 22.13 CAUTIONS (1) The in-service priority register (ISPR) is read-only. Writing to this register may result in malfunction. (2) The watchdog timer mode register (WDM) can only be written to with a dedicated instruction (MOV WDM/#byte). (3) The RETI instruction must not be used to return from a software interrupt caused by a BRK instruction.
Page 574 CHAPTER 22 INTERRUPT FUNCTIONS (10) When an interrupt related register is polled using a BF instruction, etc., the branch destination of that BR instruction, etc., should not be that instruction. If a program is written in which a branch is made to that instruction itself, all interrupts and macro service requests will be held pending until a condition whereby a branch is not made by that instruction arises.
Page 575 CHAPTER 23 LOCAL BUS INTERFACE FUNCTION The local bus interface function is provided for the connection of external memory (ROM and RAM) and I/Os. External memory (ROM and RAM) and I/Os are accessed using the RD, WR, and ASTB pin signals, with pins AD0 to AD7 used as the multiplexed address/data bus and pins A8 to A19 as the address bus.
Page 576 CHAPTER 23 LOCAL BUS INTERFACE FUNCTION Figure 23-1 Memory Extension Mode Register (MM) Format Address After Reset IFCH 0FFC4H ASTB P64/ P65/ /CLK MM2 MM1 MM0 Mode Port 4 Port 5 P60 to P63 Single-chip Port Port Port Port Port CLKOUT Note mode...
Page 577 CHAPTER 23 LOCAL BUS INTERFACE FUNCTION 23.1.2 Memory Map with External Memory Extension The memory map when memory extension is used is shown in Figures 23-2 to 23-5. External devices at the same addresses as the internal ROM area, internal RAM area and SFR area (excluding the external SFR area (0FFD0H to 0FFDFH)) cannot be accessed.
Page 578 CHAPTER 23 LOCAL BUS INTERFACE FUNCTION Figure 23-2 µ µ µ µ µ PD784035 Memory Map (2/2) (b) When LOCATION 0FH instruction is executed FFFFFH FFFE0H Note 2 Note 2 External Memory FFFCFH Internal RAM Internal RAM Internal RAM FF700H Note 1 External Memory External Memory...
Page 579 CHAPTER 23 LOCAL BUS INTERFACE FUNCTION Figure 23-3 µ µ µ µ µ PD784036 Memory Map (1/2) (a) When LOCATION 0H instruction is executed FFFFFH Note 1 External Memory External Memory 0FFFFH 0FFE0H Note 2 External Memory Note 2 0FFCFH Internal RAM Internal RAM Internal RAM...
Page 580 CHAPTER 23 LOCAL BUS INTERFACE FUNCTION Figure 23-3 µ µ µ µ µ PD784036 Memory Map (2/2) (b) When LOCATION 0FH instruction is executed FFFFFH FFFE0H Note 2 Note 2 External Memory FFFCFH Internal RAM Internal RAM Internal RAM FF700H External Memory Note 1 External Memory...
Page 581 CHAPTER 23 LOCAL BUS INTERFACE FUNCTION Figure 23-4 µ µ µ µ µ PD784037 Memory Map (1/2) (a) When LOCATION 0H instruction is executed FFFFFH External Memory Note 1 External Memory 17FFFH Internal ROM Internal ROM Internal ROM 10000H 0FFFFH 0FFE0H Note 2 Note 2...
Page 582 CHAPTER 23 LOCAL BUS INTERFACE FUNCTION Figure 23-4 µ µ µ µ µ PD784037 Memory Map (2/2) (b) When LOCATION 0FH instruction is executed FFFFFH FFFE0H Note 2 External Memory Note 2 FFFCFH Internal RAM Internal RAM Internal RAM FF100H Note 1 External Memory External Memory...
Page 583 CHAPTER 23 LOCAL BUS INTERFACE FUNCTION Figure 23-5 µ µ µ µ µ PD784038 Memory Map (1/2) (a) When LOCATION 0H instruction is executed FFFFFH External Memory Note 1 External Memory 1FFFFH Internal ROM Internal ROM Internal ROM 10000H 0FFFFH 0FFE0H Note 2 External Memory...
Page 584 CHAPTER 23 LOCAL BUS INTERFACE FUNCTION Figure 23-5 µ µ µ µ µ PD784038 Memory Map (2/2) (b) When LOCATION 0FH instruction is executed FFFFFH FFFE0H Note 2 External Memory Note 2 FFFCFH Internal RAM Internal RAM Internal RAM EE100H Note 1 External Memory External Memory...
Page 585 CHAPTER 23 LOCAL BUS INTERFACE FUNCTION Figure 23-6 µ µ µ µ µ PD784031 Memory Map (1/2) (a) When LOCATION 0H instruction is executed Logical Address Output Address Output Address Output Address FFFFFH 0FFFFH 3FFFFH FFFFFH 00000H 0FFFFH 00000H 0FFFFH 00000H 00000H C0000H...
Page 586 CHAPTER 23 LOCAL BUS INTERFACE FUNCTION Figure 23-6 µ µ µ µ µ PD784031 Memory Map (2/2) (b) When LOCATION 0FH instruction is executed Logical Address Output Address Output Address Output Address FFFFFH FFFDFH FFFDFH 0FFDFH 3FFDFH Note Note Note FFFD0H 0FFD0H 3FFD0H...
Page 587 CHAPTER 23 LOCAL BUS INTERFACE FUNCTION 23.1.3 Basic Operation of Local Bus Interface The local bus interface accesses external memory using ASTB, RD, WR, an address/data bus (AD0 to AD7) and address bus (A8 to A19). When the local bus interface is used, P64, P65 and port 4 automatically operate as RD, WR, and AD0 to AD7.
Page 588 CHAPTER 23 LOCAL BUS INTERFACE FUNCTION 23.2 WAIT FUNCTION When a low-speed memory or I/O is connected externally to the µ PD784038, waits can be inserted in the external memory access cycle. There are two kinds of wait cycle, an address wait for securing the address decoding time, and an access wait for securing the access time.
Page 589 CHAPTER 23 LOCAL BUS INTERFACE FUNCTION (2) Programmable wait control registers (PWC1/PWC2) The PWC1 and PWC2 specify the number of waits. PWC1 is an 8-bit register that divides the space from 0 to FFFFH into four, and specifies wait control for each of these four spaces.
Page 590 CHAPTER 23 LOCAL BUS INTERFACE FUNCTION Figure 23-10 Programmable Wait Control Register (PWC1/PWC2) Format (a) Programmable wait control register 1 (PWC1) Address After Reset 0FFC7H PWC1 PW31 PW30 PW21 PW20 PW11 PW10 PW01 PW00 (n = 0 to 3) Addresses Subject to Wait 000000H to 00C000H to 008000H to...
Page 591 CHAPTER 23 LOCAL BUS INTERFACE FUNCTION 23.2.2 Address Waits Address waits are used to secure the address decoding time. If the AW bit of the memory extension mode register (MM) Note is set (to 1), waits are inserted in every memory access .
Page 592 CHAPTER 23 LOCAL BUS INTERFACE FUNCTION Figure 23-11 Address Wait Function Read/Write Timing (2/3) (b) Read timing with address wait insertion Note High Address A8 to A19 Hi-Z Hi-Z Hi-Z Low Address Input Data AD0 to AD7 ASTB : Internal system clock frequency. This signal is present inside the µ PD784038 only. Note f User’s Manual U11316EJ4V1UD...
Page 593 CHAPTER 23 LOCAL BUS INTERFACE FUNCTION Figure 23-11 Address Wait Function Read/Write Timing (3/3) (c) Write timing with no address wait insertion Note A8 to A19 High Address Hi-Z Hi-Z Hi-Z AD0 to AD7 Low Address Output Data ASTB (d) Write timing with address wait insertion Note A8 to A19 High Address...
Page 594 CHAPTER 23 LOCAL BUS INTERFACE FUNCTION 23.2.3 Access Waits Access waits are inserted in the RD or WR signal low-level period, and extend the low-level period by 1/f (62.5 ns: = 16 MHz) per cycle. There are two wait insertion methods, using either the programmable wait function that automatically inserts the preset number of cycles, or the external wait function controlled by a wait signal from outside.
Page 595 CHAPTER 23 LOCAL BUS INTERFACE FUNCTION Figure 23-12 Wait Control Spaces FFFFFH Controlled by Bits 512 Kbytes PW70 & PW71 80000H 7FFFFH Controlled by PWC2 Controlled by Bits 256 Kbytes PW60 & PW61 40000H 3FFFFH Controlled by Bits 128 Kbytes PW50 &...
Page 596 CHAPTER 23 LOCAL BUS INTERFACE FUNCTION Figure 23-13 Access Wait Function Read Timing (1/2) (a) 0 wait cycles set Note A8 to A15 High Address (Output) Hi-Z Hi-Z Hi-Z AD0 to AD7 Data (Input) Address ASTB (Output) RD (Output) (b) 1 wait cycle set Note A8 to A15 High Address...
Page 597 CHAPTER 23 LOCAL BUS INTERFACE FUNCTION Figure 23-13 Access Wait Function Read Timing (2/2) (c) 2 wait cycles set Note A8 to A15 High Address (Output) Hi-Z Hi-Z AD0 to AD7 Data (Input) Address ASTB (Output) RD (Output) : Internal system clock frequency. This signal is only present inside the µ PD784038. Note f User’s Manual U11316EJ4V1UD...
Page 598 CHAPTER 23 LOCAL BUS INTERFACE FUNCTION Figure 23-14 Access Wait Function Write Timing (1/2) (a) 0 wait cycles set Note A8 to A15 High Address (Output) Hi-Z AD0 to AD7 Hi-Z Hi-Z Data (Output) Address ASTB (Output) WR (Output) (b) 1 wait cycle set Note A8 to A15 High Address...
Page 599 CHAPTER 23 LOCAL BUS INTERFACE FUNCTION Figure 23-14 Access Wait Function Write Timing (2/2) (c) 2 wait cycles set Note A8 to A15 High Address (Output) Hi-Z Hi-Z Hi-Z AD0 to AD7 Data (Output) Address ASTB (Output) WR (Output) : Internal system clock frequency. This signal is only present inside the µ PD784038. Note f User’s Manual U11316EJ4V1UD...
Page 600 CHAPTER 23 LOCAL BUS INTERFACE FUNCTION Figure 23-15 Timing with External Wait Signal (a) Read timing Note A8 to A15 High Address (Output) Hi-Z Hi-Z AD0 to AD7 Data (Input) Address ASTB (Output) RD (Output) WAIT (Input) (b) Write timing Note A8 to A15 High Address...
Page 601 CHAPTER 23 LOCAL BUS INTERFACE FUNCTION 23.3 PSEUDO-STATIC RAM REFRESH FUNCTION The µ PD784038 incorporates a pseudo-static RAM refresh function for direct connection of pseudo-static RAM. The pseudo-static RAM refresh function outputs refresh pulses at any desired intervals. The refresh pulse output interval is specified by the refresh mode register (RFM) setting.
Page 602 CHAPTER 23 LOCAL BUS INTERFACE FUNCTION 23.3.1 Control Registers (1) Refresh mode register (RFM) The RFM is an 8-bit register that controls the pseudo-static RAM refresh cycle and switching to self-refresh operations. The RFM register can be read or written to with an 8-bit manipulation instruction or bit manipulation instruction. RFM format is shown in Figure 23-16.
Page 603 CHAPTER 23 LOCAL BUS INTERFACE FUNCTION (2) Refresh area specification register (RFA) The RFA is an 8-bit register that specifies the areas on which refresh operations can be performed at the same time as memory access operations. The RFA register can be read or written to with an 8-bit manipulation instruction and bit manipulation instruction. RFA format is shown in Figure 23-17.
Page 604 CHAPTER 23 LOCAL BUS INTERFACE FUNCTION (a) Internal memory accesses In the case of internal memory accesses in which the external pseudo-static RAM is not accessed, also, refresh bus cycles are output at the intervals specified by the refresh mode (RFM) register so that the data stored in the pseudo-static RAM is retained.
Page 605 CHAPTER 23 LOCAL BUS INTERFACE FUNCTION (b) External memory accesses When an access is made to an address corresponding to a cleared (to 0) bit in the refresh area specification register (RFA), a refresh pulse is always output from the REFRQ pin at the same time as the RD signal or WR signal, irrespective of the cycle specified by the refresh mode register (RFM).
Page 606 CHAPTER 23 LOCAL BUS INTERFACE FUNCTION (2) Self-refresh operation This mode is used to retain the contents of pseudo-static RAM in standby mode. (a) Self-refresh operating mode setting When bit 4 (RFEN) of the refresh mode (RFM) register is set to “1”, and bit 7 (RFLV) to “0”, a low level is output from the REFRQ pin, and the self-refresh operating mode is specified for the pseudo-static RAM.
Page 607 CHAPTER 23 LOCAL BUS INTERFACE FUNCTION 23.4 BUS HOLD FUNCTION The bus hold function is provided for the connection of a device that functions as the bus master, such as a DMA controller. In response to a request from the bus master device, all local bus interface pins are set to high impedance (except HLDAK), and local bus interface mastership is passed to that device.
Page 608 CHAPTER 23 LOCAL BUS INTERFACE FUNCTION 23.4.2 Operation When the HLDE bit of the hold mode register (HLDM) is set (to 1), the bus hold function is enabled. When the bus hold function is enabled, pins P66 and P67 operate as the HLDRQ and HLDAK pins respectively. The HLDRQ pin becomes high-impedance, and the HLDAK pin outputs a low-level signal.
Page 609 CHAPTER 23 LOCAL BUS INTERFACE FUNCTION Figure 23-22 Hold Mode Timing Hi-Z ASTB Hi-Z A8 to A19 Hi-Z AD0 to AD7 Hi-Z Hi-Z Hi-Z HLDRQ HLDAK 23.5 CAUTIONS (1) When the bus hold function is used, the external wait function cannot be used (access wait control by means of the WAIT pin), and 0, 1 or 2 waits must be selected for the entire space.
Page 610 CHAPTER 24 STANDBY FUNCTION 24.1 CONFIGURATION AND FUNCTION The µ PD784038 has a standby function that enables the system power consumption to be reduced. The standby function includes three modes as follows: • HALT mode..In this mode the CPU operating clock is stopped. Intermittent operation in combination with the normal operating mode enables the total system power consumption to be reduced.
Page 611 To Peripheral Circuit Oscillation Stabilization Timer (20) RAM PROTECT OSTS0 To Peripheral Circuit OSTS1 Selector OSTS2 fxx/2 EXTC fxx/4 System Frequency CPU CLK Clock Selector fxx/8 Divider Oscillator fxx/16 HLT F/F HALT Bit Setting STOP Bit Setting EXTC Macro Service Request IDLE F/F STP F/F2...
Page 612 If recovery from an operand error is simply performed by means of an RETB instruction, an endless loop will result. As an operand error interrupt is only generated in the event of an inadvertent program loop (with the NEC Electronics assembler, RA78K4, only the correct dedicated instruction is generated when MOV STBC, #byte is written), system initialization should be performed by the program.
Page 613 CHAPTER 24 STANDBY FUNCTION Figure 24-3 Standby Control Register (STBC) Format Address After Reset × STBC 0FFC0H Operating Mode Normal operating mode HALT mode STOP mode IDLE mode = 32 MHz) Internal System Clock Selection /2 (16 MHz) /4 (8 MHz) /8 (4 MHz) /16 (2 MHz) Cautions 1.
Page 614 CHAPTER 24 STANDBY FUNCTION 24.2.2 Oscillation Stabilization Time Specification Register (OSTS) The OSTS specifies the oscillator operation and the oscillation stabilization time when STOP mode is released. The EXTC bit of the OSTS specifies whether crystal/ceramic oscillation or an external clock is used. STOP mode can be set when external clock input is used only when the EXTC bit is set (to 1).
Page 615 CHAPTER 24 STANDBY FUNCTION 24.3 HALT MODE 24.3.1 HALT Mode Setting and Operating States The HALT mode is selected by setting (to 1) the HLT bit of the standby control (STBC) register. The only writes that can be performed on the STBC are 8-bit data writes by means of a dedicated instruction. HALT mode setting is therefore performed by means of the “MOV STBC/#byte”...
Page 616 CHAPTER 24 STANDBY FUNCTION Table 24-2 HALT Mode Release and Operations after Release Note 1 Note 2 Release Source State on Release Operation after Release × × RESET input — Normal reset operation × × Non-maskable • Non-maskable interrupt service program Interrupt request acknowledgment interrupt request not being executed...
Page 617 CHAPTER 24 STANDBY FUNCTION Figure 24-5 Operation after HALT Mode Release (1/4) (1) When interrupt generates after HALT mode has been set Main Routine MOV STBC, #byte HALT Mode Interrupt Request • HALT Mode Release • Interrupt Processing (2) Reset after HALT mode has been set Main Routine MOV STBC, #byte HALT Mode...
Page 618 CHAPTER 24 STANDBY FUNCTION Figure 24-5 Operation after HALT Mode Release (2/4) (3) When HALT mode is set while interrupt routine with priority higher than or same as that of interrupt of release source Main Routine MOV STBC, #byte HALT Mode •...
Page 619 CHAPTER 24 STANDBY FUNCTION Figure 24-5 Operation after HALT Mode Release (3/4) (5) When macro service request is generated in HALT mode (a) When end condition of macro service is satisfied and interrupt request is generated immediately (VCIE = 0) Main Routine MOV STBC, #byte HALT Mode...
Page 620 CHAPTER 24 STANDBY FUNCTION Figure 24-5 Operation after HALT Mode Release (4/4) (6) When interrupt generates during execution of instruction that temporarily keeps interrupt pending, and if HALT mode is set while that interrupt is kept pending Main Routine Interrupt is kept pending for Interrupt Request duration of 8 clocks MOV STBC, #byte...
Page 621 CHAPTER 24 STANDBY FUNCTION (1) Release by non-maskable interrupt When a non-maskable interrupt is generate, the µ PD784038 is released from HALT mode irrespective of whether the interrupt acknowledgment enabled state (EI) or disabled state (DI) is in effect. When the µ PD784038 is released from HALT mode, if the non-maskable interrupt that released HALT mode can be acknowledged, acknowledgment of that non-maskable interrupt is performed and a branch is made to the service program.
Page 622 CHAPTER 24 STANDBY FUNCTION Table 24-3 HALT Mode Release by Maskable Interrupt Request Note 1 Note 2 Release Source State on Release Operation after Release Maskable • Interrupt service program not being Interrupt request acknowledgment interrupt request executed (excluding macro •...
Page 623 CHAPTER 24 STANDBY FUNCTION 24.4 STOP MODE 24.4.1 STOP Mode Setting and Operating States The STOP mode is selected by setting (to 1) the STP bit of the standby control register (STBC) register. The only writes that can be performed on the STBC register are 8-bit data writes by means of a dedicated instruction. STOP mode setting is therefore performed by means of the “MOV STBC/#byte”...
Page 624 CHAPTER 24 STANDBY FUNCTION 24.4.2 STOP Mode Release STOP mode is released by NMI input, INTP4 input, and RESET input. Release sources and an outline of operations after release are shown in Table 24-5. Figure 24-6 shows operations after STOP mode release. Table 24-5 STOP Mode Release and Operations after Release Note 1 Note 2...
Page 625 CHAPTER 24 STANDBY FUNCTION Figure 24-6 Operation after STOP Mode Release (1/2) (1) When interrupt generates after STOP mode has been set Main Routine MOV STBC, #byte STOP Mode Interrupt Request • STOP Mode Release • Interrupt Processing (2) Reset after STOP mode has been set Main Routine MOV STBC, #byte STOP Mode...
Page 626 CHAPTER 24 STANDBY FUNCTION Figure 24-6 Operation after STOP Mode Release (2/2) (3) When STOP mode is set while interrupt routine with priority higher than or same as that of interrupt of release source Main Routine MOV STBC, #byte STOP Mode •...
Page 627 CHAPTER 24 STANDBY FUNCTION (1) STOP mode release by NMI input The oscillator resumes oscillation when the valid edge specified by external interrupt mode register 0 (INTM0) is input to the NMI input. STOP mode is released after the oscillation stabilization time specified by the oscillation stabilization time specification register (OSTS) elapses.
Page 628 CHAPTER 24 STANDBY FUNCTION (2) STOP mode release by INTP4 or INTP5 input When masking of interrupts by INTP4 and INTP5 input is released and macro service is disabled, the oscillator resumes oscillation when the valid edge specified by external interrupt mode register 1 (INTM1) is input to the INTP4 or INTP5 input.
Page 629 CHAPTER 24 STANDBY FUNCTION 24.5 IDLE MODE 24.5.1 IDLE Mode Setting and Operating States The IDLE mode is selected by setting (to 1) both the STP bit and the HLT bit of the standby control (STBC) register. The only writes that can be performed on the STBC are 8-bit data writes by means of a dedicated instruction. IDLE mode setting is therefore performed by means of the ”MOV STBC/#byte”...
Page 630 CHAPTER 24 STANDBY FUNCTION 24.5.2 IDLE Mode Release IDLE mode is released by NMI input, INTP4 input, INTP5 input, or RESET input. Release source and an outline of operations after release are shown in Table 24-7. Figure 24-9 shows operations after IDLE mode release.
Page 631 CHAPTER 24 STANDBY FUNCTION Figure 24-9 Operation after IDLE Mode Release (1/2) (1) When interrupt generates after IDLE mode has been set Main Routine MOV STBC, #byte IDLE Mode Interrupt Request • IDLE Mode Release • Interrupt Processing (2) Reset after IDLE mode has been set Main Routine MOV STBC, #byte IDLE Mode...
Page 632 CHAPTER 24 STANDBY FUNCTION Figure 24-9 Operation after IDLE Mode Release (2/2) (3) When IDLE mode is set while interrupt routine with priority higher than or same as that of interrupt of release source Main Routine MOV STBC, #byte IDLE Mode •...
Page 633 CHAPTER 24 STANDBY FUNCTION (1) IDLE mode release by NMI input IDLE mode is released when the valid edge specified by external interrupt mode register 0 (INTM0) is input to the NMI input. When the µ PD784038 is released from IDLE mode, if a non-maskable interrupt by NMI pin input can be acknowledged, a branch is made to the NMI interrupt service program.
Page 634 CHAPTER 24 STANDBY FUNCTION 24.6 CHECK ITEMS WHEN STOP MODE/IDLE MODE IS USED Check items required to reduce the power consumption when STOP mode/IDLE mode is used are shown below. (1) Is the output level of each output pin appropriate? The appropriate output level for each pin varies according to the next-stage circuit.
Page 635 CHAPTER 24 STANDBY FUNCTION (4) Is processing of the address bus, address/data bus, etc., appropriate? In STOP mode and IDLE mode, the address bus, address/data bus, RD and WR pins become high-impedance. Normally, these pins are pulled high with a pull-up resistor. If this pull-up resistor is connected to the backed-up power supply, then if the input impedance of circuitry connected to the non-backed-up power supply is low, a current will flow through the pull-up resistor, and the power consumption will increase.
Page 636 CHAPTER 24 STANDBY FUNCTION 24.7 CAUTIONS (1) If HALT/STOP/IDLE mode (standby mode hereafter) setting is performed when a condition that release HALT mode (refer to 24.3.2 HALT Mode Release) is satisfied, standby mode is not entered, and execution of the next instruction, or a branch to a vectored interrupt service program, is performed.
Page 637 CHAPTER 25 RESET FUNCTION 25.1 RESET FUNCTION When low level is input to the RESET input pin, a system reset is affected, the various hardware units are set to the states shown in Table 25-2, and all pins except the power supply pins and the X1 and X2 pins are placed in the high- impedance state.
Page 638 CHAPTER 25 RESET FUNCTION In a reset operation upon powering on, the RESET signal must be kept active until the oscillation stabilization time has elapsed (approx. 40 ms, depending on the resonator used). Figure 25-2 Power-On Reset Operation Execution of Instruction at Oscillation Stabilization Time Delay PC Initialization, etc.
Page 639 CHAPTER 25 RESET FUNCTION Table 25-2 Hardware States After Reset (1/2) Hardware State After Reset Program counter (PC) Set with contents of reset vector table (0000H/0001H). Note 1 Stack pointer (SP) Undefined Program status word (PSW) Note 1 On-chip RAM Data memory Undefined General-purpose registers...
Page 640 CHAPTER 25 RESET FUNCTION Table 25-2 Hardware States After Reset (2/2) Hardware State After Reset Serial interface Clocked serial interface mode registers (CSIM, CSIM1, CSIM2) Shift registers (SIO, SIO1, SIO2) Undefined Asynchronous serial interface mode registers (ASIM, ASIM2) Asynchronous serial interface status registers (ASIS, ASIS2) C bus control register (IICC) Serial receive buffers (RXB, RXB2) Undefined...
Page 641 CHAPTER 25 RESET FUNCTION Figure 25-3 Reset Input Timing (a) µ µ µ µ µ PD784031 RESET (Input) Hi-Z ASTB (Output) Hi-Z A8 to A19 (Output) Hi-Z Address Program AD0 to AD7 (Output) (Input) Hi-Z RD (Output) Hi-Z WR (Output) REF2 Hi-Z ANO0, ANO1...
Page 642 CHAPTER 25 RESET FUNCTION 25.2 CAUTION Reset input when powering on must remain at the low level until oscillation stabilizes after the supply voltage has reached the prescribed voltage. User’s Manual U11316EJ4V1UD...
Page 643 CHAPTER 26 µ PD78P4038 PROGRAMMING The µ PD78P4038 incorporates a 128-Kbyte PROM as program memory. When programming the µ PD78P4038, the PROM programming mode is set by means of the V pin and the RESET pin. For the connection of unused pins, see 1.3.2 PROM Programming Mode in 1.3 PIN CONFIGURATION (Top View).
Page 644 CHAPTER 26 µ µ µ µ µ PD78P4038 PROGRAMMING (1) Read mode Read mode is set by setting CE to L and OE to L. (2) Output disable mode If OE is set to H, data output becomes high impedance and the output disable mode is set. Therefore, if multiple µ...
Page 645 CHAPTER 26 µ µ µ µ µ PD78P4038 PROGRAMMING 26.2 PROM WRITE PROCEDURE Figure 26-1 Page Program Mode Flowchart Start Address = G = 6.5 V, V = 12.5 V X = 0 Latch Address = address + 1 Latch Address = address + 1 Address = address + 1 Latch...
Page 646 CHAPTER 26 µ µ µ µ µ PD78P4038 PROGRAMMING Figure 26-2 Page Program Mode Timing Page Data Latch Page Program Page Verify A2 to A16 A0, A1 D0 to D7 Data Input Data Output + 1.5 User’s Manual U11316EJ4V1UD...
Page 647 CHAPTER 26 µ µ µ µ µ PD78P4038 PROGRAMMING Figure 26-3 Byte Program Mode Flowchart Start Address = G = 6.5 V, V = 12.5 V X = 0 X = X + 1 X = 10? 0.1 ms program pulse Address = address + 1 Fail Verify...
Page 648 CHAPTER 26 µ µ µ µ µ PD78P4038 PROGRAMMING Figure 26-4 Byte Program Mode Timing Program Program Verify A0 to A16 D0 to D7 Data Input Data Output + 1.5 Cautions 1. Ensure that V is applied before V , and cut after V 2.
Page 649 Because of its construction, the one-time PROM product ( µ PD78P4038GC-8BT, 78P4038YGC-8BT, 78P4038GK-9EU, 78P4038YGK-9EU) cannot be fully tested by NEC Electronics before shipment. After the necessary data has been written, it is recommended that screening be carried out by performing PROM verification after high-temperature storage under the following conditions.
Page 650 CHAPTER 27 INSTRUCTION OPERATIONS 27.1 LEGEND (1) Operand identifiers and descriptions (1/2) Identifier Description Note 1 r, r’ X(R0), A(R1), C(R2), B(R3), R4, R5, R6, R7, R8, R9, R10, R11, E(R12), D(R13), L(R14), H(R15) Note 1 X(R0), A(R1), C(R2), B(R3), R4, R5, R6, R7 R8, R9, R10, R11, E(R12), D(R13), L(R14), H(R15) V, U, T, W Note 2...
Page 651 CHAPTER 27 INSTRUCTION OPERATIONS (1) Operand identifiers and descriptions (2/2) Identifier Description saddr, saddr’ FD20H to FF1FH immediate data or label saddr1 FE00H to FEFFH immediate data or label saddr2 FD20H to FDFFH, FF00H to FF1FH immediate data or label saddrp FD20H to FF1EH immediate data or label (16-bit operation) saddrp1...
Page 652 CHAPTER 27 INSTRUCTION OPERATIONS (3) Flag column symbols Symbol Description (Blank) No change Cleared to 0 Set to 1 × Set or cleared depending on result P/V flag operates as parity flag P/V flag operates as overflow flag Previously saved value is restored (4) Operation column symbols Symbol Description...
Page 653 CHAPTER 27 INSTRUCTION OPERATIONS 27.2 LIST OF OPERATIONS (1) 8-bit data transfer instruction: MOV Flags Mnemonic Operands Bytes Operation AC P/V CY r ← byte r, #byte (saddr) ← byte saddr, #byte sfr ← byte sfr, #byte (saddr16) ← byte !addr16, #byte (addr24) ←...
Page 654 CHAPTER 27 INSTRUCTION OPERATIONS (2) 16-bit data transfer instruction: MOVW Flags Mnemonic Operands Bytes Operation AC P/V CY rp ← word MOVW rp, #word (saddrp) ← word saddrp, #word sfrp ← word sfrp, #word (addr16) ← word !addr16, #word (addr24) ← word !!addr24, #word rp ←...
Page 655 CHAPTER 27 INSTRUCTION OPERATIONS (3) 24-bit data transfer instruction: MOVG Flags Mnemonic Operands Bytes Operation AC P/V CY rg ← imm24 MOVG rg, #imm24 rg ← rg’ rg, rg’ rg ← (addr24) rg, !!addr24 (addr24) ← rg !!addr24, rg rg ← (saddrg) rg, saddrg (saddrg) ←...
Page 656 CHAPTER 27 INSTRUCTION OPERATIONS (5) 16-bit data exchange instruction: XCHW Flags Mnemonic Operands Bytes Operation AC P/V CY rp ↔ rp’ XCHW rp, rp’ AX ↔ (saddrp2) AX, saddrp2 rp ↔ (saddrp) rp, saddrp rp ↔ sfrp rp, sfrp AX ↔ ((saddrp)) AX, [saddrp] AX ↔...
Page 657 CHAPTER 27 INSTRUCTION OPERATIONS Flags Mnemonic Operands Bytes Operation AC P/V CY A, CY ← A + byte + CY × × × × ADDC A, #byte r, CY ← r + byte + CY × × × × r, #byte (saddr), CY ←...
Page 658 CHAPTER 27 INSTRUCTION OPERATIONS Flags Mnemonic Operands Bytes Operation AC P/V CY A, CY ← A – byte × × × × A, #byte r, CY ← r – byte × × × × r, #byte (saddr), CY ← (saddr) – byte ×...
Page 659 CHAPTER 27 INSTRUCTION OPERATIONS Flags Mnemonic Operands Bytes Operation AC P/V CY A, CY ← A – byte – CY × × × × SUBC A, #byte r, CY ← r – byte – CY × × × × r, #byte (saddr), CY ←...
Page 660 CHAPTER 27 INSTRUCTION OPERATIONS Flags Mnemonic Operands Bytes Operation AC P/V CY × × × × A, #byte A – byte × × × × r, #byte r – byte × × × × saddr, #byte (saddr) – byte × ×...
Page 661 CHAPTER 27 INSTRUCTION OPERATIONS Flags Mnemonic Operands Bytes Operation AC P/V CY ∧ A ← A × × A, #byte byte ∧ r ← r × × r, #byte byte ∧ (saddr) ← (saddr) × × saddr, #byte byte ∧ sfr ←...
Page 662 CHAPTER 27 INSTRUCTION OPERATIONS Flags Mnemonic Operands Bytes Operation AC P/V CY ∨ A ← A × × A, #byte byte ∨ r ← r × × r, #byte byte ∨ (saddr) ← (saddr) × × saddr, #byte byte ∨ sfr ←...
Page 663 CHAPTER 27 INSTRUCTION OPERATIONS Flags Mnemonic Operands Bytes Operation AC P/V CY ∨ A ← A × × A, #byte byte ∨ r ← r × × r, #byte byte ∨ (saddr) ← (saddr) × × saddr, #byte byte ∨ sfr ←...
Page 664 CHAPTER 27 INSTRUCTION OPERATIONS (7) 16-bit operation instructions: ADDW, SUBW, CMPW Flags Mnemonic Operands Bytes Operation AC P/V CY AX, CY ← AX + word × × × × ADDW AX, #word rp, CY ← rp + word × × ×...
Page 665 CHAPTER 27 INSTRUCTION OPERATIONS (8) 24-bit operation instructions: ADDG, SUBG Flags Mnemonic Operands Bytes Operation AC P/V CY rg, CY ← rg + rg’ × × × × ADDG rg, rg’ rg, CY ← rg + # imm24 × × ×...
Page 666 CHAPTER 27 INSTRUCTION OPERATIONS (11) Increment/decrement instructions: INC, DEC, INCW, DECW, INCG, DECG Flags Mnemonic Operands Bytes Operation AC P/V CY r ← r + 1 × × × (saddr) ← (saddr) + 1 × × × saddr r ← r –1 ×...
Page 667 CHAPTER 27 INSTRUCTION OPERATIONS (13) Shift/rotate instructions: ROR, ROL, RORC, ROLC, SHR, SHL, SHRW, SHLW, ROR4, ROL4 Flags Mnemonic Operands Bytes Operation AC P/V CY ← ← ) × n times n = 0 to 7 × r, n (CY, rm –...
Page 668 CHAPTER 27 INSTRUCTION OPERATIONS Flags Mnemonic Operands Bytes Operation AC P/V CY ∧ CY ← CY × AND1 CY, saddr. bit (saddr. bit) ∧ CY ← CY × CY, /saddr. bit (saddr. bit) ∧ CY ← CY × CY, sfr. bit sfr.
Page 669 CHAPTER 27 INSTRUCTION OPERATIONS Flags Mnemonic Operands Bytes Operation AC P/V CY ∨ CY ← CY × XOR1 CY, saddr. bit (saddr. bit) ∨ CY ← CY × CY, sfr. bit sfr. bit ∨ CY ← CY × CY, X. bit X.
Page 670 CHAPTER 27 INSTRUCTION OPERATIONS (15) Stack manipulation instructions: PUSH, PUSHU, POP, POPU, MOVG, ADDWG, SUBWG, INCG, DECG Flags Mnemonic Operands Bytes Operation AC P/V CY (SP – 2) ← PSW, SP ← SP – 2 PUSH (SP – 2) ← sfrp, SP ← SP – 2 sfrp (SP –...
Page 671 CHAPTER 27 INSTRUCTION OPERATIONS (16) Call/return instructions: CALL, CALLF, CALLT, BRK, BRKCS, RET, RETI, RETB, RETCS, RETCSB Flags Mnemonic Operands Bytes Operation AC P/V CY (SP – 3) ← (PC + 3), SP ← SP – 3, CALL !addr16 ← 0, PC ←...
Page 672 CHAPTER 27 INSTRUCTION OPERATIONS (17) Unconditional branch instruction: BR Flags Mnemonic Operands Bytes Operation AC P/V CY ← 0, PC ← addr16 !addr16 PC ← addr20 !!addr20 ← 0, PC ← rp PC ← rg ← 0, PC ← (rp) [rp] PC ←...
Page 673 CHAPTER 27 INSTRUCTION OPERATIONS (18) Conditional branch instructions: BNZ, BNE, BZ, BE, BNC, BNL, BC, BL, BNV, BPO, BV, BPE, BP, BN, BLT, BGE, BLE, BGT, BNH, BH, BF, BT, BTCLR, BFSET, DBNZ Flags Mnemonic Operands Bytes Operation AC P/V CY PC ←...
Page 674 CHAPTER 27 INSTRUCTION OPERATIONS Flags Mnemonic Operands Bytes Operation AC P/V CY PC ← PC + 3 Note 1 saddr. bit, $addr20 + jdisp8 if (saddr. bit) = 1 PC ← PC + 4 + jdisp8 if sfr. bit = 1 sfr.
Page 675 CHAPTER 27 INSTRUCTION OPERATIONS Flags Mnemonic Operands Bytes Operation AC P/V CY {PC ← PC + 4 + jdisp8, (saddr. bit) ← 1} Note 1 BFSET saddr. bit, $addr20 if (saddr. bit) = 0 {PC ← PC + 4 + jdisp8, sfr. bit ← 1} if sfr. bit = 0 sfr.
Page 676 CHAPTER 27 INSTRUCTION OPERATIONS (20) Special instructions: CHKL, CHKLA Flags Mnemonic Operands Bytes Operation AC P/V CY ∨ × × CHKL (Pin level) (output latch) ∨ A ← (pin level) × × CHKLA (output latch) (21) String instructions: MOVTBLW, MOVM, XCHM, MOVBK, XCHBK, CMPME, CMPMNE, CMPMC, CMPMNC, CMPBKE, CMPBKNE, CMPBKC, CMPBKNC Flags Mnemonic...
Page 677 CHAPTER 27 INSTRUCTION OPERATIONS Flags Mnemonic Operands Bytes Operation AC P/V CY (TDE) – (WHL), TDE ← TDE + 1, × × × × CMPBKNE [TDE + ], [WHL +] WHL ← WHL + 1, C ← C – 1 End if C = 0 or Z = 1 (TDE) –...
Page 678 CHAPTER 27 INSTRUCTION OPERATIONS 27.3 INSTRUCTIONS LISTED BY TYPE OF ADDRESSING (1) 8-bit instructions (combinations expressed by writing A for r are shown in parentheses) MOV, XCH, ADD, ADDC, SUB, SUBC, AND OR XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, SHR, SHL, ROR4, ROL4, DBNZ, PUSH, POP, MOVM, XCHM, CMPME, CMPMNE, CMPMNC, CMPMC, MOVBK, XCHBK, CMPBKE, CMPBKNE, CMPBKNC, CMPBKC, CHKL, CHKLA Table 27-1 List of Instructions by 8-Bit Addressing (1/2)
Page 679 CHAPTER 27 INSTRUCTION OPERATIONS Table 27-1 List of Instructions by 8-Bit Addressing (2/2) 2nd Operand !addr16 [WHL +] Note 2 [saddrp] PSWL None !!addr24 [WHL –] 1st Operand [%saddrg] PSWH (MOV) (MOV) (XCH) (XCH) Note 1 Note 1 Note 1 (ADD) Note 3 MULU...
Page 680 CHAPTER 27 INSTRUCTION OPERATIONS (2) 16-bit instructions (combinations expressed by writing AX for rp are shown in parentheses) MOVM, XCHW, ADDW, SUBW, CMPW, MULUW, MULW, DIVUX, INCW, DECW, SHRW, SHLW, PUSH, POP, ADDWG, SUBWG, PUSHU, POPU, MOVTBLW, MACW, MACSW, SACW Table 27-2 List of Instructions by 16-Bit Addressing (1/2) 2nd Operand saddr...
Page 681 CHAPTER 27 INSTRUCTION OPERATIONS Table 27-2 List of Instructions by 16-Bit Addressing (2/2) 2nd Operand !!addr16 Note 2 [saddrp] [WHL +] byte None !!addr24 1st Operand [%saddrg] (MOVW) MOVW (MOVW) XCHW XCHW (XCHW) Note 4 MOVW SHRW MULW SHLW INCW DECW saddrp INCW...
Page 682 CHAPTER 27 INSTRUCTION OPERATIONS (3) 24-bit instructions (combinations expressed by writing WHL for rg are shown in parentheses) MOVG, ADDG, SUBG, INCG, DECG, PUSH, POP Table 27-3 List of Instructions by 24-Bit Addressing 2nd Operand Note # imm24 saddrg !!addr24 mem1 [%saddrg] None...
Page 683 CHAPTER 27 INSTRUCTION OPERATIONS (5) Call/return instructions / branch instructions CALL, CALLF, CALLT, BRK, RET, RETI, RETB, RETCS, RETCSB, BRKCS, BR, BNZ, BNE, BZ, BE, BNC, BNL, BC, BL, BNV, BPO, BV, BPE, BP, BN, BLT, BGE, BLE, BGT, BNH, BH, BF, BT, BTCLR, BFSET, DBNZ Table 27-5 List of Instructions by Call/Return Instruction / Branch Instruction Addressing Instruction Address...
Page 684 CHAPTER 28 ELECTRICAL SPECIFICATIONS ° ABSOLUTE MAXIMUM RATINGS (T = 25 Parameter Symbol Conditions Rating Unit Supply voltage –0.5 to +7.0 to V + 0.5 –0.5 to +0.5 Input voltage –0.5 to V + 0.5 µ PD78P4038, 78P4038Y only. –0.5 to +13.5 TEST/V pin and P21/INTP0/A9 pin in PROM...
Page 685 CHAPTER 28 ELECTRICAL SPECIFICATIONS OPERATING CONDITIONS • Operating ambient temperature (T : –40 to +85°C ) (at pins which are not specified) : 0 to 200 µ s • Rise time and fall time (t • Power supply voltage and clock cycle time : See Figure 28-1.
Page 686 CHAPTER 28 ELECTRICAL SPECIFICATIONS ° OSCILLATOR CHARACTERISTICS (T = –40 to +85 C, V = +4.5 to 5.5 V, V = 0 V) Resonator Recommended Circuit Parameter MIN. MAX. Unit Ceramic or crystal Oscillator frequency (f resonator External clock X1 input frequency (f X1 input rise and fall times X1 input high-level and low- level widths (t...
Page 687 CHAPTER 28 ELECTRICAL SPECIFICATIONS ° OSCILLATOR CHARACTERISTICS (T = –40 to +85 C, V = +2.7 to 5.5 V, V = 0 V) Resonator Recommended Circuit Parameter MIN. MAX. Unit Ceramic resonator Oscillator frequency (f or crystal External clock X1 input frequency (f X1 input rise and fall times X1 input high-level and low- level widths (t...
Page 688 CHAPTER 28 ELECTRICAL SPECIFICATIONS ° DC CHARACTERISTICS (T = –40 to +85 C, V = AV = +2.7 to 5.5 V, V = AV = 0 V) (1/2) Parameter Symbol Conditions MIN. TYP. MAX. Unit Input low voltage For pins other than those described in –0.3 0.3V Notes 1, 2, 3, 4, and 6...
Page 689 CHAPTER 28 ELECTRICAL SPECIFICATIONS ° DC CHARACTERISTICS (T = –40 to +85 C, V = AV = +2.7 to 5.5 V, V = AV = 0 V) (2/2) Symbol Conditions MIN. TYP. MAX. Unit Parameter 0 V ≤ V ≤ V ±10 µ...
Page 690 CHAPTER 28 ELECTRICAL SPECIFICATIONS ° AC CHARACTERISTICS (T = –40 to +85 C, V = AV = +2.7 to 5.5 V, V = AV = 0 V) (1) Read/write operation (1/2) Parameter Unit Symbol Conditions MIN. MAX. = +5.0 V ±10% Address setup time (0.5 + a) T –...
Page 691 CHAPTER 28 ELECTRICAL SPECIFICATIONS (1) Read/write operation (2/2) Unit Parameter Symbol Conditions MIN. MAX. = +5.0 V ±10% Data setup time (to WR↑) (1.5 + n) T – 30 SODW = +2.7 to 5.5 V (1.5 + n) T – 40 = +5.0 V ±10% Data hold time (from WR↑) Note...
Page 692 CHAPTER 28 ELECTRICAL SPECIFICATIONS (3) External wait timing Symbol Unit Parameter Conditions MIN. MAX. = +5.0 V ±10% Delay from address to WAIT↓ input (2 + a) T – 40 DAWT = +2.7 to 5.5 V (2 + a) T – 60 = +5.0 V ±10% Delay from ASTB↓...
Page 693 CHAPTER 28 ELECTRICAL SPECIFICATIONS ° SERIAL OPERATION (T = –40 to +85 C, V = +2.7 to 5.5 V, AV = 0 V) (1) CSI Parameter Unit Symbol Conditions MIN. MAX. Serial clock cycle time (SCK0) Input External clock 10/f + 380 CYSK0 When SCK0 and SO0 are CMOS I/O...
Page 694 CHAPTER 28 ELECTRICAL SPECIFICATIONS (3) IOE1, IOE2 Unit Parameter Symbol Conditions MIN. MAX. = +5.0 V ±10% Serial clock cycle time Input CYSK1 (SCK1, SCK2) = +2.7 to 5.5 V Output Internal, divided by 16 = +5.0 V ±10% Serial clock low-level width Input WSKL1 (SCK1, SCK2)
Page 695 CHAPTER 28 ELECTRICAL SPECIFICATIONS Note CLOCK OUTPUT OPERATION Symbol Unit Parameter Conditions MIN. MAX. CLKOUT cycle time CYCL = +5.0 V ±10% CLKOUT low-level width 0.5t – 10 CYCL = +2.7 to 5.5 V 0.5t – 20 CYCL = +5.0 V ±10% CLKOUT high-level width 0.5t –...
Page 696 CHAPTER 28 ELECTRICAL SPECIFICATIONS OTHER OPERATIONS (a) µ PD784035, 784036, 784037, 784038, 78P4038, 78P4038Y, 784031(A), 784035(A), 784036(A) Unit Parameter Symbol Conditions MIN. MAX. µ s NMI low-level width WNIL µ s NMI high-level width WNIH INTP0 low-level width WIT0L CYSMP INTP0 high-level width WIT0H CYSMP...
Page 697 CHAPTER 28 ELECTRICAL SPECIFICATIONS A/D CONVERTER CHARACTERISTICS ° = –40 to +85 C, V = AV = AV = +2.7 to 5.5 V, V = AV = 0 V) REF1 Parameter Symbol Conditions MIN. TYP. MAX. Unit Resolution Note %FSR Total error ( µ...
Page 698 CHAPTER 28 ELECTRICAL SPECIFICATIONS ° D/A CONVERTER CHARACTERISTICS (T = –40 to +85 C, V = AV = +2.7 to 5.5 V, V = AV = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Resolution Total error Load conditions: V = AV = AV REF2...
Page 699 CHAPTER 28 ELECTRICAL SPECIFICATIONS ° DATA RETENTION CHARACTERISTICS (T = –40 to +85 Symbol Conditions MIN. TYP. MAX. Unit Parameter Data retention voltage STOP mode DDDR µ A Note Data retention current = +2.7 to 5.5 V DDDR DDDR ( µ PD784031, 784031Y, µ...
Page 700 CHAPTER 28 ELECTRICAL SPECIFICATIONS TIMING WAVEFORM (1) Read operation WSTH ASTB SAST DRST DSTID HSTLA A8-A19 DAID AD0-AD7 DSTR HRID DRID (2) Write operation WSTH ASTB SAST DWST DSTOD HSTLA A8-A19 AD0-AD7 DSTW HWOD DWOD SODW User’s Manual U11316EJ4V1UD...
Page 701 CHAPTER 28 ELECTRICAL SPECIFICATIONS HOLD TIMING ADTB, A8-A19, AD0-AD7, RD, WR FHQC DCFHA DHAC HLDRQ DHQLHAL DHQHHAH HLDAK EXTERNAL WAIT SIGNAL INPUT TIMING (1) Read operation ASTB DSTWTH HSTWTH DSTWT A8-A19 AD0-AD7 DAWT DWTID DRWTL DWTR WAIT HRWT DRWTH (2) Write operation ASTB DSTWTH HSTWTH...
Page 702 CHAPTER 28 ELECTRICAL SPECIFICATIONS REFRESH TIMING WAVEFORM (1) Random read/write cycle ASTB (2) When refresh memory is accessed for a read and write at the same time ASTB RD, WR DSTRFQ DRFQST WRFQH REFRQ WRFQL (3) Refresh after a read ASTB DRFQST DRRFQ...
Page 703 CHAPTER 28 ELECTRICAL SPECIFICATIONS SERIAL OPERATION (1) CSI WSKL0 WSKH0 SSSK0 HSSK0 CYSK0 Input data DSBSK1 Output data C ( µ PD784038Y Subseries Only) (2) I HIGH HD;DAT SU;DAT (3) IOE1, IOE2 WSKL1 WSKH1 SSSK1 HSSK1 CYSK1 Input data HSOSK DSOSK Output data (4) UART, UART2...
Page 704 CHAPTER 28 ELECTRICAL SPECIFICATIONS Note CLOCK OUTPUT TIMING CLKOUT CYCL Note Not provided in the µ PD784031, 784031Y, and 784031(A). INTERRUPT INPUT TIMING WNIH WNIL WIT0H WIT0L INTP0 WIT1H WIT1L INTP1-INTP3 WIT2H WIT2L INTP4, INTP5 RESET INPUT TIMING WRSH WRSL RESET User’s Manual U11316EJ4V1UD...
Page 705 CHAPTER 28 ELECTRICAL SPECIFICATIONS EXTERNAL CLOCK TIMING DATA RETENTION CHARACTERISTICS STOP mode setting DDDR DREL WAIT RESET (Clearing by falling edge) (Clearing by rising edge) User’s Manual U11316EJ4V1UD...
Page 706 CHAPTER 28 ELECTRICAL SPECIFICATIONS ± ° = 0 V) : µ PD78P4038 and 78P4038Y only DC PROGRAMMING CHARACTERISTICS (T = 25 C, V Parameter Symbol MIN. TYP. MAX. Unit Conditions High-level input voltage + 0.3 Low-level input voltage –0.3 ±10 µ...
Page 707 CHAPTER 28 ELECTRICAL SPECIFICATIONS ± ° = 0 V) : µ PD78P4038 and 78P4038Y only AC PROGRAMMING CHARACTERISTICS (T = 25 C, V PROM Write Mode (Page Program Mode) Parameter Symbol Conditions MIN. TYP. MAX. Unit µ s Address setup time µ...
Page 708 CHAPTER 28 ELECTRICAL SPECIFICATIONS PROM Write Mode (Byte Program Mode) Parameter Symbol Conditions MIN. TYP. MAX. Unit µ s Address setup time µ s CE set time µ s Input data setup time µ s Address hold time µ s Input data hold time Output data hold time µ...
Page 709 CHAPTER 28 ELECTRICAL SPECIFICATIONS PROM Write Mode Timing (Page Program Mode) : µ PD78P4038 and 78P4038Y only Page data latch Page program Program verify A2-A16 A0, A1 Hi-Z Hi-Z Hi-Z D0-D7 Data PGMS Data input output + 1.5 User’s Manual U11316EJ4V1UD...
Page 710 CHAPTER 28 ELECTRICAL SPECIFICATIONS PROM Write Mode Timing (Byte Program Mode) : µ PD78P4038 and 78P4038Y only Program Program verify A0-A16 Hi-Z Hi-Z Hi-Z D0-D7 Data output Data input + 1.5 Cautions 1. V must be applied before V , and must be cut after V 2.
Page 711 CHAPTER 29 PACKAGE DRAWINGS CHAPTER 29 PACKAGE DRAWINGS 80-PIN PLASTIC QFP (14x14) detail of lead end NOTE ITEM MILLIMETERS Each lead centerline is located within 0.13 mm of 17.20±0.20 its true position (T.P.) at maximum material condition. 14.00±0.20 14.00±0.20 17.20±0.20 0.825 0.825 0.32±0.06...
Page 712 CHAPTER 29 PACKAGE DRAWINGS 80-PIN PLASTIC TQFP (FINE PITCH) (12x12) detail of lead end NOTE ITEM MILLIMETERS Each lead centerline is located within 0.08 mm of 14.0±0.2 its true position (T.P.) at maximum material condition. 12.0±0.2 12.0±0.2 14.0±0.2 1.25 1.25 0.22±0.05 0.08 0.5 (T.P.)
Page 713 CHAPTER 29 PACKAGE DRAWINGS 80-PIN PLASTIC QFP (14x14) detail of lead end NOTE ITEM MILLIMETERS Each lead centerline is located within 0.13 mm of 17.2±0.4 its true position (T.P.) at maximum material condition. 14.0±0.2 14.0±0.2 17.2±0.4 0.825 0.825 0.30±0.10 0.13 0.65 (T.P.) 1.6±0.2 0.8±0.2...
Page 714 For details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales representative. Remark The soldering conditions for the µ PD784031YGC-8BT, 784031GC(A)-3B9, 784035YGK-×××-9EU, 784035GC(A)- ×××-3B9, 784036YGK-×××-9EU, 784036GC(A)-×××-3B9, and 78P4038YGK-9EU are undetermined.
Page 715 CHAPTER 30 RECOMMENDED SOLDERING CONDITIONS Table 30-1 Surface Mounting Type Soldering Conditions (2/2) (2) µ µ µ µ µ PD784031GK-9EU: 80-pin plastic TQFP (fine pitch) (12 x 12) µ µ µ µ µ PD784031YGK-9EU: 80-pin plastic TQFP (fine pitch) (12 x 12) µ...
Page 716 APPENDIX A DIFFERENCES WITH µ PD784026 SUBSERIES Table A-1 Differences with µ PD784026 Subseries (1/3) µ PD784026 Subseries µ PD784038 Subseries Item 4 MHz ≤ f ≤ 25 MHz 4 MHz ≤ f ≤ 32 MHz (target value) Operating frequency Minimum instruction 160 ns (at 25 MHz) 125 ns (at 32 MHz)
Page 717 APPENDIX A DIFFERENCES WITH µ PD784026 SUBSERIES Table A-1 Differences with µ PD784026 Subseries (2/3) µ PD784026 Subseries µ PD784038 Subseries Item • UART/IOE (3-wire serial I/O) × 2 channels • UART/IOE (3-wire serial I/O) × 2 channels Serial interface •...
Page 718 APPENDIX A DIFFERENCES WITH µ µ µ µ µ PD784026 SUBSERIES Table A-1 Differences from µ µ µ µ µ PD784026 Subseries (3/3) µ PD784026 Subseries µ PD784038 Subseries Item Serial interface <Register and bit name change> SBIC mode register (SBIC) C bus control register (IICC) SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT IICC...
Page 719 APPENDIX B DEVELOPMENT TOOLS The following development tools are available for system development using the µ PD784038 Subseries. Figure B-1 shows the development tools. • For PC98-NX series Unless otherwise specified, products supported by IBM PC/AT and compatible machines can be used for the PC98-NX series.
Page 720 APPENDIX B DEVELOPMENT TOOLS Figure B-1 Development Tool Configuration (1/2) (1) When using in-circuit emulator IE-78K4-NS Language processing software • Assembler package • C compiler package • C library source file • Device file Debugging tools • System simulator • Integrated debugger •...
Page 721 APPENDIX B DEVELOPMENT TOOLS Figure B-1 Development Tool Configuration (2/2) (2) When using in-circuit emulator IE-784000-R Language processing software • Assembler package • C compiler package • C library source file • Device file Debugging tools • System simulator • Integrated debugger •...
Page 722 APPENDIX B DEVELOPMENT TOOLS B.1 LANGUAGE PROCESSING SOFTWARE SP78K4 78K/IV Series Development tools (software) common to the 78K/IV Series are combined in this software package package. Part number: µ S××××SP78K4 RA78K4 Assembler package Program that converts a program written in mnemonic to an executable microcontroller object code.
Page 723 APPENDIX B DEVELOPMENT TOOLS Remark The ×××× part number differs depending on the host machine and operating system used. µ S××××SP78K4 ×××× Host Machine Supply Medium AB17 PC-9800 series, Japanese Windows CD-ROM IBM PC/AT compatibles BB17 English Windows µ S××××RA78K4 µ...
Page 724 APPENDIX B DEVELOPMENT TOOLS B.2 PROM WRITING TOOLS (1) Hardware PG-1500 This PROM programmer can program single-chip microcontrollers containing PROM in a stand-alone mode or under the control of the host machine, when a board supplied as an accessory and an optionally available PROM programmer adapter are connected.
Page 725 APPENDIX B DEVELOPMENT TOOLS B.3 DEBUGGING TOOLS B.3.1 Hardware (1/2) (1) When using in-circuit emulator IE-78K4-NS IE-78K4-NS In-circuit emulator used to debug hardware and software when developing application In-circuit emulator systems using the 78K/IV Series. Supports the integrated debugger (ID78K4-NS). Use in combination with an interface adapter to connect to the power supply unit, emulation probe, and host machine.
Page 726 APPENDIX B DEVELOPMENT TOOLS B.3.1 Hardware (2/2) (2) When using in-circuit emulator IE-784000-R IE-784000-R The IE-784000-R is an in-circuit emulator common to the 78K/IV Series, and is used in In-circuit emulator combination with IE-784000-R-EM and IE-784038-R-EM1, which are sold separately. This in- circuit emulator debugs the connected host machine.
Page 727 APPENDIX B DEVELOPMENT TOOLS B.3.2 Software SM78K4 This enables debugging at the C source level or assembler level while simulating System simulator operation of the target system on the host machine. The SM78K4 operates on Windows. By using the SM78K4, logic verification and performance verification can be performed separately to hardware development without using an in-circuit emulator, thus improving development efficiency and software quality.
Page 728 APPENDIX B DEVELOPMENT TOOLS B.4 CAUTIONS ON DESIGNING TARGET SYSTEM The connection condition diagrams for the emulation probe, conversion socket, and conversion adapter are shown below. Design the system considering the shape of components, etc. to be mounted on the target system in accordance with this configuration.
Page 729 APPENDIX B DEVELOPMENT TOOLS Figure B-3 Target System Connection Conditions (1) Emulation probe NP-80GC-TQ, NP-H80GC-TQ Emulation board IE-784038-NS-EM1 25 mm 50 mm 35 mm 10 mm 10 mm Conversion socket TGC-080SBP Pin 1 35 mm 18.7 mm 60 mm Target system Remark NP-80GC-TQ and NP-H80GC-TQ are products made by Naito Densei Machida Mfg.
Page 730 APPENDIX B DEVELOPMENT TOOLS Figure B-4 Target System Connection Conditions (2) Emulation probe NP-80GK Emulation board IE-784038-NS-EM1 25 mm 40 mm 34 mm 23 mm 11 mm Conversion adapter TGK-080SDW Pin 1 45 mm 18 mm 65 mm Target system Remark NP-80GK is a product made by Naito Densei Machida Mfg.
Page 731 APPENDIX B DEVELOPMENT TOOLS B.5 CONVERSION SOCKET (EV-9200GC-80) AND CONVERSION ADAPTER (TGK-080SDW) (1) The package drawing of the conversion socket (EV-9200GC-80) and recommended board installation pattern Figure B-5 Package Drawing of EV-9200GC-80 (Reference) (Unit: mm) EV-9200GC-80 No.1 pin index EV-9200GC-80-G1E ITEM MILLIMETERS INCHES...
Page 732 APPENDIX B DEVELOPMENT TOOLS Figure B-6 Recommended Board Installation Pattern of EV-9200GC-80 (Reference) (Unit: mm) EV-9200GC-80-P1E ITEM MILLIMETERS INCHES 19.7 0.776 15.0 0.591 0.65 ± 0.02 × 19=12.35 ± 0.05 × 0.748=0.486 +0.001 +0.003 0.026 –0.002 –0.002 0.65 ± 0.02 × 19=12.35 ± 0.05 ×...
Page 733 APPENDIX B DEVELOPMENT TOOLS (2) Package drawing of the conversion adapter (TGK-080SDW) Combined with the emulation probe and mounted on the board. Figure B-7 TGK-080SDW Package Drawing (Reference) (Unit: mm) M2 screw I J J J L L LM Protrusion : 4 places ITEM MILLIMETERS INCHES...
Page 734 APPENDIX C EMBEDDED SOFTWARE The following embedded software is available for more efficient program development or maintenance of the µ PD784038, 784038Y Subseries. REAL-TIME OPERATING SYSTEM This is a real-time OS complying with the µ ITRON specification. The RX78K4 nucleus and tools to RX78K4 real-time OS create multiple information tables (configurator) have been added.
Page 735 APPENDIX D REGISTER INDEX D.1 REGISTER INDEX (REGISTER NAME) A/D conversion result register (ADCR) ....... 388 Hold mode register (HLDM) ........607 A/D converter mode register (ADM) ......389 Asynchronous serial interface mode register (ASIM) ..................417 I2C bus control register (IICC) ......451, 466 Asynchronous serial interface mode register 2 (ASIM2) In-service priority register (ISPR) ........
Page 736 APPENDIX D REGISTER INDEX Program status word (PSWL) ....... 84, 516 Programmable wait control register 1 (PWC1) ... 589 Programmable wait control register 2 (PWC2) ... 589 Pull-up resistor option register (PUO) ........118, 129, 134, 144, 150, 156, 167 PWM control register (PWMC) ........
Page 737 APPENDIX D REGISTER INDEX D.2 REGISTER INDEX (REGISTER SYMBOL) DACS0: D/A conversion value setting register 0 ..407 ADCR: A/D conversion result register ......388 DACS1: D/A conversion value setting register 1 ..407 ADIC: Interrupt control register ........510 DAM: D/A converter mode register ......
Page 738 APPENDIX D REGISTER INDEX PM3: Port 3 mode register .......... 141 TMC0: Timer control register 0 ......193, 361 PM4: Port 4 mode register .......... 147 TMC1: Timer control register 1 ......252, 291 PM5: Port 5 mode register .......... 153 TOC: Timer output control register ....
Page 739 APPENDIX E REVISION HISTORY The history of revisions hitherto made is shown as follows. (1/3) Edition Revisions Chapter • Addition of description on µ PD784031 and 784031Y Second General • Addition of 80-pin plastic QFP (14 × 14 mm, 1.4 mm thick) Addition of description on µ...
Page 740 APPENDIX E REVISION HISTORY (2/3) Edition Revisions Chapter Third • Change in 78K/IV Series Product Development Diagram CHAPTER 1 GENERAL • Addition of Table 3-6 Limits of Reading Timer Register CHAPTER 3 CPU ARCHITECTURE • Addition of Table 8-5 Limits of Reading Timer Register CHAPTER 8 TIMER/COUNTER 0 •...
Page 741 APPENDIX E REVISION HISTORY (3/3) Edition Revisions Chapter Fourth • Update of 78K/IV Series Product Development Diagram CHAPTER 1 GENERAL • Addition and deletion of products in 1.2 ORDERING INFORMATION AND QUALITY GRADES • Addition of 1.7 DIFFERENCES BETWEEN STANDARD-GRADE PRODUCTS AND SPECIAL-GRADE PRODUCTS Addition of caution on compare register CR00 match interrupt to 8.9 CAUTIONS CHAPTER 8 TIMER/COUNTER 0...

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NEC uPD784038 Series User Manual

Chapter 1 General

Features

Ordering Information and Quality Grades

Pin Configuration (Top View)

Application System Configuration Example (Ppc)

Block Diagram

List of Functions

Differences between Standard-Grade Products and Special-Grade Products

MAJOR DIFFERENCES with Μ Μ Μ Μ Μ PD784026 SUBSERIES

Chapter 2 Pin Functions

Pin Function Tables

Pin Functions

Input/Output Circuits and Connection of Unused Pins

Cautions

Chapter 3 Cpu Architecture

Memory Space

Internal Rom Area

Base Area

Internal Data Area

External Memory Space

Μ Μ Μ Μ Μ PD78P4038 MEMORY MAPPING

Control Registers

General Registers

Special Function Registers (Sfrs)

Cautions

Chapter 4 Clock Generator

Configuration and Function

Control Registers

Clock Generator Operation

Cautions

Chapter 5 Port Functions

Digital Input/Output Ports

Port 0

Port 1

Port 2

Port 3

Port 4

Port 5

Port 6

Port 7

Port Output Check Function

Cautions

Chapter 6 Real-Time Output Function

Configuration and Function

Real-Time Output Port Control Register (Rtpc)

Real-Time Output Port Accesses

Operation

Example of Use

Cautions

Chapter 7 Outline of Timer/Counter

Chapter 8 Timer/Counter 0

Functions

Configuration

Timer/Counter 0 Control Registers

16-Bit Timer Register 0 (Tm0) Operation

External Event Counter Function

Compare Register and Capture Register Operation

Basic Operation of Output Control Circuit

Examples of Use

Cautions

Chapter 9 Timer/Counter 1

Functions

Configuration

Timer/Counter 1 Control Registers

Timer Register 1 (Tm1) Operation

External Event Counter Function

Compare Register, Capture/Compare Register, and Capture Register Operation

Examples of Use

Cautions

Chapter 10 Timer/Counter 2

Functions

Configuration

Timer/Counter 2 Control Registers

Timer Register 2 (Tm2) Operation

External Event Counter Function

One-Shot Timer Function

Compare Register, Capture/Compare Register, and Capture Register Operation

Basic Operation of Output Control Circuit

Examples of Use