Page 1 User’s Manual User’s Manual µ PD784225, 784225Y Subseries 16-/8-Bit Single-Chip Microcontrollers Hardware µ PD784224 µ PD784224Y µ PD784225 µ PD784225Y µ PD78F4225 µ PD78F4225Y Document No. U12697EJ3V0UM00 (3rd edition) Date Published April 2001 N CP(K) © 1997, 2000 Printed in Japan...
Page 2 [MEMO] User’s Manual U12697EJ3V0UM...
Page 3 Reset operation must be executed immediately after power-on for devices having reset function. EEPROM and IEBus are trademarks of NEC Corporation. Windows is either a registered trademark or trademark of Microsoft Corporation in the United States and/ or other countries.
Page 4 The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products may be prohibited without governmental license. To export or re-export some or all of these products from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
Page 5 NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others.
Page 6 Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: •...
Page 7 Major Revisions in This Edition Page Description Throughout The following products have been developed. µ PD78F4225GC-8BT, 78F4225GK-9EU, 78F4225YGC-8BT, 78F4225YGK-9EU • CHAPTER 8 16-BIT TIMER/EVENT COUNTER • p.174 Addition of Caution related to operation in one-shot pulse output mode CHAPTER 11 WATCH TIMER •...
Page 8 INTRODUCTION Target Readers This manual is intended for user engineers who wish to understand the functions of the µ PD784225 and 784225Y Subseries and design its application systems. This manual describes the hardware functions of the µ PD784225 and 784225Y Subseries. Purpose The µ...
Page 9 • To understand the overall functions → Read in the order of the contents. • To debug when the operation is unusual → Since the cautions are summarized at the end of each chapter, see the cautions associated with the function. •...
Page 10 Register Representation Bits whose numbers are circled are reserved words in NEC’s assembler or are defined as sfr × × variables by the #pragma sfr directive in the C compiler. When writing When reading Write 0 or 1. The operation Read 0 or 1.
Page 11 Document No. SEMICONDUCTOR SELECTION GUIDE Products & Packages (CD-ROM) X13769X Semiconductor Device Mounting Technology Manual C10535E Quality Grades on NEC Semiconductor Devices C11531E NEC Semiconductor Device Reliability/Quality Control System C10983E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD)
Page 12: Table Of Contents
CONTENTS CHAPTER 1 OVERVIEW ........................31 Features ..........................33 Ordering Information ......................34 Pin Configuration (Top View) ....................35 Block Diagram ........................38 Function List ......................... 39 Differences Between µ PD784225 Subseries Products and µ PD784225Y Subseries Products ..........................42 CHAPTER 2 PIN FUNCTIONS ......................
Page 13 4.4.1 Main system clock oscillator ......................100 4.4.2 Subsystem clock oscillator ......................101 4.4.3 Frequency divider ......................... 104 4.4.4 When no subsystem clocks are used ................... 104 Clock Generator Operations ....................105 4.5.1 Main system clock operations ....................... 106 4.5.2 Subsystem clock operations ......................107 Changing System Clock and CPU Clock Settings .............
Page 14 8.4.5 Operation to output square wave ....................172 8.4.6 Operation to output one-shot pulse ..................... 174 Cautions ..........................180 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1, 2 ..............184 Functions ..........................184 Configuration ........................185 Control Registers ........................188 Operation ..........................193 9.4.1 Operation as interval timer (8-bit operation) ................
Page 15 13.4 Operations ..........................236 13.4.1 Basic operations of A/D converter ....................236 13.4.2 Input voltage and conversion result .................... 238 13.4.3 Operations mode of A/D converter ....................239 13.5 Reading the A/D Converter Characteristics Table ............. 242 13.6 Cautions ..........................245 CHAPTER 14 D/A CONVERTER .......................
Page 16 18.5.6 Wait signal (WAIT) ........................313 18.5.7 I C interrupt request (INTIIC0) ....................315 18.5.8 Interrupt request (INTIIC0) generation timing and wait control ........... 333 18.5.9 Address match detection ......................334 18.5.10 Error detection ..........................334 18.5.11 Extended codes .......................... 335 18.5.12 Arbitration ............................
Page 17 22.4.2 BRKCS instruction software interrupt (software context switching) acknowledgment operation ......................378 22.5 Operand Error Interrupt Acknowledgment Operation ............379 22.6 Non-Maskable Interrupt Acknowledgment Operation ............380 22.7 Maskable Interrupt Acknowledgment Operation ............... 384 22.7.1 Vectored interrupt ........................386 22.7.2 Context switching ........................386 22.7.3 Maskable interrupt priority levels ....................
Page 18 24.3.1 Settings and operating states of HALT mode ................472 24.3.2 Releasing HALT mode ........................ 474 24.4 STOP Mode ..........................482 24.4.1 Settings and operating states of STOP mode ................482 24.4.2 Releasing STOP mode ....................... 484 24.5 IDLE Mode ..........................490 24.5.1 Settings and operating states of IDLE mode ................
Page 19 APPENDIX C EMBEDDED SOFTWARE .................... 568 APPENDIX D REGISTER INDEX ....................... 570 D.1 Register Index ......................... 570 D.2 Register Index (Alphabetical Order) ..................573 APPENDIX E REVISION HISTORY ....................577 User’s Manual U12697EJ3V0UM...
Page 20 LIST OF FIGURES (1/8) Figure No. Title Page Pin I/O Circuits ..........................µ PD784224 Memory Map ......................... µ PD784225 Memory Map ......................... Internal RAM Memory Map ....................... Format of Internal Memory Size Switching Register (IMS) ............... Format of Program Counter (PC) ..................... Format of Program Status Word (PSW) ...................
Page 21 LIST OF FIGURES (2/8) Figure No. Title Page 5-19 Block Diagram of P130 and P131 ..................... 5-20 Format of Port Mode Register ......................5-21 Format of Pull-Up Resistor Option Register ..................5-22 Format of Port Function Control Register 2 (PF2) ................Block Diagram of Real-Time Output Port ..................
Page 22 LIST OF FIGURES (3/8) Figure No. Title Page 8-28 Timing of One-Shot Pulse Output Operation by External Trigger (with Riding Edge Specified) ..8-29 Start Timing of 16-Bit Timer Counter 0 ..................... 8-30 Timing After Changing Compare Register During Timer Count Operation ........8-31 Data Hold Timing of Capture Register ....................
Page 23 LIST OF FIGURES (4/8) Figure No. Title Page 13-7 A/D Conversion Operation by Software Start ................... 13-8 Overall Error ............................13-9 Quantization Error ..........................13-10 Zero-Scale Error ..........................13-11 Full-Scale Error ..........................13-12 Integral Linearity Error ........................13-13 Differential Linearity Error ......................... 13-14 Method to Reduce Current Consumption in Standby Mode .............
Page 24 LIST OF FIGURES (5/8) Figure No. Title Page 17-5 3-Wire Serial I/O Mode Timing ......................18-1 Serial Bus Configuration Example in I C Bus Mode ................. 18-2 Block Diagram of Clocked Serial Interface (I C Bus Mode) .............. 18-3 Format of I C Bus Control Register 0 (IICC0) ...................
Page 25 LIST OF FIGURES (6/8) Figure No. Title Page 22-7 Format of Program Status Word (PSWL) ..................22-8 Context Switching Operation by Execution of a BRKCS Instruction ..........22-9 Return from BRKCS Instruction Software Interrupt (RETCSB Instruction Operation) ...... 22-10 Non-Maskable Interrupt Request Acknowledgment Operations ............22-11 Interrupt Acknowledgment Processing Algorithm ................
Page 26 LIST OF FIGURES (7/8) Figure No. Title Page 23-1 Format of Memory Expansion Mode Register (MM) ................. 23-2 Format of Programmable Wait Control Register 1 (PWC1) .............. µ PD784224 Memory Map ......................... 23-3 µ PD784225 Memory Map ......................... 23-4 23-5 Instruction Fetch from External Memory in External Memory Expansion Mode .......
Page 27 LIST OF FIGURES (8/8) Figure No. Title Page 27-5 Connection of Flashpro III in UART Mode (When Using UART1) ............ Development Tool Configuration ....................... Package Drawing of EV-9200GC-80 (Reference) (Unit: mm) ............Recommended Board Installation Pattern of EV-9200GC-80 (Reference) (Unit: mm) ..... TGK-080SDW Package Drawing (Reference) (Unit: mm) ..............
Page 28 LIST OF TABLES (1/3) Table No. Title Page Types of Pin I/O Circuits and Recommended Connection of Unused Pins ........Vector Table Address ........................Internal RAM Area List ........................Settings of Internal Memory Size Switching Register (IMS) ............. Register Bank Selection ........................Correspondence Between Function Names and Absolute Names ...........
Page 29 LIST OF TABLES (2/3) Table No. Title Page 16-5 3-Wire Serial I/O Configuration ......................17-1 3-Wire Serial I/O Configuration ......................18-1 C Bus Mode Configuration ......................18-2 INTIIC0 Generation Timing and Wait Control ................... 18-3 Definitions of Extended Code Bits ....................18-4 Arbitration Generation States and Interrupt Request Generation Timing .........
Page 30 LIST OF TABLES (3/3) Table No. Title Page Differences Between the µ PD78F4225 and 78F4225Y Mask ROM Versions ........27-1 27-2 Internal Memory Size Switching Register (IMS) Settings ..............27-3 Communication Modes ........................27-4 Major Functions of On-Board Overwrite Mode ................. 28-1 8-Bit Addressing Instructions ......................
Page 31: Chapter 1 Overview
CHAPTER 1 OVERVIEW The µ PD784225 Subseries is a member of the 78K/IV Series, and is an 80-pin general-purpose microcontroller in which the functions of the µ PD784216 Subseries have been limited and to which a ROM correction function has been added.
Page 32 CHAPTER 1 OVERVIEW 78K/IV SERIES LINEUP : Products in mass-production Supports I C bus Supports multimaster I C bus : Products under development µ PD784038Y µ PD784225Y µ PD784038 µ PD784225 Standard models Enhanced internal memory capacity 80-pin, ROM correction added µ...
Page 33: Features
CHAPTER 1 OVERVIEW 1.1 Features • Inherits the peripheral functions of the µ PD780058 Subseries • Minimum instruction execution time • 160 ns (main system clock: @ f = 12.5 MHz operation) • 61 µ s (subsystem clock: @ f = 32.768 kHz operation) •...
Page 34: Ordering Information
CHAPTER 1 OVERVIEW 1.2 Ordering Information (1) µ PD784225 Subseries Part Number Package Internal ROM µ PD784224GC-×××-8BT 80-pin plastic QFP (14 × 14) Mask ROM µ PD784224GK-×××-9EU 80-pin plastic TQFP (fine pitch) (12 × 12) Mask ROM µ PD784225GC-×××-8BT 80-pin plastic QFP (14 × 14) Mask ROM µ...
Page 35: Pin Configuration (Top View)
CHAPTER 1 OVERVIEW 1.3 Pin Configuration (Top View) • 80-pin plastic QFP (14 × 14) µ PD784224GC-×××-8BT, 784225GC-×××-8BT, 784224YGC-×××-8BT, µ PD784225YGC-×××-8BT, 78F4225GC-8BT, 78F4225YGC-8BT • 80-pin plastic TQFP (fine pitch) (12 × 12) µ PD784224GK-×××-9EU, 784225GK-×××-9EU, 784224YGK-×××-9EU, µ PD784225YGK-×××-9EU, 78F4225GK-9EU, 78F4225YGK-9EU P15/ANI5 RESET P127/RTP7...
Page 36 CHAPTER 1 OVERVIEW Cautions 1. Connect the TEST pin directly to a V or pull down. For the pull-down connection, use of Ω Ω a resistor with a resistance between 470 and 10 k is recommended. 2. Connect the V pin directly to V or pull down during normal operation.
Page 37 CHAPTER 1 OVERVIEW A8 to A19: Address bus P130, P131: Port 13 AD0 to AD7: Address/data bus PCL: Programmable clock ANI0 to ANI7: Analog input Read strobe ANO0, ANO1: Analog output RESET: Reset ASCK1, ASCK2: Asynchronous serial clock RTP0 to RTP7: Real-time output port ASTB: Address strobe...
Page 38: Block Diagram
CHAPTER 1 OVERVIEW 1.4 Block Diagram RxD1/SI1 INTP2/NMI Programmable UART/IOE1 TxD1/SO1 interrupt INTP0, INTP1, Baud-rate ASCK1/SCK1 generator INTP3 to INTP5 controller RxD2/SI2 TI00 UART/IOE2 TxD2/SO2 Timer/event TI01 Baud-rate counter (16 bits) ASCK2/SCK2 generator Note 1 SI0/SDA0 Clocked Timer/event serial counter 1 (8 bits) interface Note 1 SCK0/SCL0...
Page 39: Function List
CHAPTER 1 OVERVIEW 1.5 Function List (1/2) µ PD784224 µ PD784225 µ PD78F4225 Product Name µ PD784224Y µ PD784225Y µ PD78F4225Y Item Number of basic instructions (mnemonics) 8 bits × 16 registers × 8 banks or 16 bits × 8 registers × 8 banks (memory mapping) General-purpose registers Minimum instruction execution time •...
Page 40 CHAPTER 1 OVERVIEW (2/2) µ PD784224 µ PD784225 µ PD78F4225 Product Name µ PD784224Y µ PD784225Y µ PD78F4225Y Item Serial interfaces • UART/IOE (3-wire serial I/O): 2 channels (on-chip baud rate generator) Note Note • CSI I (3-wire serial I/O, multimaster-supporting I C bus 1 channel 8-bit resolution ×...
Page 41 CHAPTER 1 OVERVIEW An overview of the timers is shown below. (For details, refer to CHAPTER 8 16-BIT TIMER/EVENT COUNTER, CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1, 2, and CHAPTER 10 8-BIT TIMERS 5, 6.) Name 16-Bit Timer/ 8-Bit Timer/ 8-Bit Timer/ 8-Bit Timer 5 8-Bit Timer 6 Item Event Counter Event Counter 1 Event Counter 2...
Page 42: Differences Between Μ Pd784225 Subseries Products And Μ Pd784225Y Subseries Products
CHAPTER 1 OVERVIEW 1.6 Differences Between µ PD784225 Subseries Products and µ PD784225Y Subseries Products µ PD784224 µ PD784225 µ PD78F4225 Product Name µ PD784224Y µ PD784225Y µ PD78F4225Y Item Internal ROM 96 KB 128 KB 128 KB (mask ROM) (mask ROM) (flash memory) Internal RAM...
Page 43: Chapter 2 Pin Functions
CHAPTER 2 PIN FUNCTIONS 2.1 Pin Function List (1) Port pins (1/2) Pin Name Alternate Function Function INTP0 Port 0 (P0): • 6-bit I/O port INTP1 • Input/output can be specified in 1-bit units. INTP2/NMI • Regardless of whether the input or output mode is specified, use of INTP3 an on-chip pull-up resistor can be specified by software in 1-bit units.
Page 44 CHAPTER 2 PIN FUNCTIONS (1) Port pins (2/2) Pin Name Alternate Function Function P50 to P57 A8 to A15 Port 5 (P5): • 8-bit I/O port • Input/output can be specified in 1-bit units. • For input mode pins, use of on-chip pull-up resistors can be specified for all pins by software.
Page 45 CHAPTER 2 PIN FUNCTIONS (2) Non-port pins (1/2) Pin Name Alternate Function Function TI00 Input External count clock input to 16-bit timer counter TI01 Capture trigger signal input to capture/compare register 00 External count clock input to 8-bit timer counter 1 External count clock input to 8-bit timer counter 2 Output 16-bit timer output (TM0) (also used as 14-bit PWM output)
Page 46 CHAPTER 2 PIN FUNCTIONS (2) Non-port pins (2/2) Pin Name Alternate Function Function Output Clock output (for main system clock, subsystem clock trimming) Buzzer output RTP0 to RTP7 P120 to P127 Real-time output port that outputs data synchronized with the trigger AD0 to AD7 P40 to P47 Lower address/data bus when the memory is externally expanded...
Page 47: Pin Function Description
CHAPTER 2 PIN FUNCTIONS 2.2 Pin Function Description (1) P00 to P05 (Port 0) These pins constitute a 6-bit I/O port. In addition to I/O port pins, they also function as external interrupt request inputs. The following operation modes can be specified in 1-bit unit. (a) Port mode These pins function as a 6-bit I/O port.
Page 48 CHAPTER 2 PIN FUNCTIONS (2) P10 to P17 (Port 1) These pins constitute an 8-bit input-only port. In addition to general-purpose input port pins, they also function as the analog inputs for the A/D converter. On-chip pull-up resistors are not available. (a) Port mode These pins function as an 8-bit input-only port.
Page 49 CHAPTER 2 PIN FUNCTIONS (iv) ASCK1 This is the input pin for the baud rate clock of the asynchronous serial interface. This is the clock output pin. (vi) BUZ This is the buzzer output pin. (4) P30 to P37 (Port 3) These pins constitute an 8-bit I/O port.
Page 50 CHAPTER 2 PIN FUNCTIONS (6) P50 to P57 (Port 5) These pins constitute an 8-bit I/O port. In addition to I/O port pins, they also function as an address bus. LEDs can be directly driven. The following operation modes can be specified in 1-bit units. (a) Port mode These pins function as an 8-bit I/O port.
Page 51 CHAPTER 2 PIN FUNCTIONS SI2, SO2 These are the I/O pins for serial data in the serial interface. (ii) SCK2 This is the I/O pin of the serial clock in the serial interface. (iii) RxD2, TxD2 These are the serial data I/O pins in the asynchronous serial interface. (iv) ASCK2 This is the baud rate clock input pin in the asynchronous serial interface.
Page 52 CHAPTER 2 PIN FUNCTIONS (11) AV REF1 This is the reference power input pin of the D/A converter. If the D/A converter is not used, connect to the V pin. (12) AV This is the analog power supply pin of the A/D converter. Even if the A/D converter is not used, always use this pin at the same potential as the V pin.
Page 53: Pin I/O Circuits And Recommended Connection Of Unused Pins
CHAPTER 2 PIN FUNCTIONS 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins The input/output circuit type of each pin and recommended connection of unused pins are shown in Table 2-1. For the input/output circuit configuration of each type, refer to Figure 2-1. Table 2-1.
Page 54 CHAPTER 2 PIN FUNCTIONS Table 2-1. Types of Pin I/O Circuits and Recommended Connection of Unused Pins (2/2) Pin Name I/O Circuit Type Recommended Connection of Unused Pins P120/RTP0 to P127/RTP7 Input: Independently connect to V via a resistor. Output: Leave open. P130/ANO0, P131/ANO1 12-D RESET...
Page 55 CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuits (1/2) Type 2-G Type 8-L Pull-up P-ch enable Data P-ch IN/OUT N-ch Output disable Schmitt-triggered input with hysteresis characteristics Type 8-M Type 5-H Pull-up Pull-up P-ch P-ch enable enable Data P-ch Data P-ch IN/OUT...
Page 56 CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuits (2/2) Type 12-D Type 10-I Pull-up Data P-ch P-ch enable IN/OUT Output N-ch Data disable P-ch IN/OUT Input P-ch Open drain enable N-ch Output Analog output disable voltage N-ch Type 10-J Type 16 Pull-up Feedback...
Page 57: Chapter 3 Cpu Architecture
CHAPTER 3 CPU ARCHITECTURE 3.1 Memory Space The µ PD784225 can access a 1 MB space. The mapping of the internal data area differs depending on LOCATION instruction (special function registers and internal RAM). The LOCATION instruction must always be executed after releasing reset and cannot be used more than once.
Page 58 CHAPTER 3 CPU ARCHITECTURE (1) When the LOCATION 0H instruction is executed • Internal memory The internal data area and internal ROM area are as follows. Part Number Internal Data Area Internal ROM Area µ PD784224 0F100H to 0FFFFH 00000H to 0F0FFH 10000H to 17FFFH µ...
Page 59 On execution of On execution of LOCATION 0H instruction LOCATION 0FH instruction Special function registers (SFR) Note 1 (256 bytes) General-purpose Internal RAM Note 1 External memory registers (128 bytes) (3,584 bytes) (928 KB) Internal ROM (32,768 bytes) Macro service control word Special function registers (SFR) area (52 bytes) Note 1...
Page 60 On execution of On execution of LOCATION 0H instruction LOCATION 0FH instruction Special function registers (SFR) Note 1 (256 bytes) Note 1 External memory General-purpose Internal RAM (896 KB) registers (128 bytes) (4,352 bytes) Internal ROM (65,536 bytes) Macro service control word Special function registers (SFR) area (52 bytes) Note 1...
Page 61: Internal Rom Area
CHAPTER 3 CPU ARCHITECTURE 3.2 Internal ROM Area The following products in the µ PD784225 Subseries have on-chip ROM that can store the programs and table data. If the internal ROM area and internal data area overlap when the LOCATION 0H instruction is executed, the internal data area becomes the access target.
Page 62: Base Area
CHAPTER 3 CPU ARCHITECTURE 3.3 Base Area The area from 0 to FFFFH becomes the base area. The base area is used for the following. • Reset entry address • Interrupt entry address • Entry address for CALLT instruction • 16-bit immediate addressing mode (instruction address addressing) •...
Page 63: Vector Table Area
CHAPTER 3 CPU ARCHITECTURE 3.3.1 Vector table area The 64-byte area from 00000H to 0003FH is reserved as the vector table area. The program start addresses for branching by interrupt requests and RESET input are stored in the vector table area. If context switching is used by each interrupt, the register bank number of the switch destination is also stored in this area.
Page 64: Callt Instruction Table Area
CHAPTER 3 CPU ARCHITECTURE 3.3.2 CALLT instruction table area The 64 KB area from 00040H to 0007FH can store the subroutine entry addresses for the 1-byte call instruction (CALLT). For a CALLT instruction, this table is referenced and the base area address written in the table is branched to as the subroutine.
Page 65: Internal Data Area
CHAPTER 3 CPU ARCHITECTURE 3.4 Internal Data Area The internal data area consists of the internal RAM area and the special function register area (see Figures 3- 1 and 3-2). The final address in the internal data area can be set to 0FFFFH (when executing the LOCATION 0H instruction) or FFFFFH (when executing the LOCATION 0FH instruction) by the LOCATION instruction.
Page 66: Internal Ram Area
CHAPTER 3 CPU ARCHITECTURE 3.4.1 Internal RAM area The µ PD784225 has an on-chip general-purpose static RAM. This area has the following configuration. Peripheral RAM (PRAM) Internal RAM area Internal high-speed RAM (IRAM) Table 3-2. Internal RAM Area List Internal RAM Internal RAM Area Product Name Peripheral RAM: PRAM...
Page 67 CHAPTER 3 CPU ARCHITECTURE Figure 3-3 is the internal RAM memory map. Figure 3-3. Internal RAM Memory Map 00FEFFH General-purpose register area 00FE80H Available range for short direct addressing 1 00FE39H Macro service control word area 00FE06H Internal high-speed RAM 00FE00H 00FDFFH Available range for short...
Page 68 CHAPTER 3 CPU ARCHITECTURE (1) Internal high-speed RAM (IRAM) The internal high-speed RAM can be accessed at high speed. FD20H to FEFFH can use the short direct addressing mode for high-speed access. The two short direct addressing modes are short direct addressing 1 and short direct addressing 2 that are based on the address of the target.
Page 69: Special Function Register (Sfr) Area
CHAPTER 3 CPU ARCHITECTURE 3.4.2 Special function register (SFR) area The special function register (SFR) of the on-chip peripheral hardware is mapped to the area from 0FF00H to 0FFFFH (Refer to Figures 3-1 and 3-2). The area from 0FFD0H to 0FFDFH is mapped as the external SFR area. Peripheral I/O externally connected in the external memory expansion mode (set by the memory expansion mode register (MM)) can be accessed.
Page 70: Pd78F4225 Memory Mapping
CHAPTER 3 CPU ARCHITECTURE 3.6 µ PD78F4225 Memory Mapping The µ PD78F4225 has a 128 KB flash memory and 4,352-byte internal RAM. The µ PD78F4225 has a function (memory size switching function) so that a part of the internal memory is not used by the software.
Page 71: Control Registers
CHAPTER 3 CPU ARCHITECTURE 3.7 Control Registers The control registers are the program counter (PC), program status word (PSW), and stack pointer (SP). 3.7.1 Program counter (PC) This is a 20-bit binary counter that saves address information about the program to be executed next (see Figure 3-5).
Page 72 CHAPTER 3 CPU ARCHITECTURE Figure 3-6. Format of Program Status Word (PSW) Symbol PSWH RBS2 RBS1 RBS0 — — — — PSWL Each flag is described below. (1) Carry flag (CY) This is the flag that stores the carry or borrow of an operation result. When a shift rotate instruction is executed, the shifted out value is stored.
Page 73 CHAPTER 3 CPU ARCHITECTURE Example The action of the overflow flag when an 8-bit addition instruction is executed is described next. When 78H (+120) and 69H (+105) are added, the operation result becomes E1H (+225). Since the upper limit of two’s complement is exceeded, the P/V flag is set to 1. In a two’s complement expression, E1H becomes –31.
Page 74 CHAPTER 3 CPU ARCHITECTURE (5) Register set selection flag (RSS) This flag sets the general-purpose registers that function as X, A, C, and B and the general-purpose register pairs (16 bits) that function as AX and BC. This flag is used to maintain compatibility with the 78K/III Series. Always set this flag to 0 except when using a 78K/III Series program.
Page 75: Using The Rss Bit
CHAPTER 3 CPU ARCHITECTURE 3.7.3 Using the RSS bit Basically, always use with the RSS bit fixed at 0. The following descriptions discuss using a 78K/III Series program and a program that sets the RSS bit to 1. Reading is not necessary if the RSS bit is fixed at 0. The RSS bit enables the functions in A (R1), X (R0), B (R3), C (R2), AX (RP0), and BC (RP1) to also be used in registers R4 to R7 (RP2, RP3).
Page 76 The registers used in other cases always become the same registers regardless of the contents of the RSS bit. For registers A, X, B, C, AX, and BC in NEC assembler RA78K4, instruction code is generated for any register described by name or for registers set by an RSS quasi directive in the assembler.
Page 77 CHAPTER 3 CPU ARCHITECTURE • If A, X, B, C, AX, or BC is described in an instruction that specifies r, r’, rp, or rp’ in the operand column, the A, X, B, C, AX, or BC instruction code generates the instruction code that specifies the following registers based on the operand of the RSS pseudo instruction in RA78K4.
Page 78: Stack Pointer (Sp)
CHAPTER 3 CPU ARCHITECTURE 3.7.4 Stack pointer (SP) The 24-bit register saves the starting address of the stack (LIFO: 00000H to FFFFFFH) (refer to Figure 3-7). The stack is used for addressing during subroutine processing or interrupt servicing. Always set the higher four bits to zero.
Page 79 CHAPTER 3 CPU ARCHITECTURE Figure 3-8. Data Saved to the Stack PUSH sfr instruction PUSH sfrp instruction Stack Stack ➡ ➡ ↓ ↓ SP-1 SP-1 Higher byte ↓ SP ← SP-1 SP-2 Lower byte SP ← SP-2 PUSH PSW instruction PUSH rg instruction Stack Stack...
Page 80 CHAPTER 3 CPU ARCHITECTURE Figure 3-9. Data Restored from the Stack POP sfr instruction POP sfrp instruction Stack Stack SP ← SP+2 SP ← SP+1 SP+1 SP+1 Higher byte ↑ ↑ ➡ ➡ Lower byte POP PSW instruction POP rg instruction Stack Stack SP ←...
Page 81 CHAPTER 3 CPU ARCHITECTURE Cautions 1. In stack addressing, the entire 1 MB space can be accessed, but the stack cannot be guaranteed in the SFR area and internal ROM area. 2. The stack pointer (SP) becomes undefined when RESET is input. In addition, even when SP is in the undefined state, non-maskable interrupts can be acknowledged.
Page 82: General-Purpose Registers
CHAPTER 3 CPU ARCHITECTURE 3.8 General-Purpose Registers 3.8.1 Structure There are sixteen 8-bit general-purpose registers. In addition, two 8-bit general-purpose registers can be combined and used as a 16-bit general-purpose register. Furthermore, four of the 16-bit general-purpose registers are combined with an 8-bit register for address expansion and used as a 24-bit address specification register.
Page 83 CHAPTER 3 CPU ARCHITECTURE Figure 3-11. General-Purpose Register Addresses 8-bit processing 8-bit processing (Note) FEFFH RBNK0 H (R15) L (R14) HL (RP7) (FH) (EH) (EH) RBNK1 D (R13) E (R12) DE (RP6) (DH) (CH) (CH) RBNK2 UP (R5) (BH) (AH) (AH) RBNK3 VP (R4)
Page 84: Functions
CHAPTER 3 CPU ARCHITECTURE 3.8.2 Functions In addition to being manipulatable in 8-bit units, general-purpose registers can be a pair of two 8-bit registers and be manipulated in 16-bit units. Also four of the 16-bit registers can be combined with the 8-bit register for address expansion and manipulated in 24-bit units.
Page 85 CHAPTER 3 CPU ARCHITECTURE C (R2): • This register functions as a loop counter and can be used by the DBNZ instruction. • This register can store the offset in based indexed addressing. • This register is used as the counter in string and SACW instructions. •...
Page 86 CHAPTER 3 CPU ARCHITECTURE WHL (RG7): • This register primarily performs 24-bit data transfers and operation processing. • This register functions as a pointer and specifies the base address during register indirect addressing or based addressing. • This functions as a pointer in string and SACW instructions. In addition to its function name (X, A, C, B, E, D, L, H, AX, BC, VP, UP, DE, HL, VVP, UUP, TDE, WHL) that emphasizes its unique function, each register can be described by its absolute name (R0 to R15, RP0 to RP7, RG4 to RG7).
Page 87: Special Function Registers (Sfrs)
Table 3-6 shows the list of special function registers (SFRs). The meanings of the items are described next. • Symbol ......This symbol indicates the on-chip SFR. In NEC assembler RA78K4, this is a reserved word. In C compiler CC78K4, it can be used as an sfr variable by a #pragma sfr directive.
Page 88 CHAPTER 3 CPU ARCHITECTURE Table 3-6. Special Function Register (SFR) List (1/4) Bit Manipulation Unit Note 1 Address Special Function Register (SFR) Name Symbol After Reset 1 Bit 8 Bits 16 Bits √ √ Note 2 0FF00H Port 0 — √...
Page 89 CHAPTER 3 CPU ARCHITECTURE Table 3-6. Special Function Register (SFR) List (2/4) Bit Manipulation Unit Note 1 Address Special Function Register (SFR) Name Symbol After Reset 1 Bit 8 Bits 16 Bits √ √ 0FF3CH Pull-up resistor option register 12 PU12 —...
Page 90 CHAPTER 3 CPU ARCHITECTURE Table 3-6. Special Function Register (SFR) List (3/4) Bit Manipulation Unit Note 1 Address Special Function Register (SFR) Name Symbol After Reset 1 Bit 8 Bits 16 Bits √ √ 0FF84H D/A conversion value setting register 0 DACS0 —...
Page 91 CHAPTER 3 CPU ARCHITECTURE Table 3-6. Special Function Register (SFR) List (4/4) Bit Manipulation Unit Note 1 Address Special Function Register (SFR) Name Symbol After Reset 1 Bit 8 Bits 16 Bits √ 0FFC0H Standby control register STBC — — √...
Page 92: Cautions
CHAPTER 3 CPU ARCHITECTURE 3.10 Cautions (1) Program fetches are not possible from the internal high-speed RAM space (when executing the LOCATION 0H instruction: 0FD00H to 0FEFFH, when executing the LOCATION 0FH instruction: FFD00H to FFEFFH) (2) Special function register (SFR) Note Do not access an address that is allocated to an SFR in the area from 0FF00H to 0FFFFH .
Page 93: Chapter 4 Clock Generator
CHAPTER 4 CLOCK GENERATOR 4.1 Functions The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following two types of system clock oscillators are available. (1) Main system clock oscillator This circuit oscillates at frequencies of 2 to 12.5 kHz. Oscillation can be stopped by setting the standby control register (STBC) to STOP mode (bit 1 (STP) = 1, bit 0 (HLT) = 0) or to stop main system clock (bit 2 of STBC (MCK) = 1) after switching to the subsystem clock.
Page 94 CHAPTER 4 CLOCK GENERATOR Figure 4-1. Block Diagram of Clock Generator Subsystem Watch timer, clock clock output function oscillator Prescaler Main system IDLE Clock to Prescaler clock controller peripheral hardware oscillator Divider STOP or bit 2 of STBC STOP, (MCK) = 1 when IDLE HALT selecting subsystem...
Page 95: Control Registers
Because the operand error interrupt occurs only in the case of an inadvertent program loop (if MOV STBC or #byte is described, only the correct dedicated instruction is generated in NEC’s RA78K4 assembler), initialize the system for the program that processes an operand error interrupt.
Page 96 CHAPTER 4 CLOCK GENERATOR Figure 4-2. Format of Standby Control Register (STBC) Address: 0FFC0H After reset: 30H Symbol STBC Subsystem clock oscillation control Use oscillator (Internal feedback resistor is used.) Stop oscillator (Internal feedback resistor is not used.) CPU clock selection (Recommendation) —...
Page 97 CHAPTER 4 CLOCK GENERATOR Example MOV STBC #byte • • • 3. When CK2 = 0, the oscillation of the main system clock does not stop even if MCK is set to 1 (Refer to 4.5.1 Main system clock operations). Remarks 1.
Page 98 CHAPTER 4 CLOCK GENERATOR (3) Clock status register (PCS) This register is a read-only 8-bit register that indicates the CPU clock operation status. By reading bit 2 and bits 4 to 7 of PCS, the relevant bit of the standby control register (STBC) can be read. PCS is set by a 1-bit or 8-bit memory manipulation instruction.
Page 99 CHAPTER 4 CLOCK GENERATOR (4) Oscillation stabilization time specification register (OSTS) This register specifies the operation of the oscillator. Either a crystal/ceramic resonator or external clock is set to the EXTC bit in OSTS as the clock used. The STOP mode can be set even during external clock input only when the EXTC bit is set 1.
Page 100: System Clock Oscillator
CHAPTER 4 CLOCK GENERATOR 4.4 System Clock Oscillator 4.4.1 Main system clock oscillator The main system clock oscillator oscillates with a crystal resonator or a ceramic resonator (standard: 12.5 MHz) connected to the X1 and X2 pins. External clocks can be input to the main system clock oscillator. In this case, input a clock signal to the X1 pin and an antiphase clock signal to the X2 pin.
Page 101 CHAPTER 4 CLOCK GENERATOR 4.4.2 Subsystem clock oscillator The subsystem clock oscillator oscillates with a crystal resonator (standard: 32.768 kHz) connected to the XT1 and XT2 pins. External clocks can be input to the main system clock oscillator. In this case, input a clock signal to the XT1 pin and an antiphase clock signal to the XT2 pin.
Page 102 CHAPTER 4 CLOCK GENERATOR Figure 4-8. Incorrect Examples of Resonator Connection (1/2) Wiring of connection (b) Signal lines intersect circuits is too long each other PORTn (n = 0 to 10, 12, 13) Remark When using a subsystem clock, replace X1 and X2 with XT1 and XT2, respectively. Further, insert resistors in series on the side of XT2.
Page 103 CHAPTER 4 CLOCK GENERATOR Figure 4-8. Incorrect Examples of Resonator Connection (2/2) (c) Fluctuating high current is too near a (d) Current flows through the ground line signal line of the oscillator (potential at points A, B, and C fluctuate) High current High...
Page 104 CHAPTER 4 CLOCK GENERATOR 4.4.3 Frequency divider The frequency divider divides the main system clock oscillator output (f ) and generates various clocks. 4.4.4 When no subsystem clocks are used If it is not necessary to use subsystem clocks for low power consumption operations and clock operations, connect the XT1 and XT2 pins as follows.
Page 105 CHAPTER 4 CLOCK GENERATOR 4.5 Clock Generator Operations The clock generator generates the following types of clocks and controls the CPU operation mode including the standby mode. • Main system clock (f • Subsystem clock (f • CPU clock (f •...
Page 106 CHAPTER 4 CLOCK GENERATOR 4.5.1 Main system clock operations During operation with the main system clock (with bit 6 (CK2) of the standby control register (STBC) set to 0), the following operations are carried out. (a) Because the operation guarantee instruction execution speed depends on the power supply voltage, the instruction execution time can be changed by setting bits 4 to 6 (CK0 to CK2) of the STBC.
Page 107 CHAPTER 4 CLOCK GENERATOR Figure 4-9. Main System Clock Stop Function (2/2) (c) Operation when CK2 is set after setting MCK during main system clock operation Main system clock oscillation Subsystem clock oscillation CPU clock 4.5.2 Subsystem clock operations When operated with the subsystem clock (with bit 6 (CK2) of the standby control register (STBC) set to 1), the following operations are carried out.
Page 108 CHAPTER 4 CLOCK GENERATOR This section describes the switching procedure between the system clock and the CPU clock. Figure 4-10. System Clock and CPU Clock Switching RESET Interrupt request signal System clock CPU clock Minimum Maximum speed Subsystem clock Highest-speed speed operation operation...
Page 109 CHAPTER 5 PORT FUNCTIONS 5.1 Digital I/O Ports The ports shown in Figure 5-1, which enable a variety of controls, are provided. The function of each port is described in Table 5-1. On-chip pull-up resistors can be specified for ports 0, 2 to 7, and 12 by software during input. Figure 5-1.
Page 110 CHAPTER 5 PORT FUNCTIONS Table 5-1. Port Functions Port Pin Name Function Specification of Software Pull-up Resistor Port 0 P00 to P05 • Input or output can be specified in 1-bit units Specifiable in 1-bit units Port 1 P10 to P17 •...
Page 111 CHAPTER 5 PORT FUNCTIONS 5.2 Port Configuration Ports include the following hardware. Table 5-2. Port Configuration Item Configuration Control registers Port mode register (PMm: m = 0, 2 to 7, 12, 13) Pull-up resistor option register (PUO, PUm: m = 0, 2, 3, 7, 12) Ports Total: 67 (input: 8, input/output: 59) Pull-up resistors...
Page 112 CHAPTER 5 PORT FUNCTIONS Figure 5-2. Block Diagram of P00 to P05 PU00 to PU05 P-ch Alternate function Selector PORT P00/INTP0, Output latch P01/INTP1, (P00 to P05) P02/INTP2/NMI to P05/INTP5 PM00 to PM05 PU: Pull-up resistor option register PM: Port mode register RD: Port 0 read signal WR: Port 0 write signal User’s Manual U12697EJ3V0UM...
Page 113 CHAPTER 5 PORT FUNCTIONS 5.2.2 Port 1 This is an 8-bit input-only port with no on-chip pull-up resistor. Port 1 supports A/D converter analog input as an alternate function. Figure 5-3 shows a block diagram of port 1. Figure 5-3. Block Diagram of P10 to P17 Alternate function P10/ANI0 to...
Page 114 CHAPTER 5 PORT FUNCTIONS 5.2.3 Port 2 Port 2 is an 8-bit I/O port with output latch. P20 to P27 pins can specify the input mode/output mode in 1-bit units with the port 2 mode register. A pull-up resistor can be connected via pull-up resistor option register 2, regardless of whether the input mode or output mode is specified.
Page 115 CHAPTER 5 PORT FUNCTIONS Figure 5-5. Block Diagram of P21, P23 to P24, and P26 PU21, PU23, PU24, P-ch PU26 Selector PORT P21/SO1/T Output Latch P23/PCL, (P21, P23, P24, P26) P24/BUZ, P26/SO0 PM21, PM23, PM24, PM26 Alternate function PU: Pull-up resistor option register PM: Port mode register RD: Port 2 read signal WR: Port 2 write signal...
Page 116 CHAPTER 5 PORT FUNCTIONS Figure 5-6. Block Diagram of P25 PU25 P-ch Alternate function Selector PF25 PORT Output latch P-ch (P25) Note P25/SI0/SDA0 N-ch PM25 The SDA0 pin applies only to the µ PD784225Y Subseries. Note PU: Pull-up resistor option register PF: Port function control register PM: Port mode register RD: Port 2 read signal...
Page 117 CHAPTER 5 PORT FUNCTIONS Figure 5-7. Block Diagram of P27 P-ch PU27 Alternate function Selector PF27 PORT Output latch P-ch (P27) Note P27/SCK0/SCL0 N-ch PM27 Alternate function The SCL0 pin applies only to the µ PD784225Y Subseries. Note PU: Pull-up resistor option register PF: Port function control register PM: Port mode register RD: Port 2 read signal...
Page 118 CHAPTER 5 PORT FUNCTIONS 5.2.4 Port 3 Port 3 is an 8-bit I/O port with output latch. The P30 to P37 pins can specify the input mode/output mode in 1- bit units with the port 3 mode register. A pull-up resistor can be connected via pull-up resistor option register 3, regardless of whether the input mode or output mode is specified.
Page 119 CHAPTER 5 PORT FUNCTIONS Figure 5-9. Block Diagram of P33 to P36 PU33 to PU36 P-ch Alternate function Selector PORT P33/TI1, Output latch P34/TI2, (P33 to P36) P35/TI00, P36/TI01 PM33 to PM36 PU: Pull-up resistor option register PM: Port mode register RD: Port 3 read signal WR: Port 3 write signal User’s Manual U12697EJ3V0UM...
Page 120 CHAPTER 5 PORT FUNCTIONS 5.2.5 Port 4 Port 4 is an 8-bit I/O port with output latch. The P40 to P47 pins can specify the input mode/output mode in 1- bit units with the port 4 mode register. When the P40 to P47 pins are used as input ports, a pull-up resistor can be connected in 8-bit units with bit 4 (PUO4) of the pull-up resistor option register.
Page 121 CHAPTER 5 PORT FUNCTIONS Figure 5-10. Block Diagram of P40 to P47 PUO4 MM0 to MM3 PM40 to P47 P40/AD0 to P47/AD7 Output latch (P40 to P47) External access data PUO: Pull-up resistor option register Port mode register Port 4 read signal Port 4 write signal User’s Manual U12697EJ3V0UM...
Page 122 CHAPTER 5 PORT FUNCTIONS 5.2.6 Port 5 Port 5 is an 8-bit I/O port with output latch. The P50 to P57 pins can specify the input mode/output mode in 1- bit units with the port 5 mode register. When the P50 to P57 pins are used as input ports, a pull-up resistor can be connected in 8-bit units with bit 5 (PUO5) of the pull-up resistor option register.
Page 123 CHAPTER 5 PORT FUNCTIONS Figure 5-11. Block Diagram of P50 to P57 PUO5 MM0 to MM3 PM50 to PM75 P50/A8 to P57/A15 Output latch (P50 to P57) PUO: Pull-up resistor option register Port mode register Port 5 read signal Port 5 write signal MM0 to MM3: Bits 0 to 3 of the memory expansion mode register (MM) User’s Manual U12697EJ3V0UM...
Page 124 CHAPTER 5 PORT FUNCTIONS 5.2.7 Port 6 Port 6 is an 8-bit I/O port with output latch. The P60 to P67 pins can specify the input mode/output mode in 1- bit units with the port 6 mode register. When pins P60 to P67 are used as input ports, a pull-up resistor can be connected in 8-bit units with bit 6 (PUO6) of the pull-up resistor option register.
Page 125 CHAPTER 5 PORT FUNCTIONS Figure 5-12. Block Diagram of P60 to P63 PUO6 MM0 to MM3 PM60 to PM63 P60/A16 to P63/A19 Output latch (P60 to P63) PUO: Pull-up resistor option register Port mode register Port 6 read signal Port 6 write signal MM0 to MM3: Bits 0 to 3 of the memory expansion mode register (MM) User’s Manual U12697EJ3V0UM...
Page 126 CHAPTER 5 PORT FUNCTIONS Figure 5-13. Block Diagram of P64, P65, and P67 PUO6 PM64, PM65, PM67 External expansion mode Timing signal for external expansion P64/RD, P65/WR, P67/ASTB Output latch (P64, P65, P67) PUO: Pull-up resistor option register Port mode register Port 6 read signal Port 6 write signal User’s Manual U12697EJ3V0UM...
Page 127 CHAPTER 5 PORT FUNCTIONS Figure 5-14. Block Diagram of P66 Pull-up resistor option register PUO6 Port 6 mode register PM66 External wait mode Output latch P66/WAIT (P66) Wait input PUO: Pull-up resistor option register Port mode register Port 6 read signal Port 6 write signal User’s Manual U12697EJ3V0UM...
Page 128 CHAPTER 5 PORT FUNCTIONS 5.2.8 Port 7 This is a 3-bit I/O port with output latch. Input mode/output mode can be specified in 1-bit units with the port 7 mode register. A pull-up resistor can be connected via pull-up resistor option register 7, regardless of whether the input mode or output mode is specified.
Page 129 CHAPTER 5 PORT FUNCTIONS Figure 5-16. Block Diagram of P71 P-ch PU71 Selector PORT Output latch (P71) P71/SO2/T PM71 Alternate function PU: Pull-up resistor option register PM: Port mode register RD: Port 7 read signal WR: Port 7 write signal User’s Manual U12697EJ3V0UM...
Page 130 CHAPTER 5 PORT FUNCTIONS Figure 5-17. Block Diagram of P72 PU72 P-ch Alternate function Selector PORT P72/SCK2/ Output latch ASCK2 (P72) PM72 PU: Pull-up resistor option register PM: Port mode register RD: Port 7 read signal WR: Port 7 write signal User’s Manual U12697EJ3V0UM...
Page 131 CHAPTER 5 PORT FUNCTIONS 5.2.9 Port 12 This is an 8-bit I/O port with output latch. Input mode/output mode can be specified in 1-bit units with the port 12 mode register. A pull-up resistor can be connected via pull-up resistor option register 12, regardless of whether the input mode or output mode is specified.
Page 132 CHAPTER 5 PORT FUNCTIONS 5.2.10 Port 13 This is a 2-bit I/O port with output latch. The input mode/output mode can be specified in 1-bit units with the port 13 mode register. Port 13 does not include a pull-up resistor. Port 13 supports D/A converter analog output as an alternate function.
Page 133 CHAPTER 5 PORT FUNCTIONS 5.3 Control Registers The following three types of registers control the ports. • Port mode registers (PM0, PM2 to PM7, PM12, PM13) • Pull-up resistor option registers (PU0, PU2, PU3, PU7, PU12, PUO) Note • Port function control register 2 (PF2) Applies only to the µ...
Page 134 CHAPTER 5 PORT FUNCTIONS Table 5-3. Port Mode Register and Output Latch Settings When Using Alternate Functions Alternate Function Alternate Function Pin Name PM×× P×× Pin Name PM×× P×× Name Name × × P00, P01 INTP0, INTP1 Input P35, P36 TI00, TI01 Input ×...
Page 135 CHAPTER 5 PORT FUNCTIONS Figure 5-20. Format of Port Mode Register Address: 0FF20H, 0FF22H to 0FF27H, 0FF2CH, 0FF2DH After reset: FFH Symbol PM05 PM04 PM03 PM02 PM01 PM00 PM27 PM26 PM25 PM24 PM23 PM22 PM21 PM20 PM37 PM36 PM35 PM34 PM33 PM32 PM31...
Page 136 CHAPTER 5 PORT FUNCTIONS (2) Pull-up resistor option registers (PU0, PU2, PU3, PU7, PU12, PUO) These registers are used to set whether to use an on-chip pull-up resistor at each port or not in 1-bit or 8-bit units. PUn (n = 0, 2, 3, 7, 12) can specify the pull-up resistor connection of each port pin. PUO can specify the pull- up resistor connection of ports 4, 5, and 6.
Page 137 CHAPTER 5 PORT FUNCTIONS (3) Port function control register 2 (PF2) This register specifies N-ch open drain for pins P25 and P27. PF2 is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets PF2 to 00H. Caution Only the µ PD784225Y Subseries incorporates PF2. When using the I C bus mode (serial interface), make sure to specify N-ch open drain for the P25 and P27 pins.
Page 138 CHAPTER 5 PORT FUNCTIONS 5.4 Operations Port operations differ depending on whether the input or output mode is set, as shown below. 5.4.1 Writing to I/O port (1) Output mode A value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin.
Page 139 CHAPTER 6 REAL-TIME OUTPUT FUNCTIONS 6.1 Functions The real-time output function transfers preset data in the real-time output buffer register to the output latch by hardware synchronized to the generation of a timer interrupt or an external interrupt and outputs it off the chip. Also, the pins for output off the chip are called the real-time output port.
Page 140 CHAPTER 6 REAL-TIME OUTPUT FUNCTIONS Figure 6-1. Block Diagram of Real-Time Output Port Internal bus Real-time output port control register (RTPC) RTPOE BYTE EXTR INTP2 Higher 4 bits of Lower 4 bits of Output trigger real-time output real-time output INTTM1 controller buffer register buffer register...
Page 141 CHAPTER 6 REAL-TIME OUTPUT FUNCTIONS • Real-time output buffer registers (RTBL, RTBH) These 4-bit registers save the output data beforehand. RTBL and RTBH are mapped to independent addresses in the special function register (SFR) as shown in Figure 6-2. When the 4 bits × 2 channels operation mode is specified, RTBL and RTBH can be independently set with data. In addition, if the addresses of both RTBL and RTBH are specified, the data in both registers can be read in a batch.
Page 142 CHAPTER 6 REAL-TIME OUTPUT FUNCTIONS 6.3 Control Registers The real-time output port is controlled by the following two registers. • Real-time output port mode register (RTPM) • Real-time output port control register (RTPC) (1) Real-time output port mode register (RTPM) This register sets the real-time output port mode and port mode selections in 1-bit units.
Page 143 CHAPTER 6 REAL-TIME OUTPUT FUNCTIONS (2) Real-time output port control register (RTPC) This register sets the operation mode and output trigger of the real-time output port. Table 6-3 shows the relationships between the operation modes and output triggers of the real-time output port. RTPC is set by a 1-bit or 8-bit memory manipulation instruction.
Page 144 CHAPTER 6 REAL-TIME OUTPUT FUNCTIONS 6.4 Operation When real-time output is enabled by bit 7 (RTPOE) = 1 in the real-time output port control register, data in the real-time output buffer register (RTBH, RTBL) are transferred to the output latch synchronized to the generation of Note the selected transfer trigger (set by EXTR and BYTE ).
Page 145 CHAPTER 6 REAL-TIME OUTPUT FUNCTIONS 6.5 Using This Function (1) Disabling the real-time output operation Set bit 7 (RTPOE) = 0 in the real-time output port control register (RTPC). (2) Initial settings • Set 0 in the output latch (since the output latch and real-time output are configured as a logical AND). •...
Page 146 CHAPTER 7 TIMER OVERVIEW There are one on-chip 16-bit timer/event counter, two on-chip 8-bit timer/event counters, and two 8-bit timers. Since a total of six interrupt requests is supported, these timer/event counters can function as six units of timer/ event counters. Table 7-1.
Page 147 CHAPTER 7 TIMER OVERVIEW Figure 7-1. Block Diagram of Timer (1/2) 16-bit timer/event counter Clear 16-bit timer counter 0 (TM0) INTTM3 Edge detector INTTM00 TI01 16-bit capture/compare register 00 (CR00) INTTM01 16-bit capture/compare register 01 TI00 Edge detector (CR01) 8-bit timer/event counter 1 Clear 8-bit timer counter 1 Output...
Page 148 CHAPTER 7 TIMER OVERVIEW Figure 7-1. Block Diagram of Timer (2/2) 8-bit timer 5 Clear 8-bit timer counter 5 (TM5) 8-bit compare register 50 INTTM5 (CR50) INTTM6 8-bit timer 6 Clear 8-bit timer counter 6 (TM6) 8-bit compare register 60 INTTM6 (CR60) User’s Manual U12697EJ3V0UM...
Page 149 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.1 Function The 16-bit timer/event counter has the following functions. • Interval timer • PPG output • Pulse width measurement • External event counter • Square wave output • One-shot pulse output (1) Interval timer When the 16-bit timer/event counter is used as an interval timer, it generates an interrupt request at predetermined time intervals.
Page 150 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.2 Configuration The 16-bit timer/event counter includes the following hardware. Table 8-1. Configuration of 16-Bit Timer/Event Counter Item Configuration 16 bits × 1 (TM0) Timer counter 16-bit capture/compare register: 16 bits × 2 (CR00, CR01) Register Timer output 1 (TO0)
Page 151 CHAPTER 8 16-BIT TIMER/EVENT COUNTER (1) 16-bit timer counter 0 (TM0) TM0 is a 16-bit read-only register that counts count pulses. The counter is incremented in synchronization with the rising edge of an input clock. If the count value is read during operation, input of the count clock is temporarily stopped, and the count value at that point is read.
Page 152 CHAPTER 8 16-BIT TIMER/EVENT COUNTER (2) Capture/compare register 00 (CR00) CR00 is a 16-bit register that functions as a capture register and as a compare register. Whether this register functions as a capture or compare register is specified by using bit 0 (CRC00) of capture/compare control register •...
Page 153 CHAPTER 8 16-BIT TIMER/EVENT COUNTER (3) Capture/compare register 01 (CR01) This is a 16-bit register that can be used as a capture register and a compare register. Whether it is used as a capture register or compare register is specified by bit 2 (CRC02) of capture/compare control register 0. •...
Page 154 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.3 Control Registers The following four types of registers control the 16-bit timer/event counter. • 16-bit timer mode control register 0 (TMC0) • Capture/compare control register 0 (CRC0) • 16-bit timer output control register 0 (TOC0) •...
Page 155 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-2. Format of 16-Bit Timer Mode Control Register 0 (TMC0) Address: 0FF18H After reset: 00H R/W Symbol TMC0 TMC03 TMC02 TMC01 OVF0 Selection of Selection of TO0 Generation of TMC03 TMC02 TMC01 operation mode/ output timing interrupt clear mode...
Page 156 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Cautions 1. Before changing the clear mode and TO0 output timing, be sure to stop the timer operation (reset TMC02 and TMC03 to 0, 0). The valid edge of the TI00 pin is selected by using prescaler mode register 0 (PRM0). 2.
Page 157 CHAPTER 8 16-BIT TIMER/EVENT COUNTER (2) Capture/compare control register 0 (CRC0) This register controls the operation of capture/compare registers (CR00 and CR01). CRC0 is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets CRC0 to 00H. Figure 8-3. Format of Capture/Compare Control Register 0 (CRC0) Address: FF16H After reset: 04H R/W Symbol CRC0...
Page 158 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-4. Format of 16-Bit Timer Output Control Register 0 (TOC0) Address: 0FF1AH After reset: 00H R/W Symbol TOC0 OSPT OSPE TOC04 LVS0 LVR0 TOC01 TOE0 OSPT Output trigger control of one-shot pulse by software One-shot pulse output disabled One-shot pulse output enabled OSPE...
Page 159 CHAPTER 8 16-BIT TIMER/EVENT COUNTER (4) Prescaler mode register 0 (PRM0) This register selects a count clock of the 16-bit timer/event counter and the valid edge of TI00, TI01 input. PRM0 is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets PRM0 to 00H.
Page 160 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.4 Operation 8.4.1 Operation as interval timer (16 bits) The 16-bit timer/counter operates as an interval timer when 16-bit timer mode control register 0 (TMC0) and capture/compare control register 0 (CRC0) are set as shown in Figure 8-6. In this case, the 16-bit timer/event counter repeatedly generates an interrupt at the time interval specified by the count value set in advance to 16-bit capture/compare register 00 (CR00).
Page 161 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-7. Configuration of Interval Timer 16-bit capture/compare register 00 (CR00) INTTM00 INTTM3 16-bit timer counter 0 (TM0) OVF0 TI00/P35 Clear circuit Figure 8-8. Timing of Interval Timer Operation Count clock TM0 count value 0000 0001 0000 0001 0000 0001...
Page 162 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.4.2 PPG output operation The 16-bit timer/event counter can be used for PPG (Programmable Pulse Generator) output by setting 16-bit timer mode control register 0 (TMC0) and capture/compare control register 0 (CRC0) as shown in Figure 8-9. The PPG output function outputs a rectangular wave with a cycle specified by the count value set in advance to 16-bit capture/compare register 00 (CR00) and a pulse width specified by the count value set in advance to 16-bit capture/compare register 01 (CR01).
Page 163 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.4.3 Pulse width measurement 16-bit timer counter 0 (TM0) can be used to measure the pulse widths of the signals input to the TI00/P35 and TI01/P36 pins. Measurement can be carried out with TM0 used as a free-running counter or by restarting the timer in synchronization with the edge of the signal input to the TI00/P35 pin.
Page 164 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-11. Configuration for Pulse Width Measurement with Free-Running Counter 16-bit timer counter 0 (TM0) OVF0 INTTM3 16-bit capture/compare register 01 TI00/P35 (CR01) INTTM01 Internal bus Figure 8-12. Timing of Pulse Width Measurement with Free-Running Counter and One Capture Register (with Both Edges Specified) Count clock TM0 count value...
Page 165 CHAPTER 8 16-BIT TIMER/EVENT COUNTER (2) Measurement of two pulse widths with free-running counter The pulse widths of the two signals respectively input to the TI00/P35 and TI01/P36 pins can be measured when 16-bit timer counter 0 (TM0) is used as a free-running counter (refer to Figure 8-13). When the edge specified by bits 4 and 5 (ES00 and ES01) of prescaler mode register 0 (PRM0) is input to the TI00/P35 pin, the value of the TM0 is loaded to 16-bit capture/compare register 01 (CR01) and an external interrupt request signal (INTTM01) is set.
Page 166 CHAPTER 8 16-BIT TIMER/EVENT COUNTER • Capture operation (free-running mode) The following figure illustrates the operation of the capture register when the capture trigger is input. Figure 8-14. CR01 Capture Operation with Rising Edge Specified Count clock n – 3 n –...
Page 167 CHAPTER 8 16-BIT TIMER/EVENT COUNTER (3) Pulse width measurement with free-running counter and two capture registers When 16-bit timer counter 0 (TM0) is used as a free-running counter (refer to Figure 8-16), the pulse width of the signal input to the TI00/P35 pin can be measured. When the edge specified by bits 4 and 5 (ES00 and ES01) of prescaler mode register 0 (PRM0) is input to the TI00/P35 pin, the value of TM0 is loaded to 16-bit capture/compare register 01 (CR01), and an external interrupt request signal (INTTM01) is set.
Page 168 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-17. Timing of Pulse Width Measurement with Free-Running Counter and Two Capture Registers (with Rising Edge Specified) Count clock TM0 count value 0000 0001 FFFF 0000 TI00 pin input Value loaded to CR01 Value loaded to CR00 INTTM01 OVF0...
Page 169 CHAPTER 8 16-BIT TIMER/EVENT COUNTER (4) Pulse width measurement by restarting When the valid edge of the TI00/P35 pin is detected, the pulse width of the signal input to the TI00/P35 pin can be measured by clearing 16-bit timer counter 0 (TM0) once and then resuming counting after loading the count value of TM0 to 16-bit capture/compare register 01 (CR01) (Refer to Figure 8-18).
Page 170 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-19. Timing of Pulse Width Measurement by Restarting (with Rising Edge Specified) Count clock TM0 count value 0000 0001 0000 0001 0000 0001 TI00 pin input Value loaded to CR01 Value loaded to CR00 INTTM01 D1 ×...
Page 171 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-20. Control Register Settings in External Event Counter Mode (a) 16-bit timer mode control register 0 (TMC0) TMC03 TMC02 TMC01 OVF0 TMC0 Clears and starts on match between TM0 and CR00. (b) Capture/compare control register 0 (CRC0) CRC02 CRC01 CRC00...
Page 172 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-22. Timing of External Event Counter Operation (with Rising Edge Specified) TI00 pin input TM0 count value 0000 0001 0002 0003 0004 0005 N – 1 0000 0001 0002 0003 CR00 INTTM00 Caution Read TM0 when reading the count value of the external event counter. 8.4.5 Operation to output square wave The 16-bit timer/event counter operates as the square wave output for the user-defined frequency that is used as the interval for the count value previously set in 16-bit capture/compare register 00 (CR00).
Page 173 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-23. Control Register Settings in Square Wave Output Mode (a) 16-bit timer mode control register 0 (TMC0) TMC03 TMC02 TMC01 OVF0 TMC0 Clears and starts on match between TM0 and CR00. (b) Capture/compare control register 0 (CRC0) CRC02 CRC01 CRC00...
Page 174 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.4.6 Operation to output one-shot pulse The 16-bit timer/event counter can output a one-shot pulse in synchronization with a software trigger and an external trigger (TI00/P35 pin input). (1) One-shot pulse output with software trigger A one-shot pulse can be output from the TO0/P30 pin by setting 16-bit timer mode control register 0 (TMC0), capture/compare control register 0 (CRC0), and 16-bit timer output control register 0 (TOC0) as shown in Figure 8-25, and by setting bit 6 (OSPT) of TOC0 by software.
Page 175 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-25. Control Register Settings for One-Shot Pulse Output by Software Trigger (a) 16-bit timer mode control register 0 (TMC0) TMC03 TMC02 TMC01 OVF0 TMC0 Clears and starts, or free running at valid edge of T100/P35. (b) Capture/compare control register 0 (CRC0) CRC02 CRC01...
Page 176 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-26. Timing of One-Shot Pulse Output Operation by Software Trigger Sets 0CH to TMC0 (TM0 count starts) Count clock TM0 count value 0000 0001 N + 1 0000 N – 1 M – 1 M + 1 M + 2 M + 3 CR01 set value CR00 set value...
Page 177 CHAPTER 8 16-BIT TIMER/EVENT COUNTER (2) One-shot pulse output with external trigger A one-shot pulse can be output from the TO0/P30 pin by setting 16-bit timer mode control register 0 (TMC0), capture/compare control register 0 (CRC0), and 16-bit timer output control register 0 (TOC0) as shown in Figure 8-27, and by using the valid edge of the TI00/P35 pin as an external trigger.
Page 178 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-27. Control Register Settings for One-Shot Pulse Output by External Trigger (a) 16-bit timer mode control register 0 (TMC0) TMC03 TMC02 TMC01 OVF0 TMC0 Clears and starts, or free running at valid edge of TI00/P35 pin. (b) Capture/compare control register 0 (CRC0) CRC02 CRC01...
Page 179 CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-28. Timing of One-Shot Pulse Output Operation by External Trigger (with Rising Edge Specified) Sets 08H to TMC0 (TM0 count starts) Count clock TM0 count value 0000 0001 0000 N + 1 N + 2 M –...
Page 180 CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.5 Cautions (1) Error on starting timer An error of up to 1 clock occurs before the match signal is generated after the timer has been started. This is because 16-bit timer counter 0 (TM0) is started asynchronously in respect to the count pulse. Figure 8-29.
Page 181 CHAPTER 8 16-BIT TIMER/EVENT COUNTER (4) Data hold timing of capture register If the valid edge is input to the TI00/P35 pin while 16-bit capture/compare register 01 (CR01) is read, CR01 performs the capture operation, but this capture value is not guaranteed. However, the interrupt request flag (INTTM01) is set as a result of detection of the valid edge Figure 8-31.
Page 182 CHAPTER 8 16-BIT TIMER/EVENT COUNTER (7) Trigger for one-shot pulse The software trigger (bit 6 (OSPT) of 16-bit timer output control register 0 (TOC0) = 1) and the external trigger (TI00 input) are always valid in one-shot pulse output mode. If the software trigger is used in one-shot pulse output mode, the TI00 pin cannot be used as a general-purpose port pin.
Page 183 CHAPTER 8 16-BIT TIMER/EVENT COUNTER (10) Conflict operation <1> Conflict between the read period of the 16-bit capture/compare registers (CR00 and CR01) and the capture trigger input (CR00 and CR01 are used as capture registers.) The capture trigger input is preceded. The read data of CR00 and CR01 is undefined. <2>...
Page 184 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1, 2 9.1 Functions 8-bit timer/event counters 1 and 2 (TM1, TM2) have the following two modes. • Mode using 8-bit timer/event counters 1 and 2 (TM1, TM2) alone (discrete mode) • Mode using the cascade connection (16-bit resolution: cascade connection mode) These two modes are described next.
Page 185 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1, 2 9.2 Configuration 8-bit timer/event counters 1 and 2 include the following hardware. Table 9-1. Configuration of 8-Bit Timer/Event Counters 1 and 2 Item Configuration 8-bit × 2 (TM1, TM2) Timer counter 8-bit × 2 (CR10, CR20) Register Timer output 2 (TO1, TO2)
Page 186 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1, 2 Figure 9-1. Block Diagram of 8-Bit Timer/Event Counters 1 and 2 (2/2) (2) 8-bit timer/event counter 2 Internal bus Edge detector 8-bit compare Selector INTTM1 register 20 (CR20) Match 8-bit timer counter 2 (TM2) to TM2 TM1 overflow Clear...
Page 187 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1, 2 (1) 8-bit timer counters 1 and 2 (TM1, TM2) TM1 and TM2 are 8-bit read-only registers that count the count pulses. The counter is incremented synchronous to the rising edge of the count clock. When the count is read out during operation, the count clock input temporarily stops and the count is read at that time.
Page 188 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1, 2 9.3 Control Registers The following four registers control 8-bit timer/event counters 1 and 2. • 8-bit timer mode control registers 1 and 2 (TMC1, TMC2) • Prescaler mode registers 1 and 2 (PRM1, PRM2) (1) 8-bit timer mode control registers 1 and 2 (TMC1, TMC2) The TMC1 and TMC2 make the following six settings.
Page 189 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1, 2 Figure 9-2. Format of 8-Bit Timer Mode Control Register 1 (TMC1) Address: 0FF54H After reset: 00H R/W Symbol TMC1 TCE1 TMC16 LVS1 LVR1 TMC11 TOE1 TCE1 TM1 count control Counting is disabled (prescaler disabled) after the counter is cleared to 0. Start counting TMC16 TM1 operation mode selection...
Page 190 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1, 2 Figure 9-3. Format of 8-Bit Timer Mode Control Register 2 (TMC2) Address: 0FF55H After reset: 00H R/W Symbol TMC2 TCE2 TMC26 TMC24 LVS2 LVR2 TMC21 TOE2 TCE2 TM2 count control Counting is disabled (prescaler disabled) after the counter is cleared to 0. Start counting TMC26 TM2 operation mode selection...
Page 191 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1, 2 (2) Prescaler mode registers 1 and 2 (PRM1, PRM2) This register sets the count clock of 8-bit timer counters 1 and 2 (TM1, TM2) and the valid edge of TI1, TI2 inputs. PRM1 and PRM2 are set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets PRM1 and PRM2 to 00H.
Page 192 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1, 2 Figure 9-5. Format of Prescaler Mode Register 2 (PRM2) Address: 0FF57H After reset: 00H R/W Symbol PRM2 TCL22 TCL21 TCL20 TCL22 TCL21 TCL20 Count clock selection Falling edge of TI2 Rising edge of TI2 /4 (3.13 MHz) /8 (1.56 MHz) /16 (781 kHz)
Page 193 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1, 2 9.4 Operation 9.4.1 Operation as interval timer (8-bit operation) The timer operates as an interval timer that repeatedly generates interrupt requests at the interval of the preset count in 8-bit compare register 10, 20 (CR10, CR20). If the count in 8-bit timer counters 1 and 2 (TM1, TM2) matches the value set in CR10, CR20, simultaneous to clearing the value of TM1, TM2 to 0 and continuing the count, the interrupt request signal (INTTM1, INTTM2) is generated.
Page 194 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1, 2 Figure 9-6. Timing of Interval Timer Operation (1/3) (a) Basic operation Count clock TMn count value Count starts Clear Clear CRn0 TCEn INTTMn Interrupt request Interrupt request acknowledgement acknowledgement Interval time Interval time Interval time Remarks 1.
Page 195 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1, 2 Figure 9-6. Timing of Interval Timer Operation (2/3) (b) When CRn0 = 00H Count clock CRn0 TCEn INTTMn Interval time (c) When CRn0 = FFH Count clock FEH FFH 00H CRn0 TCEn INTTMn Interrupt request acknowledgement Interrupt request...
Page 196 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1, 2 Figure 9-6. Timing of Interval Timer Operation (3/3) (d) Operated by CRn0 transition (M < N) Count clock N 00H CRn0 TCEn INTTMn CRn0 transition TMn overflows since M < N. (e) Operated by CRn0 transition (M > N) Count clock N –...
Page 197 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1, 2 9.4.2 Operation as external event counter The external event counter counts the number of external clock pulses that are input to TI1/P33, TI1/P34 pins with 8-bit timer counters 1 and 2 (TM1, TM2). Each time a valid edge specified in prescaler mode registers 1 and 2 (PRM1, PRM2) is input, TM1and TM2 are incremented.
Page 198 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1, 2 9.4.3 Operation as square wave output (8-bit resolution) A square wave having any frequency is output at the interval preset in 8-bit compare registers 10 and 20 (CR10, CR20). By setting bit 0 of 8-bit timer mode control registers 1 and 2 (TMC1, TMC2) to 1, the output state of TO1, TO2 is inverted with the count preset in CR510, CR20 as the interval.
Page 199 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1, 2 9.4.4 Operation as 8-bit PWM output By setting bit 6 (TMC16, TMC26) of 8-bit timer mode control registers 1 and 2 (TMC1, TMC2) to 1, the timer operates as a PWM output. Pulses with the duty cycle determined by the value set in 8-bit compare registers 10 and 20 (CR10, CR20) is output from TO1, TO2.
Page 200 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1, 2 Figure 9-8. Timing of PWM Output (a) Basic operation (active level = H) Count clock 00H 01H FFH 00H 01H 02H N N + 1 FFH 00H 01H 02H CRn0 CRn0 read value TCEn INTTMn Reload...
Page 201 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1, 2 Figure 9-9. Timing of Operation Based on CRn0 Transitions (a) When the CRn0 value from N to M before TMn overflows Count clock N N + 1 N + 2 FFH 00H 01H M M + 1 M + 2 FFH 00H 01H 02H M M + 1 M + 2...
Page 202 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1, 2 9.4.5 Operation as interval timer (16-bit operation) • Cascade connection (16-bit timer) mode By setting bit 4 (TMC24) of 8-bit timer mode control register 2 (TMC2) to 1, the timer enters the timer/counter mode with 16-bit resolution.
Page 203 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1, 2 9.5 Cautions (1) Error when the timer starts The time until the coincidence signal is generated after the timer starts has a maximum error of one clock. The reason is the starting of 8-bit timer counters 1 and 2 (TM1, TM2) is asynchronous with respect to the count pulse. Figure 9-11.
Page 204 CHAPTER 10 8-BIT TIMERS 5, 6 10.1 Functions 8-bit timers 5 and 6 (TM5, TM6) have the following two modes. • Mode using 8-bit timers 5 and 6 (TM5, TM6) alone (discrete mode) • Mode using the cascade connection (16-bit resolution: cascade connection mode) These two modes are described next.
Page 205 CHAPTER 10 8-BIT TIMERS 5, 6 10.2 Configuration 8-bit timers 5 and 6 includes the following hardware. Table 10-1. Configuration of 8-Bit Timers 5 and 6 Item Configuration 8-bit × 2 (TM5, TM6) Timer counter 8-bit × 2 (CR50, CR60) Register Control register 8-bit timer mode control register 5 (TMC5)
Page 206 CHAPTER 10 8-BIT TIMERS 5, 6 Figure 10-1. Block Diagram of 8-Bit Timers 5 and 6 (2/2) (2) 8-bit timer 6 Internal bus Edge detector 8-bit compare Selector INTTM6 register 60 (CR60) Match 8-bit timer counter 6 (TM6) TM5 overflow Clear Selector TCL62...
Page 207 CHAPTER 10 8-BIT TIMERS 5, 6 (1) 8-bit timer counters 5 and 6 (TM5, TM6) TM5 and TM6 are 8-bit read-only registers that count the count pulses. The counter is incremented synchronous to the rising edge of the count clock. When the count is read out during operation, the count clock input temporarily stops and the count is read at that time.
Page 208 CHAPTER 10 8-BIT TIMERS 5, 6 10.3 Control Registers The following four registers control 8-bit timers 5 and 6. • 8-bit timer mode control registers 5, 6 (TMC5, TMC6) • Prescaler mode registers 5, 6 (PRM5, PRM6) (1) 8-bit timer mode control registers 5, 6 (TMC5, TMC6) TMC5 and TMC6 make the following three settings.
Page 209 CHAPTER 10 8-BIT TIMERS 5, 6 Figure 10-3. Format of 8-Bit Timer Mode Control Register 6 (TMC6) Address: 0FF69H After reset: 00H R/W Symbol TMC6 TCE6 TMC66 TMC64 TCE6 TM6 count control Counting is disabled (prescaler disabled) after the counter is cleared to 0. Start counting TMC66 TM6 operation mode selection...
Page 210 CHAPTER 10 8-BIT TIMERS 5, 6 (2) Prescaler mode registers 5 and 6 (PRM5, PRM6) This register sets the count clock of 8-bit timer counters 5 and 6 (TM5, TM6). PRM5 and PRM6 are set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets PRM5 and PRM6 to 00H.
Page 211 CHAPTER 10 8-BIT TIMERS 5, 6 Figure 10-5. Format of Prescaler Mode Register 6 (PRM6) Address: 0FF6DH After reset: 00H R/W Symbol PRM6 TCL62 TCL61 TCL60 TCL62 TCL61 TCL60 Count clock selection /4 (3.13 MHz) /8 (1.56 MHz) /16 (781 kHz) /32 (391 kHz) /128 (97.6 kHz) /512 (24.4 kHz)
Page 212 CHAPTER 10 8-BIT TIMERS 5, 6 10.4 Operation 10.4.1 Operation as interval timer (8-bit operation) The timer operates as an interval timer that repeatedly generates interrupt requests at the interval of the preset count in 8-bit compare registers 50 and 60 (CR50, CR60). If the count in 8-bit timer counters 5 and 6 (TM5, TM6) matches the value set in CR50, CR60, simultaneous to clearing the value of TM5, TM6 to 0 and continuing the count, the interrupt request signal (INTTM5, INTTM6) is generated.
Page 213 CHAPTER 10 8-BIT TIMERS 5, 6 Figure 10-6. Timing of Interval Timer Operation (1/3) (a) Basic operation Count clock TMn count value Count starts Clear Clear CRn0 TCEn INTTMn Interrupt request Interrupt request acknowledgement acknowledgement Interval time Interval time Interval time Remarks 1.
Page 214 CHAPTER 10 8-BIT TIMERS 5, 6 Figure 10-6. Timing of Interval Timer Operation (2/3) (b) When CRn0 = 00H Count clock CRn0 TCEn INTTMn Interval time (c) When CRn0 = FFH Count clock FEH FFH 00H CRn0 TCEn INTTMn Interrupt request acknowledgement Interrupt request acknowledgement...
Page 215 CHAPTER 10 8-BIT TIMERS 5, 6 Figure 10-6. Timing of Interval Timer Operation (3/3) (d) Operated by CRn0 transition (M < N) Count clock N 00H CRn0 TCEn INTTMn CRn0 transition TMn overflows since M < N. (e) Operated by CRn0 transition (M > N) Count clock N –...
Page 216 CHAPTER 10 8-BIT TIMERS 5, 6 Figure 10-7. Timing of Operation Based on CRn0 Transitions (a) When the CRn0 value from N to M before TMn overflows Count clock N N + 1 N + 2 FFH 00H 01H M N + 1 N + 2 FFH 00H 01H 02H M N + 1 N + 2 CRn0...
Page 217 CHAPTER 10 8-BIT TIMERS 5, 6 10.4.2 Operation as interval timer (16-bit operation) • Cascade connection (16-bit timer) mode By setting bit 4 (TMC64) of 8-bit timer mode control register 6 (TMC6) to 1, the timer enters the timer mode with 16-bit resolution.
Page 218 CHAPTER 10 8-BIT TIMERS 5, 6 10.5 Cautions (1) Error when the timer starts The time until the coincidence signal is generated after the timer starts has a maximum error of one clock. The reason is the starting of 8-bit timer counters 5 and 6 (TM5, TM6) is asynchronous with respect to the count pulse. Figure 10-9.
Page 219 CHAPTER 11 WATCH TIMER 11.1 Function The watch timer has the following functions: • Watch timer • Interval timer The watch timer and interval timer functions can be used at the same time. (1) Watch timer The watch timer generates an interrupt request (INTWT) at time intervals of 2 or 2 by using the main system clock of 4.19 MHz or subsystem clock of 32.768 kHz.
Page 220 CHAPTER 11 WATCH TIMER 11.2 Configuration The watch timer includes the following hardware. Table 11-2. Configuration of Watch Timer Item Configuration 5 bits × 1 Counter 9 bits × 1 Prescaler Control register Watch timer mode control register (WTM) Figure 11-1. Block Diagram of Watch Timer INTWT Clear 5-bit counter...
Page 221 CHAPTER 11 WATCH TIMER 11.3 Watch Timer Control Register • Watch timer mode control register (WTM) This register enables or disables the count clock and operation of the watch timer, sets the interval time of the prescaler, controls the operation of the 5-bit counter, and sets the set time of the watch flag. WTM is set by a 1-bit or 8-bit memory manipulation instruction.
Page 222 CHAPTER 11 WATCH TIMER Figure 11-2. Format of Watch Timer Mode Control Register (WTM) Address: 0FF9CH After reset: 00H Symbol WTM7 WTM6 WTM5 WTM4 WTM3 WTM1 WTM0 WTM7 Selects count clock of watch timer Main system clock (f Subsystem clock (f WTM6 WTM5 WTM4...
Page 223 CHAPTER 11 WATCH TIMER 11.4 Operation 11.4.1 Operation as watch timer The watch timer operates with time intervals of 2 or 2 with the main system clock (4.19 MHz) or subsystem clock (32.768 kHz). The watch timer generates an interrupt request (INTWT) at fixed time intervals. The count operation of the watch timer is started when bits 0 (WTM0) and 1 (WTM1) of the watch timer mode control register (WTM) are set to 1.
Page 224 CHAPTER 11 WATCH TIMER Figure 11-3. Operation Timing of Watch Timer/Interval Timer Watch timer Overflow Overflow Start Count clock Watch timer interrupt INTWT Interrupt time of watch timer Interrupt time of watch timer Interval timer interrupt INTTM3 Interval time Interval time Caution When enabling operation of the watch timer mode control register (WTM), watch timer, and 5- bit counter, the time until the first watch timer interrupt request (INTWT) is generated is not exactly the same time as set by bits 4 to 6 of WTM (WTM4 to WTM6).
Page 225 CHAPTER 12 WATCHDOG TIMER The watchdog timer detects inadvertent program loops. Program or system errors are detected by the generation of watchdog timer interrupts. Therefore, at each location in the program, the instruction that clears the watchdog timer (starts the count) within a constant time is input. If the watchdog timer overflows without executing the instruction that clears the watchdog timer within the set period, a watchdog timer interrupt (INTWDT) is generated to signal a program error.
Page 226 If returning by simply using the RETB instruction from the operand error, an infinite loop results. Since an operand error interrupt is generated only when the program inadvertently loops (the correct special instruction is only generated when MOV WDM #byte is described in the RA78K4 NEC assembler), make the program initialize the system.
Page 227 CHAPTER 12 WATCHDOG TIMER Figure 12-2. Format of Watchdog Timer Mode Register (WDM) Address: 0FFC2H After reset: 00H Symbol WDT4 WDT2 WDT1 Watchdog timer operation setting Stops the watchdog timer. Clears the watchdog timer and starts counting. WDT4 Watchdog timer interrupt request priority Watchdog timer interrupt request <NMI pin input interrupt request Watchdog timer interrupt request...
Page 228 CHAPTER 12 WATCHDOG TIMER 12.3 Operations 12.3.1 Count operation The watchdog timer is cleared by setting the RUN bit of the watchdog timer mode register (WDM) to 1 to start counting. After the RUN bit is set to 1, when the overflow time set by bits WDT2 and WDT1 in WDM has elapsed, a non-maskable interrupt (INTWDT) is generated.
Page 229 CHAPTER 12 WATCHDOG TIMER 12.4 Cautions 12.4.1 General cautions when using the watchdog timer (1) The watchdog timer is one way to detect inadvertent program loop , but not all the program loops can be detected. Therefore, in a device that particularly demands reliability, the inadvertent program loop must be detected early not only by the on-chip watchdog timer but by an externally attached circuit;...
Page 230 CHAPTER 13 A/D CONVERTER 13.1 Functions The A/D converter converts analog inputs to digital values, and is configured by eight 8-bit resolution channels (ANI0 to ANI7). Successive approximation is used as the conversion method, and conversion results are saved in the 8-bit A/D conversion result register (ADCR).
Page 231 CHAPTER 13 A/D CONVERTER Figure 13-1. Block Diagram of A/D Converter ANI0 ANI1 Sample & hold circuit ANI2 Voltage comparator ANI3 ANI4 ANI5 Successive ANI6 approximation ANI7 register (SAR) Edge INTP3/P03 INTAD Controller detector Edge INTP3 detector Note Trigger enable A/ D conversion result register ADCS...
Page 232 CHAPTER 13 A/D CONVERTER (1) Successive approximation register (SAR) Compares the voltage of the analog input with the voltage tap (comparison voltage) from the series resistor string, and saves the result from the most significant bit (MSB). The contents of SAR will be transmitted across to the A/D conversion result register after the least significant bit (LSB) is saved (A/D conversion finished).
Page 233 CHAPTER 13 A/D CONVERTER 13.3 Control Registers The A/D converter controls the following two registers. • A/D converter mode register (ADM) • A/D converter input selection register (ADIS) (1) A/D converter mode register (ADM) Used to set the A/D conversion time of analog input to be converted, start/stop of conversion operation, and external triggers.
Page 234 CHAPTER 13 A/D CONVERTER Figure 13-2. Format of A/D Converter Mode Register (ADM) Address: 0FF80H After reset: 00H Symbol ADCS EGA1 EGA0 ADCE ADCS A/D conversion control Conversion stop Conversion enable Software start/hardware start selection Software start Hardware start A/D conversion time selection Number of clocks @f = 12.5 MHz = 6.25 MHz...
Page 235 CHAPTER 13 A/D CONVERTER Cautions 1. Set the A/D conversion time as follows: = 2.7 V to 5.5 V: 14 µ s or more When V = 2.0 V to 2.7 V: 24 µ s or more When V = 1.9 V to 2.0 V: 48 µ s or more ( µ PD78F4225 only) When V = 1.8 V to 2.0 V: 48 µ...
Page 236 CHAPTER 13 A/D CONVERTER 13.4 Operations 13.4.1 Basic operations of A/D converter <1> Select one channel for A/D conversion with the A/D converter input selection register (ADIS). <2> The voltage input to the selected analog input channel is sampled by the sample & hold circuit. <3>...
Page 237 CHAPTER 13 A/D CONVERTER Figure 13-4. Basic Operations of A/D Converter Conversion time Sampling time A/D converter Sampling A/D conversion operation Conversion Undefined result Conversion ADCR result INTAD A/D conversion is performed continuously until bit 7 (ADCS) of A/D converter mode register (ADM) is reset 0 by software.
Page 238 CHAPTER 13 A/D CONVERTER 13.4.2 Input voltage and conversion result The relationship between the analog input voltage input to the analog input pins (ANI0 to ANI7) and the A/D conversion result (value saved in the A/D conversion result register (ADCR)) is expressed by the following equation. ×...
Page 239 CHAPTER 13 A/D CONVERTER 13.4.3 Operations mode of A/D converter Select one channel for analog input from between ANI0 to ANI7 with the A/D converter input selection register (ADIS) and commence A/D conversion. A/D conversion can be started in the following two ways. •...
Page 240 CHAPTER 13 A/D CONVERTER Figure 13-6. A/D Conversion Operation by Hardware Start (When Falling Edge Is Specified) ADM overwrite ADM overwrite ADCS = 1, TRG = 1 ADCS = 1, TRG = 1 Standby Standby Standby A /D conversion ANIn ANIn ANIn ANIm...
Page 241 CHAPTER 13 A/D CONVERTER (2) A/D conversion operation by software start A/D conversion of the voltage applied to the analog input pin specified with A/D converter input selected register (ADIS) is started by setting “0” to bit 6 (TRG) and “1” to bit 7 (ADCS) of the A/D converter mode register (ADM). When A/D conversion ends, the conversion result is saved in the A/D conversion result register (ADCR), and an interrupt request signal (INTAD) is issued.
Page 242 CHAPTER 13 A/D CONVERTER 13.5 Reading the A/D Converter Characteristics Table Words used specifically for the A/D converter are defined below. (1) Resolution The lowest identifiable analog input voltage, or the ratio of the analog input voltage to one bit of a digital output, is known as 1LSB (least significant bit).
Page 243 CHAPTER 13 A/D CONVERTER (4) Zero-scale error This expresses the difference between the actual and theoretical analog input voltage measurement values when the digital output changes from 0 ..000 to 0 ..001 (1/2LSB). If the actual value is higher than the theoretical value, the zero-scale error indicates the difference between the actual and theoretical analog input voltage measurement values when the digital output changes from 0 ..
Page 244 CHAPTER 13 A/D CONVERTER Figure 13-12. Integral Linearity Error Figure 13-13. Differential Linearity Error Ideal linearity Theoretical 1LSB width Differential linearity error Integral linearity error Analog input Analog input (8) Conversion time This expresses the time from when the analog input voltage is applied to when the digital output is obtained. The sampling time is included in the conversion time value shown in the characteristic table.
Page 245 CHAPTER 13 A/D CONVERTER 13.6 Cautions (1) Current consumption in standby mode The A/D converter operation is stopped during the standby mode. At this time, the current consumption can be reduced by setting bit 7 (ADCS) of the A/D converter mode register (ADM) to 0 or by stopping the reference voltage circuit (bit of ADM (ADCE) = 0).
Page 246 CHAPTER 13 A/D CONVERTER (4) Anti-noise measures Attention must be paid to noise fed to AV and ANI0 to ANI7 to preserve the 8-bit resolution. The influence of noise grows proportionally to the output impedance of the analog input source. Therefore, it is recommended to connect C externally, as shown in Figure 13-15.
Page 247 CHAPTER 13 A/D CONVERTER (7) Interrupt request flag (ADIF) The interrupt request flag (ADIF) is not cleared even if the A/D converter input selected register (ADIS) is changed. Owing to this, there will be cases when the A/D conversion result and ADIF that correspond with the pre-amended analog input immediately prior to ADM overwriting will be set if the analog input pin is amended during A/D conversion.
Page 248 CHAPTER 13 A/D CONVERTER (8) Bit 0 (ADCE) of A/D converter mode register (ADM) Setting ADCE to 1, allows the value of the first A/D conversion immediately after A/D conversion operation start to be used. (9) Conversion results immediately after A/D conversion is started If bit 7 (ADCS0) of the A/D converter mode register (ADM) is set to 1 without setting bit 0 (ADCE) to 1, the value of the first A/D conversion is undefined immediately after the A/D conversion operation starts.
Page 249 CHAPTER 13 A/D CONVERTER (10) Reading A/D conversion result register (ADCR) If the conversion result register (ADCR) is read after stopping the A/D conversion operation, the conversion result may be undefined. Therefore, be sure to read ADCR before stopping operation of the A/D converter. (11) Timing that makes the A/D conversion result undefined If the timing of the end of A/D conversion and the timing of the stop of operation of the A/C converter conflict, the A/D conversion value may be undefined.
Page 250 CHAPTER 13 A/D CONVERTER (12) Cautions on board design In order to avoid negative effects from digital circuit noise on the board, analog circuits must be placed as far away as possible from digital circuits. It is particularly important to prevent analog and digital signal lines from crossing or coming into close proximity, as A/D conversion characteristics are vulnerable to degradation from the induction of noise or other such factors.
Page 251 CHAPTER 13 A/D CONVERTER Figure 13-21. Internal Equivalence Circuit of ANI0 to ANI7 Pins ANin Remark n = 0 to 7 Table 13-2. Resistance and Capacitance Values for Equivalence Circuits (Reference Values) 1.8 V 75 kΩ 30 kΩ 3 pF 4 pF 2 pF 2.7 V...
Page 252 CHAPTER 14 D/A CONVERTER 14.1 Function The D/A converter converts the digital input into analog values and consists of two channels of voltage output D/ A converters with 8-bit resolution. The conversion method is a R-2R resistor ladder. Set DACE0 of D/A converter mode register 0 (DAM0) and DACE1 of D/A converter mode register 1 (DAM1) to start the D/A conversion.
Page 253 CHAPTER 14 D/A CONVERTER Figure 14-1. Block Diagram of D/A Converter Internal bus DACS1 D/A conversion setting write register 1 (DACS1) INTTM2 DACS0 D/A conversion setting write register 0 (DACS0) INTTM1 ANO1/P131 REF1 Selector ANO0/P130 Selector DAM1 DACE1 DAM0 DACE0 D/A converter D/A converter mode register 1...
Page 254 CHAPTER 14 D/A CONVERTER 14.3 Control Registers • D/A converter mode registers 0 and 1 (DAM0, DAM1) D/A converters are controlled by D/A converter mode registers 0, 1 (DAM0, DAM1). These registers enable or stop the operation of the D/A converters. DAM0 and DAM1 are set by a 1-bit and 8-bit memory manipulation instruction.
Page 255 CHAPTER 14 D/A CONVERTER 14.4 Operation <1> Select the operation mode in channel 0 in DAM0 of D/A converter mode register 0 (DAM0) and the operation mode of the channel 1 in DAM1 of D/A converter mode register 1 (DAM1). <2>...
Page 256 CHAPTER 14 D/A CONVERTER Figure 14-3. Buffer Amp Insertion Example (a) Inverting Amp µ PD784225, 784225Y ANOn – • The input impedance of the buffer amp is R (b) Voltage follower µ PD784225, 784225Y ANOn – • The input impedance of the buffer amp is R •...
Page 257 CHAPTER 15 SERIAL INTERFACE OVERVIEW The µ PD784225 Subseries has a serial interface with three independent channels. Therefore, communication outside and within the system can be simultaneous on the three channels. • Asynchronous serial interface (UART)/3-wire serial I/O (IOE) × 2 channels →...
Page 258 CHAPTER 15 SERIAL INTERFACE OVERVIEW Figure 15-1. Serial Interface Example (a) UART + I µ PD784225Y (master) µ PD78054Y (slave) µ PD4711A [UART] SDA0 RxD1 SCL0 TxD1 RS-232C driver/receiver  Port   µ PD78062Y (slave) µ PD4711A [UART] RxD2 TxD2 RS-232C driver/receiver...
Page 259 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O µ PD784225 provides on chip two serial interface channels for which the asynchronous serial interface (UART) mode and the 3-wire serial I/O (IOE) mode can be selected. These two serial interface channels have exactly the same functions. Table 16-1.
Page 260 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O 16.1 Switching Asynchronous Serial Interface Mode and 3-Wire Serial I/O Mode The asynchronous serial interface mode and the 3-wire serial I/O mode cannot be used at the same time. Both these modes can be switched by setting asynchronous serial interface mode registers 1, 2 (ASIM1, ASIM2) and serial operation mode registers 1, 2 (CSIM1, CSIM2), as shown in Figure 16-1 below.
Page 261 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O 16.2 Asynchronous Serial Interface Mode The asynchronous serial interface (UART: Universal Asynchronous Receiver Transmitter) offers the following two modes. (1) Operation stop mode This mode is used when serial transfer is not performed to reduce the power consumption. (2) Asynchronous serial interface (UART) mode This mode is used to send and receive 1-byte data that follows the start bit, and supports full-duplex transmission.
Page 262 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O Figure 16-2. Block Diagram in Asynchronous Serial Interface Mode Internal bus Receive buffer registers 1, 2 (RXB1, RXB2) Transmit shift Receive shift RxD1, RxD2 registers 1, 2 registers 1, 2 (TXS1, TXS2) (RX1, RX2) TxD1, TxD2 Receive Transmit...
Page 263 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O (1) Transmit shift registers 1, 2 (TXS1, TXS2) These registers are used to set transmit data. Data written to TXS1 and TXS2 is sent as serial data. If a data length of 7 bits is specified, bits 0 to 6 of the data written to TXS1 and TXS2 are transferred as transmit data.
Page 264 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O 16.2.2 Control registers The asynchronous serial interface is controlled by the following six registers. • Asynchronous serial interface mode registers 1, 2 (ASIM1, ASIM2) • Asynchronous serial interface status registers 1, 2 (ASIS1, ASIS2) •...
Page 265 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O Figure 16-3. Format of Asynchronous Serial Interface Mode Registers 1 and 2 (ASIM1, ASIM2) Address: 0FF70H, 0FF71H After reset: 00H Symbol Note ASIMn TXEn RXEn PSn1 PSn0 ISRMn RxD1/P20, RxD2/P70 TxD1/P21, TxD2/P71 TXEn RXEn Operation mode pin function...
Page 266 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O (2) Asynchronous serial interface status registers 1 and 2 (ASIS1, ASIS2) ASIS1 and ASIS2 are registers used display the type of error when a receive error occurs. ASIS1 and ASIS2 can be read by a 1-bit or 8-bit memory manipulation instruction. RESET input sets ASIS1 and ASIS2 to 00H.
Page 267 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O Figure 16-5. Format of Baud Rate Generator Control Registers 1 and 2 (BRGC1, BRGC2) Address: 0FF76H, 0FF77H After reset: 00H Symbol BRGCn TPSn2 TPSn1 TPSn0 MDLn3 MDLn2 MDLn1 MDLn0 TPSn2 TPSn1 TPSn0 5-bit counter source clock selection External clock (ASCKn) (12.5 MHz) /2 (6.5 MHz)
Page 268 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O 16.3 Operation The asynchronous serial interface has the following two operation modes. • Operation stop mode • Asynchronous serial interface (UART) mode 16.3.1 Operation stop mode Serial transfer cannot be performed in the operation stop mode, resulting in reduced power consumption. Moreover, in the operation stop mode, pins can be used as regular ports.
Page 269 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O 16.3.2 Asynchronous serial interface (UART) mode This mode is used to transmit and receive the 1-byte data following the start bit. It supports full-duplex operation. A UART-dedicated baud rate generator is incorporated enabling communication using any baud rate within a large range.
Page 270 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O (a) Asynchronous serial interface mode registers 1 and 2 (ASIM1, ASIM2) ASIM1 and ASIM2 can be set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets ASIM1 and ASIM2 to 00H. Address: 0FF70H, 0FF71H After reset: 00H Symbol Note...
Page 271 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O (b) Asynchronous serial interface status registers 1 and 2 (ASIS1, ASIS2) ASIS1 and ASIS2 can be read by a 1-bit or 8-bit memory manipulation instruction. RESET input sets ASIS1 and ASIS 2 to 00H. Address: 0FF72H, 0FF73H After reset: 00H Symbol ASISn...
Page 272 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O (c) Baud rate generator control registers 1 and 2 (BRGC1, BRGC2) BRGC1 and BRGC2 are set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets BRGC1 and BRGC2 to 00H. Address: 0FF76H, 0FF77H After reset: 00H Symbol BRGCn TPSn2...
Page 273 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O 3. Set the 8-bit timer mode control register (TMC1) as follows when selecting TO1 for the source clock of the 5-bit counter. TMC16 = 0, LVS1 = 0, LVR1 = 0, TMC11 = 1 Moreover, set TOE1 to 0 when TO1 is not output externally and TOE1 to 1 when TO1 is output externally Remarks 1.
Page 274 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O • Baud rate capacity error range The baud rate capacity range depends on the number of bits per frame and the counter division ratio [1/(16 + k)]. Table 16-3 shows the relationship between the main system clock and the baud rate, Table 16-6 shows a baud rate allowable error example.
Page 275 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O (2) Communication operation (a) Data format The format for sending and receiving data is shown in Figure 16-7. Figure 16-7. Format of Asynchronous Serial Interface Transmit/Receive Data 1-data frame Start Parity Stop bit(s) Character bits Each data frame is composed for the bits outlined below.
Page 276 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O (b) Parity types and operations Parity bits serve to detect bit errors in transmit data. Normally, the parity bit used on the transmit side and the receive side are of the same type. In the case of even parity and odd parity, it is possible to detect “1” bit (odd number) errors.
Page 277 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O (c) Transmission Transmission is begun by writing transmit data to transmission shift register n (TXSn). The start bit, parity bit, and stop bit(s) are automatically added. The contents of transmit shift register n (TXSn) are shifted out upon transmission start, and when transmit shift register n (TXSn) becomes empty, a transmit interrupt (INTSTn) is generated.
Page 278 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O (d) Reception When the RXEn bit of asynchronous serial interface mode register n (ASIMn) is set to 1, reception is enabled and sampling of the RxDn pin input is performed. Sampling of the RxDn pin input is performed by the serial clock set in baud rate generator control register n (BRGCn).
Page 279 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O (e) Receive error Errors that occur during reception are of three types: parity errors, framing errors, and overrun errors. As the data reception result error flag is set inside asynchronous serial interface status register n (ASISn), the receive error interrupt request (INTSERn) is generated.
Page 280 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O 16.3.3 Standby mode operation (1) HALT mode operation Serial transfer operation is normally performed. (2) STOP mode or IDLE mode operation (a) When internal clock is selected as serial clock Asynchronous serial interface mode register n (ASIMn), transmit shift register n (TXSn), receive shift register n (RXn), and receive buffer register n (RXBn) stop operation holding the value immediately before the clock stops.
Page 281 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O 16.4 3-Wire Serial I/O Mode This mode is used to perform 8-bit data transfer with the serial clock (SCK1, SCK2), serial output (SO1, SO2), and serial input (SI1, SI2) lines. The 3-wire serial I/O mode supports simultaneous transmit/receive operation, thereby reducing the data transfer processing time.
Page 282 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O Figure 16-11. Block Diagram in 3-Wire Serial I/O Mode Internal bus Serial I/O shift registers 1, 2 SI1, SI2 (SIO1, SIO2) SO1, SO2 Serial Interrupt SCK1, SCK2 clock INTCSI1, generator counter INTCSI2 Serial clock Selector controller...
Page 283 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O 16.4.2 Control registers • Serial operation mode registers 1 and 2 (CSIM1, CSIM 2) CSIM1 and CSIM2 are used to set the serial clock, operation mode, and operation enable/disable during the 3-wire serial I/O mode. CSIM1 and SCIM2 can be set by a 1-bit or 8-bit memory manipulation instruction.
Page 284 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O 16.4.3 Operation The following two types of 3-wire serial I/O operation mode are available. • Operation stop mode • 3-wire serial I/O mode (1) Operation stop mode Serial transfer is not possible in the operation stop mode, which reduces power consumption. Moreover, in operation stop mode, pins can normally be used a I/O ports.
Page 285 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O (2) 3-wire serial I/O mode The 3-wire serial I/O mode is effective when connecting a peripheral I/O with an on-chip clock synchronization serial interface, a display controller, etc. This mode is used to perform communication with the serial clock (SCK1, SCK2), serial output (SO1, SO2), and serial input (SI1, SI2) lines.
Page 286 CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O (b) Communication operation The 3-wire serial I/O mode performs data transfer in 8-byte units. Data is transmitted and received one byte at a time in synchronization with the serial clock. The shift operation of the serial I/O shift register n (SIOn) is performed in synchronization with the falling edge of the serial clock (SCKn).
Page 287 CHAPTER 17 3-WIRE SERIAL I/O MODE 17.1 Function This mode transfers 8-bit data by using the three lines of the serial clock (SCK0), the serial output (SO0), and the serial input (SI0). Since the 3-wire serial I/O mode can perform simultaneous transmission and reception, the data transfer processing time becomes shorter.
Page 288 CHAPTER 17 3-WIRE SERIAL I/O MODE Figure 17-1. Block Diagram of Clocked Serial Interface (in 3-Wire Serial I/O Mode) Internal bus Serial I/O shift register 0 (SIO0) Serial clock Interrupt INTCSI0 SCK0 counter generator Serial clock Selector controller • Serial I/O shift register 0 (SIO0) This 8-bit shift register performs parallel to serial conversion and serially communication (shift operation) synchronized to the serial clock.
Page 289 CHAPTER 17 3-WIRE SERIAL I/O MODE 17.3 Control Registers • Serial operation mode register 0 (CSIM0) The CSIM0 register sets the serial clock and operation mode to the 3-wire serial I/O mode, and enables or stops operation. CSIM0 is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets CSIM0 to 00H.
Page 290 CHAPTER 17 3-WIRE SERIAL I/O MODE 17.4 Operation 3-wire serial I/O has the following two operation modes. • Operation stop mode • 3-wire serial I/O mode (1) Operation stop mode Since serial transfers are not performed in the operation stopped mode, power consumption can be decreased. In the operation stop mode, the pin can be used as an ordinary I/O port.
Page 291 CHAPTER 17 3-WIRE SERIAL I/O MODE (2) 3-wire serial I/O mode The 3-wire serial I/O mode is valid when connected to peripheral I/O or a display controller with an internal clocked serial interface. Communication is over three lines, the serial clock (SCK0), serial output (SO0), and serial input (SI0). (a) Register setting The 3-wire serial I/O mode is set in serial operation mode register 0 (CSIM0).
Page 292 CHAPTER 17 3-WIRE SERIAL I/O MODE (b) Communication operation The 3-wire serial I/O mode transmits and receives in 8-bit units. Data is transmitted and received with each bit synchronized to the serial clock. The shifting of the serial I/O shift register 0 (SIO0) is synchronized to the falling edge of the serial clock (SCK0).
Page 293 C BUS MODE ( µ PD784225Y SUBSERIES ONLY) CHAPTER 18 I 18.1 Function Overview • I C (Inter IC) bus mode (supporting multi master) This interface communicates with devices that conform to the I C bus format. Eight bit data transfers with multiple devices are performed by the two lines of the serial clock (SCL0) and the serial data bus (SDA0).
Page 294 C BUS MODE ( µ PD784225Y SUBSERIES ONLY) CHAPTER 18 I Figure 18-1. Serial Bus Configuration Example in I C Bus Mode Master CPU 2 Serial data bus Slave CPU 2 SDA0 SDA0 Master CPU 1 Slave CPU 1 Serial clock Address 1 SCL0 SCL0...
Page 295 C BUS MODE ( µ PD784225Y SUBSERIES ONLY) CHAPTER 18 I Figure 18-2. Block Diagram of Clocked Serial Interface (I C Bus Mode) Internal bus C bus status register 0 (IICS0) MSTS0 ALD0 EXC0 COI0 TRC0 ACKD0 STD0 SPD0 C bus control register 0 (IICC0) Slave address IICE0 LREL0 WREL0 SPIE0 WTIM0 ACKE0 STT0 SPT0...
Page 296 C BUS MODE ( µ PD784225Y SUBSERIES ONLY) CHAPTER 18 I (1) Serial shift register 0 (IIC0) The IIC0 register converts 8-bit serial data into 8-bit parallel data and 8-bit parallel data into 8-bit serial data. IIC0 is used in both transmission and reception. The actual transmission and reception are controlled by writing and reading IIC0.
Page 297 C BUS MODE ( µ PD784225Y SUBSERIES ONLY) CHAPTER 18 I 18.3 Control Registers The I C bus mode is controlled by the following three registers. • I C bus control register 0 (IICC0) • I C bus status register 0 (IICS0) •...
Page 298 C BUS MODE ( µ PD784225Y SUBSERIES ONLY) CHAPTER 18 I Figure 18-3. Format of I C Bus Control Register 0 (IICC0) (1/4) Address: 0FFB0H After reset: 00H Symbol IICC0 IICE0 LREL0 WREL0 SPIE0 WTIM0 ACKE0 STT0 SPT0 IICE0 C operation enabled Operation disabled.
Page 299 C BUS MODE ( µ PD784225Y SUBSERIES ONLY) CHAPTER 18 I Figure 18-3. Format of I C Bus Control Register 0 (IICC0) (2/4) WTIM0 Control of wait and interrupt request generation Interrupt request generated at the falling edge of the eighth clock For the master: After the eighth clock is output, wait with the clock output low.
Page 300 C BUS MODE ( µ PD784225Y SUBSERIES ONLY) CHAPTER 18 I Figure 18-3. Format of I C Bus Control Register 0 (IICC0) (3/4) STT0 Start condition trigger The start condition is not generated. • When the bus is released (stop condition): The start condition is generated (started as the master).
Page 301 C BUS MODE ( µ PD784225Y SUBSERIES ONLY) CHAPTER 18 I Figure 18-3. Format of I C Bus Control Register 0 (IICC0) (4/4) SPT0 Stop condition trigger The stop condition is not generated. The stop condition is generated (ends the transfer as the master). After the SDA0 line goes low, the SCL0 line goes high, or wait until SCL0 goes high.
Page 302 C BUS MODE ( µ PD784225Y SUBSERIES ONLY) CHAPTER 18 I (2) I C bus status register 0 (IICS0) The IICS0 register displays the status of the I C bus. IICS0 is set by a 1-bit or 8-bit memory manipulation instruction. IICS0 can only be read. RESET input sets IICS0 to 00H.
Page 303 C BUS MODE ( µ PD784225Y SUBSERIES ONLY) CHAPTER 18 I Figure 18-4. Format of I C Bus Status Register 0 (IICS0) (2/3) COI0 Address match detection The address does not match. The address matches. Clear condition (COI0 = 0) Set condition (COI0 = 1) •...
Page 304 C BUS MODE ( µ PD784225Y SUBSERIES ONLY) CHAPTER 18 I Figure 18-4. Format of I C Bus Status Register 0 (IICS0) (3/3) ACKD0 Acknowledge detection The acknowledge is not detected. The acknowledge is detected. Clear condition (ACKD0 = 0) Set condition (ACKD0 = 1) •...
Page 305 C BUS MODE ( µ PD784225Y SUBSERIES ONLY) CHAPTER 18 I (3) Prescaler mode register 0 for the serial clock (SPRM0) The SPRM0 register sets the transfer clock of the I C bus. SPRM0 is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets SPRM0 to 00H.
Page 306 C BUS MODE ( µ PD784225Y SUBSERIES ONLY) CHAPTER 18 I Figure 18-5. Format of Prescaler Mode Register 0 for Serial Clock (SPRM0) (2/2) Note 1 Note 2 Transfer clock setting allowable range 2 to 4.19 MHz 4.19 to 8.38 MHz /172 8.38 to 12.5 MHz TM2 output/66...
Page 307 C BUS MODE ( µ PD784225Y SUBSERIES ONLY) CHAPTER 18 I (4) Serial shift register 0 (IIC0) This register performs serial communication (shift operation) synchronized to the serial clock. Although this register can be read and written in 1-bit and 8-bit units, do not write data to IIC0 during a data transfer. Address: 0FFB8H After reset: 00H Symbol...
Page 308 C BUS MODE ( µ PD784225Y SUBSERIES ONLY) CHAPTER 18 I 18.4 I C Bus Mode Function 18.4.1 Pin configuration The serial clock pin (SCL0) and the serial data bus pin (SDA0) have the following configurations. (1) SCL0 ········· I/O pin for the serial clock The outputs to both the master and slave are N-ch open drains.
Page 309 C BUS MODE ( µ PD784225Y SUBSERIES ONLY) CHAPTER 18 I 18.5 I C Bus Definitions and Control Method Next, the serial data communication formats of the I C bus and the meanings of the signals used are described. Figure 18-7 shows the transfer timing of the start condition, data, and stop condition that are output on the serial data bus of the I C bus.
Page 310 C BUS MODE ( µ PD784225Y SUBSERIES ONLY) CHAPTER 18 I 18.5.2 Address The 7-bit data following the start condition defines the address. The address is 7-bit data that is output so that the master selects a specific slave from the multiple slaves connected to the bus line.
Page 311 C BUS MODE ( µ PD784225Y SUBSERIES ONLY) CHAPTER 18 I 18.5.4 Acknowledge signal (ACK) The acknowledge signal verifies the reception of the serial data on the transmitting and receiving sides. The receiving side returns the acknowledge signal each time 8-bit data is received. Usually, after transmitting 8- bit data, the transmitting side receives an acknowledge signal.
Page 312 C BUS MODE ( µ PD784225Y SUBSERIES ONLY) CHAPTER 18 I 18.5.5 Stop condition When the SCL0 pin is high and the SDA0 pin changes from low to high, the stop condition results. The stop condition is the signal output by the master to the slave when serial transfer ends. The slave has hardware that detects the stop condition.
Page 313 C BUS MODE ( µ PD784225Y SUBSERIES ONLY) CHAPTER 18 I 18.5.6 Wait signal (WAIT) The wait signal notifies the other side that the master or slave is being prepared (wait state) for data communication. The wait state is notified to the other side by setting the SCL0 pin low. When both the master and the slave are released from the wait state, the next transfer can start.
Page 314 C BUS MODE ( µ PD784225Y SUBSERIES ONLY) CHAPTER 18 I Figure 18-13. Wait Signal (2/2) (2) Both the master and slave have 9 clock waits (Master: transmitting, Slave: receiving, ACKE0 = 1) Master Both the master and slave wait after nine clocks are output.
Page 315 C BUS MODE ( µ PD784225Y SUBSERIES ONLY) CHAPTER 18 I 18.5.7 I C interrupt request (INTIIC0) This section describes the values of I C bus status register 0 (IICS0) at the INTIIC0 interrupt request generation timing and the INTIIC0 interrupt request timing. (1) Master operation (a) Start - Address - Data - Data - Stop (normal communication) <1>...
Page 316 C BUS MODE ( µ PD784225Y SUBSERIES ONLY) CHAPTER 18 I (b) Start - Address - Data - Start - Address - Data - Stop (Restart) <1> When WTIM0 = 0 STT0 = 1 SPT0 = 1 AD6-AD0 D7 to D0 AD6 to AD0 D7 to D0 1: IICS0 = 10×××110B...
Page 317 C BUS MODE ( µ PD784225Y SUBSERIES ONLY) CHAPTER 18 I (c) Start - Code - Data - Data - Stop (Extended code transmission) <1> When WTIM0 = 0 SPT0 = 1 AD6 to AD0 D7 to D0 D7 to D0 1: IICS0 = 1010×110B 2: IICS0 = 1010×000B 3: IICS0 = 1010×000B (WTIM0 = 1)
Page 318 C BUS MODE ( µ PD784225Y SUBSERIES ONLY) CHAPTER 18 I (2) Slave operation (when receiving slave address data (SVA0 match)) (a) Start - Address - Data - Data - Stop <1> When WTIM0 = 0 AD6 to AD0 D7 to D0 D7 to D0 1: IICS0 = 0001×110B 2: IICS0 = 0001×000B...
Page 319 C BUS MODE ( µ PD784225Y SUBSERIES ONLY) CHAPTER 18 I (b) Start - Address - Data - Start - Address - Data - Stop <1> When WTIM0 = 0 (SVA0 match after restart) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 1: IICS0 = 0001×110B...
Page 320 C BUS MODE ( µ PD784225Y SUBSERIES ONLY) CHAPTER 18 I (c) Start - Address - Data - Start - Code - Data - Stop <1> When WTIM0 = 0 (extended code received after restart) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 1: IICS0 = 0001×110B...
Page 321 C BUS MODE ( µ PD784225Y SUBSERIES ONLY) CHAPTER 18 I (d) Start - Address - Data - Start - Address - Data - Stop <1> When WTIM0 = 0 (no address match after restart (not extended code)) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0...
Page 322 C BUS MODE ( µ PD784225Y SUBSERIES ONLY) CHAPTER 18 I (3) Slave operation (when receiving the extended code) (a) Start - Code - Data - Data - Stop <1> When WTIM0 = 0 AD6 to AD0 D7 to D0 D7 to D0 1: IICS0 = 0010×010B 2: IICS0 = 0010×000B...
Page 323 C BUS MODE ( µ PD784225Y SUBSERIES ONLY) CHAPTER 18 I (b) Start - Code - Data - Start - Address - Data - Stop <1> When WTIM0 = 0 (SVA0 match after restart) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 1: IICS0 = 0010×010B...
Page 324 C BUS MODE ( µ PD784225Y SUBSERIES ONLY) CHAPTER 18 I (c) Start - Code - Data - Start - Code - Data - Stop <1> When WTIM0 = 0 (extended code received after restart) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0 1: IICS0 = 0010×010B...
Page 325 C BUS MODE ( µ PD784225Y SUBSERIES ONLY) CHAPTER 18 I (d) Start - Code - Data - Start - Address - Data - Stop <1> When WTIM0 = 0 (no address match after restart (not an extended code)) AD6 to AD0 D7 to D0 AD6 to AD0 D7 to D0...
Page 326 C BUS MODE ( µ PD784225Y SUBSERIES ONLY) CHAPTER 18 I (5) Arbitration failed operation (operates as the slave after arbitration fails) (a) When arbitration failed during the transfer of slave address data <1> When WTIM0 = 0 AD6 to AD0 D7 to D0 D7 to D0 1: IICS0 = 0101×110B (Example: Read ALD0 during interrupt servicing.)
Page 327 C BUS MODE ( µ PD784225Y SUBSERIES ONLY) CHAPTER 18 I (b) When arbitration failed while transmitting an extended code <1> When WTIM0 = 0 AD6 to AD0 D7 to D0 D7 to D0 1: IICS0 = 0110×010B (Example: Read ALD0 during interrupt servicing.) 2: IICS0 = 0010×000B 3: IICS0 = 0010×000B 4: IICS0 = 00000001B...
Page 328 C BUS MODE ( µ PD784225Y SUBSERIES ONLY) CHAPTER 18 I (6) Arbitration failed operation (no participation after arbitration failed) (a) When arbitration failed while transmitting slave address data AD6 to AD0 D7 to D0 D7 to D0 1: IICS0 = 01000110B (Example: Read ALD0 during interrupt servicing.) 2: IICS0 = 00000001B Remarks : Always generated.
Page 329 C BUS MODE ( µ PD784225Y SUBSERIES ONLY) CHAPTER 18 I (c) When arbitration failed during a data transfer <1> When WTIM0 = 0 AD to D0 D7 to D0 D7 to D0 1: IICS0 = 10001110B 2: IICS0 = 01000000B (Example: Read ALD0 during interrupt servicing.) 3: IICS0 = 00000001B Remarks : Always generated.
Page 330 C BUS MODE ( µ PD784225Y SUBSERIES ONLY) CHAPTER 18 I (d) When failed in the restart condition during a data transfer <1> Not an extended code (Example: SVA0 does not match) AD6 to AD0 D7 to Dn AD6 to D0 D7 to D0 1: IICS0 = 1000×110B 2: IICS0 = 01000110B (Example: Read ALD0 during interrupt servicing.)
Page 331 C BUS MODE ( µ PD784225Y SUBSERIES ONLY) CHAPTER 18 I (e) When failed in the stop condition during a data transfer AD6 to AD0 D7 to Dn 1: IICS0 = 1000×110B 2: IICS0 = 01000001B Remarks : Always generated. : Generated only when SPIE0 = 1 ×: don’t care Dn = D6 to D0...
Page 332 C BUS MODE ( µ PD784225Y SUBSERIES ONLY) CHAPTER 18 I (h) When arbitration failed in the low data level and the stop condition was about to be generated WTIM0 = 1 SPT0 = 1 AD6 to AD0 D7 to D0 D7 to D0 D7 to D0 1: IICS0 = 1000×110B...
Page 333 C BUS MODE ( µ PD784225Y SUBSERIES ONLY) CHAPTER 18 I 18.5.8 Interrupt request (INTIIC0) generation timing and wait control By setting the WTIM0 bit in I C bus control register 0 (IICC0), INTIIC0 is generated at the timing shown in Table 18-2 and wait control is performed.
Page 334 C BUS MODE ( µ PD784225Y SUBSERIES ONLY) CHAPTER 18 I 18.5.9 Address match detection In the I C bus mode, the master can select a specific slave device by transmitting the slave address. Address matching can be detected automatically by the hardware. When the base address is set in slave address register 0 (SVA0), if the slave address transmitted from the master matches the address set in SVA0, or if the extended code is received, an INTIIC0 interrupt request occurs.
Page 335 C BUS MODE ( µ PD784225Y SUBSERIES ONLY) CHAPTER 18 I 18.5.11 Extended codes (1) If the most significant four bits of the receiving address are “0000” or “1111”, an extended code is received and the extended code received flag (EXC0) is set. The interrupt request (INTIIC0) is generated at the falling edge of the eighth clock.
Page 336 C BUS MODE ( µ PD784225Y SUBSERIES ONLY) CHAPTER 18 I Figure 18-14. Example of Arbitration Timing Master 1 Hi-Z SCL0 Hi-Z SDA0 Master 1 arbitration failed Master 2 SCL0 SDA0 Transfer lines SCL0 SDA0 Table 18-4. Arbitration Generation States and Interrupt Request Generation Timing Arbitration Generation State Interrupt Request Generation Timing Note 1...
Page 337 C BUS MODE ( µ PD784225Y SUBSERIES ONLY) CHAPTER 18 I 18.5.13 Wake-up function This is a slave function of the I C bus and generates the interrupt request (INTIIC0) when the base address and extended code were received. When the address does not match, an unused interrupt request is not generated, and efficient processing is possible.
Page 338 C BUS MODE ( µ PD784225Y SUBSERIES ONLY) CHAPTER 18 I 18.5.14 Communication reservation When you want the master to communicate after being in the not participating state in the bus, the start condition can be transmitted when a bus is released by reserving communication. The following two states are included when the bus does not participate.
Page 339 C BUS MODE ( µ PD784225Y SUBSERIES ONLY) CHAPTER 18 I Figure 18-15 shows the timing of communication reservation. Figure 18-15. Timing of Communication Reservation STT0 Program processing IIC0 write Communi- SPD0 and STD0 cation Hardware processing INTIIC0 reserva- setting settings tion SCL0...
Page 340 C BUS MODE ( µ PD784225Y SUBSERIES ONLY) CHAPTER 18 I Figure 18-17 shows the communication reservation procedure. Figure 18-17. Communication Reservation Procedure SET1 STT0 ; Set the STT0 flag (communication reservation). Define communication ; Define that communication is being reserved. reservation.
Page 341 C BUS MODE ( µ PD784225Y SUBSERIES ONLY) CHAPTER 18 I 18.5.15 Additional warnings After a reset, when the master is communicating from the state where the stop condition is not detected (bus is not released), perform master communication after the stop condition is first generated and the bus is released. The master cannot communicate in the state where the bus is not released (the stop condition is not detected) in the multimaster.
Page 342 C BUS MODE ( µ PD784225Y SUBSERIES ONLY) CHAPTER 18 I 18.5.16 Communication operation (1) Master operation The following example shows the master operating procedure. Figure 18-18. Master Operating Procedure START IICCL0 ← ××H Select the transfer clock IICC0 ← ××H IICE0 = SPIE0 = WTIM0 =1 STT0 = 1 INTIIC0 = 1 ?
Page 343 C BUS MODE ( µ PD784225Y SUBSERIES ONLY) CHAPTER 18 I (2) Slave operation The following example is the slave operating procedure. Figure 18-19. Slave Operating Procedure START IICC0 ← ××H IICE0 = 1 INTIIC0 = 1 ? EXC0 = 1 ? Participate in communication ? COI0 = 1 ?
Page 344 C BUS MODE ( µ PD784225Y SUBSERIES ONLY) CHAPTER 18 I 18.6 Timing Charts In the I C bus mode, the master outputs an address on the serial bus and selects one of the slave devices from multiple slave devices as the communication target. The master transmits the TRC0 bit, bit 3 of I C bus status register 0 (IICS0), that indicates the transfer direction of the data after the slave address and starts serial communication with the slave.
Page 345 C BUS MODE ( µ PD784225Y SUBSERIES ONLY) CHAPTER 18 I Figure 18-20. Master → Slave Communication Example (When Master and Slave Select 9 Clock Waits) (1/3) (1) Start condition - Address Master device process IIC0 ← Address IIC0 ← Data IIC0 ACKD0 STD0...
Page 346 C BUS MODE ( µ PD784225Y SUBSERIES ONLY) CHAPTER 18 I Figure 18-20. Master → Slave Communication Example (When Master and Slave Select 9 Clock Waits) (2/3) (2) Data Master device process IIC0 ← Data IIC0 ← Data IIC0 ACKD0 STD0 SPD0 WTIM0...
Page 347 C BUS MODE ( µ PD784225Y SUBSERIES ONLY) CHAPTER 18 I Figure 18-20. Master → Slave Communication Example (When Master and Slave Select 9 Clock Waits) (3/3) (3) Stop condition Master device process IIC0 ← Data IIC0 ← Address IIC0 ACKD0 STD0 SPD0...
Page 348 C BUS MODE ( µ PD784225Y SUBSERIES ONLY) CHAPTER 18 I Figure 18-21. Slave → Master Communication Example (When Master and Slave Select 9 Clock Waits) (1/3) (1) Start condition - Address Master device process IIC0 ← Address IIC0 ← FFH IIC0 Note ACKD0...
Page 349 C BUS MODE ( µ PD784225Y SUBSERIES ONLY) CHAPTER 18 I Figure 18-21. Slave → Master Communication Example (When Master and Slave Select 9 Clock Waits) (2/3) (2) Data Master device process IIC0 ← FFH IIC0 ← FFH IIC0 Note Note ACKD0 STD0...
Page 350 C BUS MODE ( µ PD784225Y SUBSERIES ONLY) CHAPTER 18 I Figure 18-21. Slave → Master Communication Example (When Master and Slave Select 9 Clock Waits) (3/3) (3) Stop condition Master device process IIC0 IIC0 ← Address IIC0 ← FFH Note ACKD0 STD0...
Page 351 CHAPTER 19 CLOCK OUTPUT FUNCTION 19.1 Functions The clock output function is used to output the clock supplied to a peripheral LSI and carrier output during remote transmission. The clock selected by means of the clock output control register (CKS) is output from the PCL/P23 pin. To output the clock pulse, follow the procedure described below.
Page 352 CHAPTER 19 CLOCK OUTPUT FUNCTION 19.2 Configuration The clock output function includes the following hardware. Table 19-1. Configuration of Clock Output Function Item Configuration Control registers Clock output control register (CKS) Port 2 mode register (PM2) Figure 19-2. Block Diagram of Clock Output Function Synchronization PCL/P23 circuit...
Page 353 CHAPTER 19 CLOCK OUTPUT FUNCTION Figure 19-3. Format of Clock Output Control Register (CKS) Address: 0FF40H After reset: 00H Symbol BZOE BCS1 BCS0 CLOE CCS3 CCS2 CCS1 CCS0 BZOE Buzzer output control (Refer to Figure 20-2) BCS1 BCS0 Buzzer output frequency selection (Refer to Figure 20-2) CLOE Clock output control Clock output stop...
Page 354 CHAPTER 19 CLOCK OUTPUT FUNCTION (2) Port 2 mode register (PM2) This register sets input/output for port 2 in 1-bit units. When using the P23/PCL pin for clock output, set the output latch of PM23 and P23 to 0. PM2 is set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets PM2 to FFH.
Page 355 CHAPTER 20 BUZZER OUTPUT FUNCTIONS 20.1 Function This function outputs a square wave at the frequencies of 1.5 kHz, 3.1 kHz, 6.1 kHz, and 12.2 kHz. The buzzer frequency selected by the clock output control register (CKS) is output from the BUZ/P24 pin. The following procedure outputs the buzzer frequency.
Page 356 CHAPTER 20 BUZZER OUTPUT FUNCTIONS 20.3 Control Registers The buzzer output function is controlled by the following two registers. • Clock output control register (CKS) • Port 2 mode register (PM2) (1) Clock output control register (CKS) This register sets the frequency of the buzzer output. CKS is set by a 1-bit or 8-bit memory manipulation instruction.
Page 357 CHAPTER 20 BUZZER OUTPUT FUNCTIONS (2) Port 2 mode register (PM2) This register sets port 2 I/O in 1-bit units. When the P24/BUZ pin is used as the buzzer output function, set the output latches of PM24 and P24 to 0. PM2 is set by a 1-bit or 8-bit memory manipulation instruction.
Page 358 CHAPTER 21 EDGE DETECTION FUNCTION The P00 to P05 pins have an edge detection function that can be programmed to detect the rising edge or falling edge and sends the detected edge to on-chip hardware components. The edge detection function is always functioning, even in the STOP mode and IDLE mode. 21.1 Control Registers •...
Page 359 CHAPTER 21 EDGE DETECTION FUNCTION 21.2 Edge Detection of P00 to P05 Pins The P00 to P05 pins do not incorporate an analog delay-based noise eliminator. Therefore, a valid edge is input to the pins and edge detection is performed (acknowledged) immediately after passing through the hysteresis-type input buffer.
Page 360 CHAPTER 22 INTERRUPT FUNCTIONS The µ PD784225 is provided with three interrupt request service modes (refer to Table 22-1). These three service modes can be set as required in the program. However interrupt service by macro service can only be selected for interrupt request sources provided with the macro service processing mode shown in Table 22-2.
Page 361 CHAPTER 22 INTERRUPT FUNCTIONS 22.1 Interrupt Request Sources The µ PD784225 has the 28 interrupt request sources shown in Table 22-2, with a vector table allocated to each. Table 22-2. Interrupt Request Sources (1/2) Macro Interrupt Type of Service Vector Default Interrupt Request Generating Control...
Page 362 CHAPTER 22 INTERRUPT FUNCTIONS Table 22-2. Interrupt Request Sources (2/2) Macro Interrupt Type of Service Vector Default Interrupt Request Generating Control Context Macro Interrupt Control Table Priority Generating Source Unit Register Switching Service Request Word Address Name Address Watchdog timer overflow) Watchdog WDTIC Possible...
Page 363 CHAPTER 22 INTERRUPT FUNCTIONS Remarks 1. The default priority is a fixed number. This indicates the order of priority when interrupt requests specified as having the same priority are generated simultaneously. 2. ASI: Asynchronous serial interface CSI: Clocked serial interface 3.
Page 364 CHAPTER 22 INTERRUPT FUNCTIONS 22.2 Interrupt Servicing Modes There are three µ PD784225 interrupt servicing modes, as follows: • Vectored interrupt servicing • Macro servicing • Context switching 22.2.1 Vectored interrupt servicing When an interrupt is acknowledged, the program counter (PC) and program status word (PSW) are automatically saved to the stack, a branch is made to the address indicated by the data stored in the vector table, and the interrupt service routine is executed.
Page 365 CHAPTER 22 INTERRUPT FUNCTIONS 22.3 Interrupt Servicing Control Registers µ PD784225 interrupt servicing is controlled for each interrupt request by various control registers that perform interrupt servicing specification. The interrupt control registers are listed in Table 22-3. Table 22-3. Control Registers Register Name Symbol Function...
Page 366 CHAPTER 22 INTERRUPT FUNCTIONS Table 23-4. Flag List of Interrupt Control Registers for Interrupt Requests Interrupt Control Register Interrupt Default Request Interrupt Interrupt Macro Service Priority Speci- Context Switching Priority Signal Request Flag Mask Flag Enable Flag fication Flag Enable Flag INTWDTM WDTIC WDTIF...
Page 367 CHAPTER 22 INTERRUPT FUNCTIONS 22.3.1 Interrupt control registers An interrupt control register is allocated to each interrupt source, and performs priority control, mask control, etc., for the corresponding interrupt request. The interrupt control register format is shown in Figure 22-1. (1) Priority specification flags (××PR1/××PR0) The priority specification flags specify the priority on an individual interrupt source basis for the 23 maskable interrupts.
Page 368 CHAPTER 22 INTERRUPT FUNCTIONS Figure 22-1. Interrupt Control Register (xxICn) (1/3) After reset: 43H Address: 0FFE0H to 0FFE6H, 0FFE8H Symbol WDTIC WDTIF WDTISM WDTMK WDCSE WDTPR1 WDTPR0 PIC0 PIF0 PMK0 PCSE0 PPR01 PPR00 PISM0 PIC1 PIF1 PMK1 PISM1 PCSE1 PPR11 PPR10 PIC2 PIF2...
Page 369 CHAPTER 22 INTERRUPT FUNCTIONS Figure 22-1. Interrupt Control Register (xxICn) (2/3) After reset: 43H Address: 0FFE9H to 0FFF1H Symbol SERIC1 SERIF1 SERISM1 SERCSE1 SERMK1 SERPR11 SERPR10 SRIC1 SRIF1 SRMK1 SRCSE1 SRPR11 SRPR10 SRISM1 STIC1 STIF1 STMK1 STCSE1 STPR11 STPR10 STISM1 SERIC2 SERIF2 SERMK2...
Page 370 CHAPTER 22 INTERRUPT FUNCTIONS Figure 22-1. Interrupt Control Register (xxICn) (3/3) Address: 0FFF2H to 0FFF6H, 0FFF9H After reset: 43H Symbol TMIC1 TMIF1 TMMK1 TMISM1 TMCSE1 TMPR11 TMPR10 TMIC2 TMIF2 TMMK2 TMISM2 TMCSE2 TMPR21 TMPR20 ADIC ADIF ADMK ADCSE ADPR01 ADPR00 ADISM TMIC5 TMIF5...
Page 371 CHAPTER 22 INTERRUPT FUNCTIONS 22.3.2 Interrupt mask registers (MK0, MK1) The MK0 and MK1 are composed of interrupt mask flags. MK0 and MK1 are 16-bit registers which can be manipulated as a 16-bit unit. MK0 can be manipulated in 8-bit units using MK0L and MK0H, and similarly MK1 can be manipulated using MK1L and MK1H.
Page 372 CHAPTER 22 INTERRUPT FUNCTIONS Figure 22-2. Format of Interrupt Mask Registers (MK0, MK1) <Byte access> After reset: FFH Address: 0FFACH to 0FFAFH Symbol MK0L PMK5 PMK4 PMK3 PMK2 PMK1 PMK0 WDTMK MK0H TMMK3 STMK2 SERMK2 SRMK2 STMK1 SRMK1 SERMK1 CSIMK0 MK1L TMMK6 ADMK...
Page 373 CHAPTER 22 INTERRUPT FUNCTIONS 22.3.3 In-service priority register (ISPR) The ISPR shows the priority level of the maskable interrupt currently being serviced and the non-maskable interrupt being processed. When a maskable interrupt request is acknowledged, the bit corresponding to the priority of that interrupt request is set (1), and remains set until the service program ends.
Page 374 CHAPTER 22 INTERRUPT FUNCTIONS 22.3.4 Interrupt mode control register (IMC) IMC contains the PRSL flag. The PRSL flag specifies enabling/disabling of nesting of maskable interrupts for which the lowest priority level (level 3) is specified. When the IMC is manipulated, the interrupt disabled state (DI state) should be set first to prevent misoperation. IMC can be read or written to with an 8-bit manipulation instruction or bit manipulation instruction.
Page 375 If recovery from an operand error is simply performed by means of an RETB instruction, an endless loop will result. As an operand error interrupt is only generated in the event of an inadvertent program loop (with the NEC assembler, RA78K4, only the correct dedicated instruction is generated when MOV WDM, #byte is written), system initialization should be performed by the program.
Page 376 CHAPTER 22 INTERRUPT FUNCTIONS 22.3.6 Interrupt selection control register (SNMI) SNMI selects whether to use and interrupt request signals from the watchdog timer inputs from the P02 pin as maskable interrupt signals or non-maskable interrupts. Since the bit of this register can be set (1) only once after reset, the bit should be cleared (0) by reset. SNMI is set with a 1-bit or 8-bit memory manipulation instruction.
Page 377 CHAPTER 22 INTERRUPT FUNCTIONS 22.3.7 Program status word (PSW) The PSW is a register that holds the current status regarding instruction execution results and interrupt requests. The IE flag that sets enabling/disabling of maskable interrupts is mapped in the lower 8 bits of the PSW (PSWL). PSWL can be read or written to with an 8-bit manipulation instruction, and can also be manipulated with a bit manipulation instruction or dedicated instruction (EI/DI).
Page 378 CHAPTER 22 INTERRUPT FUNCTIONS 22.4 Software Interrupt Acknowledgment Operations A software interrupt is acknowledged in response to execution of a BRK or BRKCS instruction. Software interrupts cannot be disabled. 22.4.1 BRK instruction software interrupt acknowledgment operation When a BRK instruction is executed, the program status word (PSW) and program counter (PC) are saved in that order to the stack, the IE flag is cleared (0), the vector table (003EH/003FH) contents are loaded into the lower 16 bits of the PC, and 0000B into the higher 4 bits, and a branch is performed (the start of the service program must be in the base area).
Page 379 CHAPTER 22 INTERRUPT FUNCTIONS Figure 22-9. Return from BRKCS Instruction Software Interrupt (RETCSB Instruction Operation) Register bank n (n = 0 to 7) 19-16 15-0 1 Restoration RETCSB instruction operand 2 Restoration 3 Transfer 4 Restoration (To original register bank) 22.5 Operand Error Interrupt Acknowledgement Operation An operand error interrupt is generated when the data obtained by inverting all the bits of the 3rd byte of the operand of an MOV STBC, #byte instruction or LOCATION instruction or an MOV WDM,#byte instruction does not match the...
Page 380 CHAPTER 22 INTERRUPT FUNCTIONS 22.6 Non-Maskable Interrupt Acknowledgment Operation Non-maskable interrupts are acknowledged even in the interrupt disabled state. Non-maskable interrupts can be acknowledged at all times except during execution of the service program for an identical non-maskable interrupt or a non-maskable interrupt of higher priority.
Page 381 CHAPTER 22 INTERRUPT FUNCTIONS Figure 22-10. Non-Maskable Interrupt Request Acknowledgment Operations (1/2) (a) When a new NMI request is generated during NMI service program execution Main routine (NMIS = 1) NMI request NMI request held pending since NMIS = 1 NMI request Pending NMI request is serviced (b) When a watchdog timer interrupt request is generated during NMI service program execution (when...
Page 382 CHAPTER 22 INTERRUPT FUNCTIONS Figure 22-10. Non-Maskable Interrupt Request Acknowledgment Operations (2/2) (c) When a watchdog timer interrupt request is generated during NMI service program execution (when the NMI interrupt priority is higher (when WDT4 in the WDM = 0)) Main routine Watchdog Watchdog timer interrupt is kept...
Page 383 CHAPTER 22 INTERRUPT FUNCTIONS Cautions 1. Macro service requests are acknowledged and serviced even during execution of a non- maskable interrupt service program. If you do not want macro service processing to be performed during a non-maskable interrupt service program, you should manipulate the interrupt mask register in the non-maskable interrupt service program to prevent macro service generation.
Page 384 CHAPTER 22 INTERRUPT FUNCTIONS 22.7 Maskable Interrupt Acknowledgment Operation A maskable interrupt can be acknowledged when the interrupt request flag is set (1) and the mask flag for that interrupt is cleared (0). When servicing is performed by macro service, the interrupt is acknowledged and serviced by macro service immediately.
Page 385 CHAPTER 22 INTERRUPT FUNCTIONS Figure 22-11. Interrupt Acknowledgment Processing Algorithm ××IF = 1 Interrupt request? ××MK = 0 Interrupt mask released? ××ISM = 1 Macro service? Highest default priority among IE = 1 macro service Interrupt enabled state? requests? Higher priority Macro service than interrupt currently processing execution...
Page 386 CHAPTER 22 INTERRUPT FUNCTIONS 22.7.1 Vectored interrupt When a vectored interrupt maskable interrupt request is acknowledged, the program status word (PSW) and program counter (PC) are saved in that order to the stack, the IE flag is cleared (0) (the interrupt disabled status is set), and the in-service priority register (ISPR) bit corresponding to the priority of the acknowledged interrupt is set (1).
Page 387 CHAPTER 22 INTERRUPT FUNCTIONS The RETCS instruction is used to return from an interrupt that uses the context switching function. The RETCS instruction must specify the start address of the interrupt service program to be executed when that interrupt is acknowledged next.
Page 388 CHAPTER 22 INTERRUPT FUNCTIONS 22.7.3 Maskable interrupt priority levels The µ PD784225 performs multiple interrupt servicing in which an interrupt is acknowledged during servicing of another interrupt. Multiple interrupts can be controlled by priority levels. There are two kinds of priority control, control by default priority and programmable priority control in accordance with the setting of the priority specification flag.
Page 389 CHAPTER 22 INTERRUPT FUNCTIONS Figure 22-14. Examples of Servicing When Another Interrupt Request Is Generated During Interrupt Service (1/3) Main routine a servicing b servicing Interrupt request a Interrupt (Level 3) request b Since interrupt request b has a higher (Level 2) priority than interrupt request a, and interrupts are enabled, interrupt...
Page 390 CHAPTER 22 INTERRUPT FUNCTIONS Figure 22-14. Examples of Servicing When Another Interrupt Request Is Generated During Interrupt Service (2/3) Main routine i servicing Interrupt request i Macro service j macro service (Level 1) request j The macro service request is (Level 2) serviced irrespective of interrupt enabling/disabling and priority.
Page 391 CHAPTER 22 INTERRUPT FUNCTIONS Figure 22-14. Examples of Servicing When Another Interrupt Request Is Generated During Interrupt Service (3/3) Main routine q servicing r servicing s servicing Interrupt Interrupt request q t servicing request r Interrupt (Level 3) Interrupt (Level 2) request s request t Multiple acknowledgment of levels 3 to 0.
Page 392 CHAPTER 22 INTERRUPT FUNCTIONS Figure 22-15. Examples of Servicing of Simultaneously Generated Interrupts Request Main routine Interrupt request a (Level 2) Macro service request b servicing • When requests are generated Macro service request b (Level 3) simultaneously, they are Macro service request c (Level 1) Macro service request c servicing acknowledged in order starting...
Page 393 CHAPTER 22 INTERRUPT FUNCTIONS Figure 22-16. Differences in Level 3 Interrupt Acknowledgment According to IMC Register Setting Main routine The PRSL bit of the IMC is set to 1, and nesting between level 3 interrupts is IMC ← 80H disabled. a servicing Interrupt request a Interrupt...
Page 394 CHAPTER 22 INTERRUPT FUNCTIONS 22.8 Macro Service Function 22.8.1 Outline of macro service function Macro service is one method of servicing interrupts. With a normal interrupt, the program counter (PC) and program status word (PSW) are saved, and the start address of the interrupt service program is loaded into the PC, but with macro service, different processing (mainly data transfers) is performed instead of this processing.
Page 395 CHAPTER 22 INTERRUPT FUNCTIONS Table 22-6. Interrupts for Which Macro Service Can Be Used Default Macro Service Control Interrupt Request Generation Source Generating Unit Priority Word Address INTWDTM (Watchdog timer overflow) Watchdog timer 0FE06H INTP0 (Pin input edge detection) Edge detection 0FE08H INTP1 (Pin input edge detection) 0FE0AH...
Page 396 CHAPTER 22 INTERRUPT FUNCTIONS There are four kinds of macro service, as shown below. (1) Type A One byte or one word of data is transferred between a special function register (SFR) and memory each time an interrupt request is generated, and a vectored interrupt request is generated when the specified number of transfers have been performed.
Page 397 CHAPTER 22 INTERRUPT FUNCTIONS 22.8.3 Basic macro service operation Interrupt requests for which the macro service processing generated by the algorithm shown in Figure 22-11 can be specified are basically serviced in the sequence shown in Figure 22-18. Interrupt requests for which macro service processing can be specified are not affected by the status of the IE flag, but are disabled by setting (1) an interrupt mask flag in the interrupt mask register (MK0).
Page 398 CHAPTER 22 INTERRUPT FUNCTIONS 22.8.4 Operation at end of macro service In macro service, processing is performed the number of times specified during execution of another program. Macro service ends when the processing has been performed the specified number of times (when the macro service counter (MSC) reaches 0).
Page 399 CHAPTER 22 INTERRUPT FUNCTIONS Figure 22-19. Operation at End of Macro Service When VCIE = 0 Main routine Macro service request Macro service processing Last macro service request At the end of macro service Macro service processing (MSC = 0), an interrupt Servicing of interrupt request request is generated and due to end of macro service...
Page 400 CHAPTER 22 INTERRUPT FUNCTIONS (2) When VCIE bit is 1 In this mode, an interrupt is not generated after macro service ends. Figure 22-20 shows an example of macro service and interrupt acknowledgment operations when the VCIE bit is 1. This mode is used when the final operation is to be started by the last macro service processing performed, for instance.
Page 401 CHAPTER 22 INTERRUPT FUNCTIONS 22.8.5 Macro service control registers (1) Macro service control word The µ PD784225’s macro service function is controlled by the macro service control mode register and macro service channel pointer. The macro service processing mode is set by means of the macro service mode register, and the macro service channel address is indicated by the macro service channel pointer.
Page 402 CHAPTER 22 INTERRUPT FUNCTIONS Figure 22-21. Format of Macro Service Control Word Address Cause Channel pointer 0FE39H INTWT 0FE38H Mode register Channel pointer 0FE33H INTTM6 0FE32H Mode register Channel pointer 0FE31H INTTM5 0FE30H Mode register Channel pointer 0FE2FH INTAD 0FE2EH Mode register Channel pointer 0FE2DH...
Page 403 CHAPTER 22 INTERRUPT FUNCTIONS (2) Macro service mode register The macro service mode register is an 8-bit register that specifies the macro service operation. This register is written in internal RAM as part of the macro service control word (refer to Figure 22-21). The format of the macro service mode register is shown in Figure 22-22.
Page 404 CHAPTER 22 INTERRUPT FUNCTIONS Figure 22-22. Format of Macro Service Mode Register (2/2) VCIE MOD2 MOD1 MOD0 CHT3 CHT2 CHT1 CHT0 CHT0 CHT1 CHT2 CHT3 MOD2 MOD1 MOD0 Type C Decrements MPD Increments MPD Retains MPT Decrements MPT Retains MPT Increments MPT Data size for timer No automatic...
Page 405 CHAPTER 22 INTERRUPT FUNCTIONS 22.8.6 Macro service type A (1) Operation Data transfers are performed between buffer memory in the macro service channel and an SFR specified in the macro service channel. With type A, the data transfer direction can be selected as memory-to-SFR or SFR-to-memory. Data transfers are performed the number of times set beforehand in the macro service counter.
Page 406 CHAPTER 22 INTERRUPT FUNCTIONS Figure 22-23. Macro Service Data Transfer Processing Flow (Type A) Macro service request acknowledgment Read contents of macro service mode register Other Determine channel type To other macro service processing TYPE A Read channel pointer contents (m) Read MSC contents (n) Note 1-byte transfer: m –...
Page 407 CHAPTER 22 INTERRUPT FUNCTIONS (2) Macro service channel configuration The channel pointer and 8-bit macro service counter (MSC) indicate the buffer address in internal RAM (FE00H to FEFFH when the LOCATION 0H instruction is executed, or FFE00H to FFEFFH when the LOCATION 0FH instruction is executed) which is the transfer source or transfer destination (refer to Figure 22-24).
Page 408 CHAPTER 22 INTERRUPT FUNCTIONS Figure 22-24. Type A Macro Service Channel (a) 1-byte transfers  Higher addresses Macro service counter (MSC)   SFR pointer (SFRP)   Macro service buffer 1  MSC = 1  Macro service Macro service buffer 2 ...
Page 409 CHAPTER 22 INTERRUPT FUNCTIONS (3) Example of use of type A An example is shown below in which data received via the asynchronous serial interface is transferred to a buffer area in internal RAM. Figure 22-25. Asynchronous Serial Reception (Internal RAM) –1 0FE7FH MSC 0EH...
Page 410 CHAPTER 22 INTERRUPT FUNCTIONS 22.8.7 Macro service type B (1) Operation Data transfers are performed between a data area in memory and an SFR specified by the macro service channel. With type B, the data transfer direction can be selected as memory-to-SFR or SFR-to-memory. Data transfers are performed the number of times set beforehand in the macro service counter.
Page 411 CHAPTER 22 INTERRUPT FUNCTIONS Figure 22-26. Macro Service Data Transfer Processing Flow (Type B) Macro service request acknowledgment Read contents of macro service mode register Other Determine channel type To other macro service processing TYPE B Read channel pointer contents (m) Memory →...
Page 412 CHAPTER 22 INTERRUPT FUNCTIONS (2) Macro service channel configuration The macro service pointer (MP) indicates the data buffer area in the 1 MB memory space that is the transfer destination or transfer source. The lower 8 bits of the SFR that is the transfer destination or transfer source is written to the SFR pointer (SFRP). The macro service counter (MSC) is a 16-bit counter that specifies the number of data transfers.
Page 413 CHAPTER 22 INTERRUPT FUNCTIONS (3) Example of use of type B An example is shown below in which parallel data is input from port 3 in synchronization with an external signal. The INTP4 external interrupt pin is used for synchronization with the external signal. Figure 22-28.
Page 414 CHAPTER 22 INTERRUPT FUNCTIONS Figure 22-29. Parallel Data Input Timing Port 3 INTP4 Data fetch (macro service) User’s Manual U12697EJ3V0UM...
Page 415 CHAPTER 22 INTERRUPT FUNCTIONS 22.8.8 Macro service type C (1) Operation In type C macro service, data in the memory specified by the macro service channel is transferred to two SFRs, for timer use and data use, specified by the macro service channel in response to a single interrupt request (the SFRs can be freely selected).
Page 416 CHAPTER 22 INTERRUPT FUNCTIONS Figure 22-30. Macro Service Data Transfer Processing Flow (Type C) (1/2) Macro service request acknowledgment Read contents of macro service mode register Other Determine channel type To other macro service processing TYPE C Read channel pointer contents (m) Read memory addressed by MPT Automatic addition specified? Transfer data to compare register...
Page 417 CHAPTER 22 INTERRUPT FUNCTIONS Figure 22-30. Macro Service Data Transfer Processing Flow (Type C) (2/2) Ring control? Decrement ring counter Ring counter = 0? Increment MPD? Subtract modulo register Add modulo register contents contents from data macro to data macro service pointer service pointer (MPD), and (MPD), and return pointer to return pointer to start address...
Page 418 CHAPTER 22 INTERRUPT FUNCTIONS (2) Macro service channel configuration There are two kinds of type C macro service channel, as shown in Figure 22-31. The timer macro service pointer (MPT) mainly indicates the data buffer area in the 1 MB memory space to be transferred or added to the timer/counter compare register.
Page 419 CHAPTER 22 INTERRUPT FUNCTIONS Figure 22-31. Type C Macro Service Channel (1/2) (a) No ring control Higher addresses TSFR (Bits 8 to 15) Macro service counter (MSC) (Bits 0 to 7) Timer SFR pointer (TSFRP) DSFR Note (Bits 16 to 23) Timer buffer area Timer macro service (Bits 8 to 15)
Page 420 CHAPTER 22 INTERRUPT FUNCTIONS Figure 22-31. Type C Macro Service Channel (2/2) (b) With ring control Higher addresses TSFR (Bits 8 to 15) Macro service counter (MSC) (Bits 0 to 7) DSFR Timer SFR pointer (TSFRP) Note (Bits 16 to 23) Timer buffer area Timer macro service (Bits 8 to 15)
Page 421 CHAPTER 22 INTERRUPT FUNCTIONS Figure 22-32. Stepper Motor Open Loop Control by Real-Time Output Port Macro service control word, macro service channel 1 MB memory space (Internal RAM) –1 123411H 0FE5EH TSFRP Lower 8 bits Output timing of CR10 address data area 123409H 123408H...
Page 422 CHAPTER 22 INTERRUPT FUNCTIONS Figure 22-33. Data Transfer Control Timing Count value Count starts INTTM1 Timer interrupt Compare register (CR10) Buffer register RTBL P120 P121 P122 P123 User’s Manual U12697EJ3V0UM...
Page 423 CHAPTER 22 INTERRUPT FUNCTIONS (b) Examples of use of automatic addition control and ring control (i) Automatic addition control The output timing data (∆t) specified by the macro service pointer (MPT) is added to the contents of the compare register, and the result is written back to the compare register. Use of this automatic addition control eliminates the need to calculate the compare register setting value in the program each time.
Page 424 CHAPTER 22 INTERRUPT FUNCTIONS Figure 22-34. Single-Phase Excitation of 4-Phase Stepper Motor Phase A Phase B Phase C Phase D 1 cycle (4 patterns) Figure 22-35. 1-2-Phase Excitation of 4-Phase Stepper Motor Phase A Phase B Phase C Phase D 1 cycle (8 patterns) User’s Manual U12697EJ3V0UM...
Page 425 CHAPTER 22 INTERRUPT FUNCTIONS Figure 22-36. Automatic Addition Control + Ring Control Block Diagram 1 (When Output Timing Varies with 1-2-Phase Excitation) Macro service control word, macro service channel (Internal RAM) 1M memory space 1237FEH –1 t256 1237FCH 0FE5AH TSFRP Lower 8 bits of CR00 address 123402H Output timing: 123400H...
Page 426 CHAPTER 22 INTERRUPT FUNCTIONS Figure 22-37. Automatic Addition Control + Ring Control Timing Diagram 1 (When Output Timing Varies with 1-2-Phase Excitation) FFFFH ∆t7 ∆t6 ∆t5 ∆t4 TM1W ∆t3 Count value ∆t2 ∆t1 ∆t9 ∆t ∆t8 Count starts INTP2 (TO0) Compare register (CR1W) T0 + ∆t...
Page 427 CHAPTER 22 INTERRUPT FUNCTIONS Figure 22-38. Automatic Addition Control + Ring Control Block Diagram 2 (1-2-Phase Excitation Constant-Velocity Operation) Macro service control word, Macro service channel (Internal RAM) 1M memory space Output timing: 1233FFH 0FE7AH TSFRP Lower 8 bits of CR00 address 123007H Output data (8 Items) DSFRP...
Page 428 CHAPTER 22 INTERRUPT FUNCTIONS Figure 22-39. Automatic Addition Control + Ring Control Timing Diagram 2 (1-2-Phase Excitation Constant-Velocity Operation) FFFFH Count value ∆t Count starts INTTP2 (TO0) Compare register (CR10) T0+∆t T1+∆t T2+∆t T3+∆t T4+∆t T5+∆t T6+∆t T7+∆t T8+∆t T9+∆t Buffer register RTBL P120...
Page 429 CHAPTER 22 INTERRUPT FUNCTIONS 22.8.9 Counter mode (1) Operation MSC is decremented the number of times set in advance to the macro service counter (MSC). Because the number of times an interrupt occurs can be counted, this function can be used as an event counter where the interrupt generation cycle is long.
Page 430 CHAPTER 22 INTERRUPT FUNCTIONS (2) Configuration of macro service channel The macro service channel consists of only a 16-bit macro service counter (MSC). The lower 8 bits of the address of the MSC are written to the channel pointer. Figure 22-41. Counter Mode ...
Page 431 CHAPTER 22 INTERRUPT FUNCTIONS 22.9 When Interrupt Requests and Macro Service Are Temporarily Held Pending When the following instructions are executed, interrupt acknowledgment and macro service processing is deferred for 8 system clock cycles. However, software interrupts are not deferred. BRKCS RETCS RETCSB !addr16...
Page 432 CHAPTER 22 INTERRUPT FUNCTIONS 22.10 Instructions Whose Execution Is Temporarily Suspended by an Interrupt or Macro Service Execution of the following instructions is temporarily suspended by an acknowledgeable interrupt request or macro service request, and the interrupt or macro service request is acknowledged. The suspended instruction is resumed after completion of the interrupt service program or macro service processing.
Page 433 CHAPTER 22 INTERRUPT FUNCTIONS 22.11.1 Interrupt acknowledge processing time The time shown in Table 22-7 is required to acknowledge an interrupt request. After the time shown in this table has elapsed, execution of the interrupt processing program is started. Table 22-7. Interrupt Acknowledge Processing Time (Unit: Clock = 1/f Vector Table IROM...
Page 434 CHAPTER 22 INTERRUPT FUNCTIONS 22.11.2 Processing time of macro service Macro service processing time differs depending on the type of the macro service, as shown in Table 22-8. Table 22-8. Macro Service Processing Time (Units: Clock = 1/f Data Area Processing Type of Macro Service IRAM Others...
Page 435 CHAPTER 22 INTERRUPT FUNCTIONS 22.12 Restoring Interrupt Function to Initial State If an inadvertent program loop or system error is detected by means of an operand error interrupt, the watchdog timer, NMI pin input, etc., the entire system must be restored to its initial state. In the µ PD784225, interrupt acknowledgment related priority control is performed by hardware.
Page 436 CHAPTER 22 INTERRUPT FUNCTIONS 22.13 Cautions (1) The in-service priority register (ISPR) is read-only. Writing to this register may result in misoperation. (2) The watchdog timer mode register (WDM) can only be written to with a dedicated instruction (MOV WDM/#byte). (3) The RETI instruction must not be used to return from a software interrupt caused by a BRK instruction.
Page 437 CHAPTER 22 INTERRUPT FUNCTIONS (10) When the following instructions are executed, interrupt acknowledgement and macro service processing are held pending for 8 system clocks. However, software interrupts are not held. BRKCS RETCS RETCSB !addr16 RETI RETB LOCATION 0H or LOCATION 0FH POP PSW POPU post MOV PSWL, A...
Page 438 CHAPTER 23 LOCAL BUS INTERFACE FUNCTIONS 23.1 External Memory Expansion Function The external memory expansion function connects external memory to the areas other than the internal ROM, RAM, and SFR. A time-divided address/data bus is used to connect external memory. A 256-byte expansion mode and a 1 MB expansion mode are supported in the external memory expansion function.
Page 439 CHAPTER 23 LOCAL BUS INTERFACE FUNCTIONS 23.2 Control Registers (1) Memory expansion mode register (MM) MM is an 8-bit register that controls the external expanded memory, sets the number of address waits, and controls the internal fetch cycle. MM can be read or written by a 1-bit or 8-bit memory manipulation instruction. Figure 23-1 shows the MM format. RESET input sets MM to 20H.
Page 440 CHAPTER 23 LOCAL BUS INTERFACE FUNCTIONS (2) Programmable wait control register 1 (PWC1) PWC1 is an 8-bit register that sets the number of waits. The insertion of wait cycles is controlled by PWC1 over the entire space. PWC1 can be read and written by a 1-bit or 8-bit memory manipulation instruction. RESET input sets PWC1 to AAH.
Page 441 CHAPTER 23 LOCAL BUS INTERFACE FUNCTIONS 23.3 Memory Map for External Memory Expansion Figures 23-4 and 23-5 show the memory map during memory expansion. Even during memory expansion, an external device at the same address as the internal ROM area, internal RAM area, or SFR area (except for the external SFR area (0FFD0H to 0FFDFH)) cannot be accessed.
Page 442 CHAPTER 23 LOCAL BUS INTERFACE FUNCTIONS Figure 23-3. µ PD784224 Memory Map (1/2) (a) When executing the LOCATION 0H instruction F F F F F H Note 1 External memory External memory 1 7 F F F H Internal ROM Internal ROM Internal ROM 1 0 0 0 0 H...
Page 443 CHAPTER 23 LOCAL BUS INTERFACE FUNCTIONS Figure 23-3. µ PD784224 Memory Map (2/2) (b) When executing the LOCATION 0FH instruction FFFFFH FFFE0H Note 2 Note 2 External memory FFFCFH Internal RAM Internal RAM Internal RAM F F 1 0 0 H Note 1 External memory External memory...
Page 444 CHAPTER 23 LOCAL BUS INTERFACE FUNCTIONS Figure 23-4. µ PD784225 Memory Map (1/2) (a) When executing the LOCATION 0H instruction FFFFFH Note 1 External memory External memory 1 F F F F H Internal ROM Internal ROM Internal ROM 1 0 0 0 0 H 0 F F F F H 0 F F E 0 H Note 2...
Page 445 CHAPTER 23 LOCAL BUS INTERFACE FUNCTIONS Figure 23-4. µ PD784225 Memory Map (2/2) (b) When executing the LOCATION 0FH instruction FFFFFH FFFE0H Note 2 Note 2 External memory FFFCFH Internal RAM Internal RAM Internal RAM 0EE00H Note 1 External memory External memory 1FFFFH Internal ROM...
Page 446 CHAPTER 23 LOCAL BUS INTERFACE FUNCTIONS 23.4 Timing of External Memory Expansion Functions The timing control signal output pins in the external memory expansion mode are described below. (1) RD pin (shared by: P64) This pin outputs the read strobe during an instruction fetch or a data access from external memory. During an internal memory access, the read strobe is not output (held at the high level).
Page 447 CHAPTER 23 LOCAL BUS INTERFACE FUNCTIONS Figure 23-5. Instruction Fetch from External Memory in External Memory Expansion Mode (a) Setting 0 wait cycles (PW01, PW00 = 0, 0) ASTB AD0 to AD7 Lower address Instruction code A8 to A19 Higher address (b) Setting 1 wait cycle (PW01, PW00 = 0, 1) ASTB AD0 to AD7...
Page 448 CHAPTER 23 LOCAL BUS INTERFACE FUNCTIONS Figure 23-6. Read Timing for External Memory in External Memory Expansion Mode (a) Setting 0 wait cycles (PW01, PW00 = 0, 0) ASTB AD0 to AD7 Lower address Read data A8 to A19 Higher address (b) Setting 1 wait cycle (PW01, PW00 = 0, 1) ASTB Lower address...
Page 449 CHAPTER 23 LOCAL BUS INTERFACE FUNCTIONS Figure 23-7. External Write Timing for External Memory in External Memory Expansion Mode (a) Setting 0 wait cycles (PW01, PW00 = 0, 0) ASTB Hi-Z Lower address AD0 to AD7 Write data A8 to A19 Higher address (b) Setting 1 wait cycle (PW01, PW00 = 0, 1) ASTB...
Page 450 CHAPTER 23 LOCAL BUS INTERFACE FUNCTIONS Figure 23-8. Read Modify Write Timing for External Memory in External Memory Expansion Mode (a) Setting 0 wait cycles (PW01, PW00 = 0, 0) ASTB Hi-Z Hi-Z Higher address Read data Lower address Write data AD0 to AD7 Higher address Higher address...
Page 451 CHAPTER 23 LOCAL BUS INTERFACE FUNCTIONS 23.5 Wait Functions If slow memory and I/O are connected externally to the µ PD784225, waits can be inserted in the external memory access cycle. For the wait cycle, there is an address wait to guarantee the address decoding time and an access wait to guarantee the access time.
Page 452 CHAPTER 23 LOCAL BUS INTERFACE FUNCTIONS Figure 23-9. Read/Write Timing by Address Wait Function (2/3) (b) Read timing when an address wait is inserted Note Higher address A8 to A19 Hi-Z Hi-Z Hi-Z Lower address Input data AD0 to AD7 ASTB : Main system clock frequency.
Page 453 CHAPTER 23 LOCAL BUS INTERFACE FUNCTIONS Figure 23-9. Read/Write Timing by Address Wait Function (3/3) (c) Write timing when an address wait is not inserted Note A8 to A19 Higher address Hi-Z Hi-Z Hi-Z AD0 to AD7 Lower address Output data ASTB (d) Write timing when an address wait is inserted Note...
Page 454 CHAPTER 23 LOCAL BUS INTERFACE FUNCTIONS 23.5.2 Access wait An access wait is inserted during low RD and WR signals. The low level is lengthened by 1/f (80 ns, f = 12.5 MHz) per cycle. The wait insertion methods are the programmable wait function that automatically inserts a preset number of cycles and the external wait function that is controlled from the outside by the wait signal.
Page 455 CHAPTER 23 LOCAL BUS INTERFACE FUNCTIONS Figure 23-10. Read Timing by Access Wait Function (1/2) (a) Setting 0 wait cycles (PW01, PW00 = 0, 0) Note A8 to A19 Higher address (output) Hi-Z Hi-Z Lower Hi-Z AD0 to AD7 Data (input) address ASTB (output) RD (output)
Page 456 CHAPTER 23 LOCAL BUS INTERFACE FUNCTIONS Figure 23-10. Read Timing by Access Wait Function (2/2) (c) Setting 2 wait cycles (PW01, PW00 = 1, 0) Note A8 to A19 Higher address (output) Lower Hi-Z Hi-Z AD0 to AD7 Data (input) address ASTB (output) RD (output)
Page 457 CHAPTER 23 LOCAL BUS INTERFACE FUNCTIONS Figure 23-11. Write Timing by Access Wait Function (1/2) (a) Setting 0 wait cycles (PW01, PW00 = 0, 0) Note A8 to A19 Higher address (output) Hi-Z AD0 to AD7 Hi-Z Lower Hi-Z Data address (output) ASTB (output)
Page 458 CHAPTER 23 LOCAL BUS INTERFACE FUNCTIONS Figure 23-11. Write Timing by Access Wait Function (2/2) (c) Setting 2 wait cycles (PW01, PW00 = 1, 0) Note A8 to A19 Higher address (output) Lower Hi-Z Hi-Z Hi-Z AD0 to AD7 Data address (output) ASTB (output)
Page 459 CHAPTER 23 LOCAL BUS INTERFACE FUNCTIONS Figure 23-12. Timing by External Wait Signal (a) Read Timing (PW01, PW00 = 1, 1) Note A8 to A19 Higher address (output) Hi-Z Lower Hi-Z AD0 to AD7 Data (input) address ASTB (output) RD (output) WAIT (input) (b) Write timing (PW01, PW00 = 1, 1) Note...
Page 460 CHAPTER 23 LOCAL BUS INTERFACE FUNCTIONS 23.6 External Access Status Output Function 23.6.1 Summary The external access status signal is output from the P37/EXA pin. This signal is output at the moment of external access when use of the external bus interface function has been enabled. This signal detected the external access status of other devices connected to the external bus, prohibits other devices from outputting data to the external bus, and enables reception.
Page 461 CHAPTER 23 LOCAL BUS INTERFACE FUNCTIONS 23.6.3 External access status enable register The external access status enable register (EXAE) controls the EXA signal output indicated during external access. EXAE are set by a 1-bit or 8-bit memory manipulation instruction. RESET input sets to 00H. Figure 23-14.
Page 462 CHAPTER 23 LOCAL BUS INTERFACE FUNCTIONS (b) Data read timing P4, P5, P60 to P63 Address P67/ASTB P64/RD P65/WR H P37/EXA (c) Data write timing P4, P5, P60 to P63 Address Data P67/ASTB P64/RD P65/WR H P37/EXA 23.6.5 EXA pin status during each mode P37/EXA pin status during each mode is shown in Table 23-4.
Page 463 CHAPTER 23 LOCAL BUS INTERFACE FUNCTIONS 23.7 External Memory Connection Example Figure 23-15. Example of Local Bus Interface (Multiplexed Bus) µ PD784225 SRAM Data bus I/O1 to I/O8 Address bus A8 to A19 A0 to A19 Address latch ASTB Q0 to Q7 AD0 to AD7 D0 to D7 User’s Manual U12697EJ3V0UM...
Page 464 CHAPTER 24 STANDBY FUNCTION 24.1 Configuration and Function The µ PD784225 has a standby function that can decrease the system’s power consumption. The standby function has the following six modes. Table 24-1. Standby Function Modes HALT mode Stops the CPU operating clock. The average power consumption can be reduced by intermittent operation during normal operation.
Page 465 CHAPTER 24 STANDBY FUNCTION Figure 24-1. Standby Function State Transition Macro service Low power consumption IDLE mode set Low power consumption HALT mode set Low power power power consumption consumption consumption mode Note 1 HALT mode (Subsystem IDLE mode Interrupt request clock operation) (Standby) (Standby)
Page 466 If the RETB instruction is used to simply return from an operand error, an infinite loop occurs. Since an operand error interrupt is generated only when the program inadvertently loops (only the correct instruction is generated when MOV STBC, #byte is specified in RA78K4 NEC assembler), make the program initialize the system.
Page 467 CHAPTER 24 STANDBY FUNCTION Figure 24-2. Format of Standby Control Register (STBC) Address: 0FFC0H After reset: 30H Symbol STBC Subsystem clock oscillation control Oscillator operation. (Use internal feedback resistors.) Oscillator stop. (Do not use internal feedback resistors.) CPU clock selection (Recommended) –...
Page 468 CHAPTER 24 STANDBY FUNCTION Example MOV STBC, #byte 3. When CK2 = 0, even if MCK = 1, the oscillation of the main system clock does not stop (refer to 4.5.1 Main system clock operations). Remarks 1. f : Main system clock oscillation frequency (f or f : Main system clock oscillation frequency : Subsystem clock oscillation frequency...
Page 469 CHAPTER 24 STANDBY FUNCTION Figure 24-3. Format of Clock Status Register (PCS) Address: 0FFCEH After reset: 32H Symbol Feedback resistor state for subsystem clock Use internal feedback resistors. Do not use internal feedback resistors. CPU clock operating frequency (Recommended) – –...
Page 470 CHAPTER 24 STANDBY FUNCTION (3) Oscillation stabilization time specification register (OSTS) OSTS register sets the oscillator operation and the oscillation stabilization time when the STOP mode is released. Whether a crystal/ceramic oscillator or an external clock will be used is set in the EXTC bit of OSTS. If only the EXTC bit is set to 1, the STOP mode can also be set when the external clock is input.
Page 471 CHAPTER 24 STANDBY FUNCTION Figure 24-4. Format of Oscillation Stabilization Time Specification Register (OSTS) Address: 0FFCFH After reset: 00H Symbol OSTS EXTC OSTS2 OSTS1 OSTS0 EXTC External clock selection Use crystal/ceramic oscillation Use an external clock EXTC OSTS2 OSTS1 OSTS0 Oscillation stabilization time selection (42.0 ms) (21.0 ms)
Page 472 CHAPTER 24 STANDBY FUNCTION 24.3 HALT Mode 24.3.1 Settings and operating states of HALT mode The HALT mode is set by setting the HLT bit in standby control register (STBC) to 1. STBC can be written in with 8-bit data by a special instruction. Therefore, the HALT mode is specified by the MOV STBC, #byte instruction.
Page 473 CHAPTER 24 STANDBY FUNCTION Table 24-2. Operating States in HALT Mode HALT Mode Setting HALT Instruction Mode Setting During HALT Instruction Mode Setting During Main System Clock Operation Subsystem Clock Operation No subsystem clock Subsystem clock When the main system When the main system Note 1 Note 2...
Page 474 CHAPTER 24 STANDBY FUNCTION 24.3.2 Releasing HALT mode The HALT mode can be released by the following three sources. • Non-maskable interrupt request (Only possible for NMI pin input) • Maskable interrupt request (vectored interrupt, context switching, macro service) • RESET input Table 24-3 lists the release source and describes the operation after release.
Page 475 CHAPTER 24 STANDBY FUNCTION Table 24-3. Releasing HALT Mode and Operation After Release Note 1 Note 2 Release Source State During Release Operation After Release × × RESET input – Normal reset operation × × NMI pin input • None while executing a non-maskable Acknowledges interrupt requests interrupt service program •...
Page 476 CHAPTER 24 STANDBY FUNCTION Figure 24-5. Operations After Releasing HALT Mode (1/4) (1) Interrupt after HALT mode Main routine MOV STBC, #byte HALT mode Interrupt request • HALT mode release • Interrupt servicing (2) Reset after HALT mode Main routine MOV STBC, #byte HALT mode RESET input...
Page 477 CHAPTER 24 STANDBY FUNCTION Figure 24-5. Operations After Releasing HALT Mode (2/4) (3) HALT mode during interrupt servicing routine whose priority is higher than or equal to release source interrupt Main routine MOV STBC, #byte HALT mode • HALT mode release •...
Page 478 CHAPTER 24 STANDBY FUNCTION Figure 24-5. Operations After Releasing HALT Mode (3/4) (5) Macro service request in HALT mode (a) Immediately after macro service end condition is satisfied, interrupt request is issued (VCIE = 0). Main routine MOV STBC, #byte HALT mode Last macro service request •...
Page 479 CHAPTER 24 STANDBY FUNCTION Figure 24-5. Operations After Releasing HALT Mode (4/4) (6) HALT mode which the interrupt is held, which is enabled in an instruction that interrupt requests are temporarily held Main routine Interruption held for the Interrupt request space of eight clocks MOV STBC, #byte •...
Page 480 CHAPTER 24 STANDBY FUNCTION (1) Released by a non-maskable interrupt When a non-maskable interrupt is generated, the halt mode is released regardless of the enable state (EI) and disable state (DI) for interrupt acknowledgement. If the non-maskable interrupt that released the HALT mode can be acknowledged when released from the HALT mode, that non-maskable interrupt is acknowledged, and execution branches to the service program.
Page 481 CHAPTER 24 STANDBY FUNCTION Table 24-4. Releasing HALT Mode by Maskable Interrupt Request Note 1 Note 2 Release Source State During Release Operation After Release Maskable • None while executing an interrupt Acknowledges interrupt requests interrupt service program request (except •...
Page 482 CHAPTER 24 STANDBY FUNCTION 24.4 STOP Mode 24.4.1 Settings and operating states of STOP mode The STOP mode is set by setting the STP bit in the standby control register (STBC) to one. STBC can be written with 8-bit data by a special instruction. Therefore, the STOP mode is set by the MOV STBC, #byte instruction.
Page 483 CHAPTER 24 STANDBY FUNCTION Table 24-5. Operating States in STOP Mode STOP Mode Setting With Subsystem Clock Without Subsystem Clock Item Clock generator Only main system clock stops oscillating. Operation disabled Port (output latch) Holds the state before the STOP mode was set. 16-bit timer/counter Operational when the watch timer output is Operation disabled...
Page 484 CHAPTER 24 STANDBY FUNCTION 24.4.2 Releasing STOP mode The STOP mode is released by NMI input, INTP0 to INTP5 input, watch timer interrupt (INTWT), or RESET input. Outlines of the release sources and operations following release are shown in Table 24-6. Operations following release of the STOP mode are also shown in Figure 24-6.
Page 485 CHAPTER 24 STANDBY FUNCTION Figure 24-6. Operations After Releasing STOP Mode (1/3) (1) Interrupt after STOP mode Main routine MOV STBC, #byte STOP mode (Oscillation stabilization time wait) • STOP mode release • Interrupt servicing (2) Reset after STOP mode Main routine MOV STBC, #byte STOP mode...
Page 486 CHAPTER 24 STANDBY FUNCTION Figure 24-6. Operations After Releasing STOP Mode (2/3) (3) STOP mode during interrupt servicing routine whose priority is lower than release source interrupt Main routine MOV STBC, #byte STOP mode (Oscillation stabilization time wait) • STOP mode release •...
Page 487 CHAPTER 24 STANDBY FUNCTION Figure 24-6. Operations After Releasing STOP Mode (3/3) (5) Contention between STOP mode setting instruction and interrupt Main routine MOV STBC, #byte • STOP mode not executed Execute instruction up to 6 clocks Interrupt request • Interrupt servicing User’s Manual U12697EJ3V0UM...
Page 488 CHAPTER 24 STANDBY FUNCTION (1) Releasing the STOP mode by NMI input When the valid edge specified in external interrupt edge enable registers 0 (EGP0, EGN0) is input by the NMI input, the oscillator starts oscillating again. Then the STOP mode is released after the oscillation stabilization time set by the oscillation stabilization time specification register (OSTS).
Page 489 CHAPTER 24 STANDBY FUNCTION (2) Releasing the STOP mode by INTP0 to INTP5 input and watch timer interrupt If interrupt masking is released through INTP0 to INTP5 input and macro service is disabled, the oscillator restarts oscillating when a valid edge specified in external interrupt edge enable registers 0 (EGP0, EGN0) is input to INTP0 to INTP5.
Page 490 CHAPTER 24 STANDBY FUNCTION 24.5 IDLE Mode 24.5.1 Settings and operating states of IDLE mode The IDLE mode is set by setting both bits STP and HLT in the standby control register (STBC) to one. STBC can only be written with 8-bit data by using a special instruction. Therefore, the IDLE mode is set by the MOV STBC, #byte instruction.
Page 491 CHAPTER 24 STANDBY FUNCTION Table 24-7. Operating States in IDLE Mode IDLE Mode Setting With Subsystem Clock Without Subsystem Clock Item Clock generator The oscillation circuits in both the main system clock and subsystem clock continue operating. The clock supply to both the CPU and peripherals is stopped. Operation disabled Port (output latch) Holds the state before the IDLE mode was set.
Page 492 CHAPTER 24 STANDBY FUNCTION 24.5.2 Releasing IDLE mode The IDLE mode is released by NMI input, INTP0 to INTP5 input, watch timer interrupt (INTWT), or RESET input. Outlines of the release sources and operations following release are shown in Table 24-8. Operations following release of the IDLE mode are also shown in Figure 24-9.
Page 493 CHAPTER 24 STANDBY FUNCTION Figure 24-9. Operations After Releasing IDLE Mode (1/2) (1) Interrupt after IDLE mode Main routine MOV STBC, #byte IDLE mode Interrupt request • IDLE mode release • Interrupt servicing (2) Reset after IDLE mode Main routine MOV STBC, #byte IDLE mode RESET input...
Page 494 CHAPTER 24 STANDBY FUNCTION Figure 24-9. Operations After Releasing IDLE Mode (2/2) (3) IDLE mode during interrupt servicing routine whose priority is higher than or equal to release source interrupt Main routine MOV STBC, #byte IDLE mode • IDLE mode release •...
Page 495 CHAPTER 24 STANDBY FUNCTION Figure 24-9. Operations After Releasing IDLE Mode (3/3) (5) Contention between IDLE mode setting instruction and interrupt Main routine MOV STBC, #byte • IDLE mode not executed Execute instruction up to 6 clocks • Interrupt servicing User’s Manual U12697EJ3V0UM...
Page 496 CHAPTER 24 STANDBY FUNCTION (1) Releasing the IDLE mode by NMI input When the valid edge specified in external interrupt edge enable registers 0 (EGP0, EGN0) is input by the NMI input, the IDLE mode is released. When the IDLE mode is released and the non-maskable interrupt from the NMI pin input can be acknowledged, execution branches to the NMI interrupt service program.
Page 497 CHAPTER 24 STANDBY FUNCTION 24.6 Check Items When Using STOP or IDLE Mode The checks required to decrease the current consumption when using the STOP mode or IDLE mode are described below. (1) Is the output level of each output pin appropriate? The appropriate output level of each pin differs with the circuit in the next stage.
Page 498 CHAPTER 24 STANDBY FUNCTION (4) Are the address bus, the address/data bus, etc. handled appropriately? The address bus, address/data bus, and RD and WR pins have high impedances in the STOP and IDLE modes. Normally, these pins are pulled up by pull-up resistors. If the pull-up resistors are connected to the power supply that is backed up, the current flows through the pull-up resistors when the low input impedance of the circuit connected to the power supply that is not backed up, and the consumption current increases.
Page 499 CHAPTER 24 STANDBY FUNCTION 24.7 Low Power Consumption Mode Note 24.7.1 Setting low power consumption mode When the low power consumption mode is entered, set 70H in the standby control register (STBC). This setting switches the system clock from the main system clock to the subsystem clock. Whether the system clock switched to the subsystem clock can be verified from the data read from bit CST in the clock status register (PCS) (refer to Figure 24-3).
Page 500 CHAPTER 24 STANDBY FUNCTION Figure 24-12. Setting Timing for Subsystem Clock Operation Main system clock Stop main system clock oscillation. Subsystem clock System clock STBC Subsystem clock CST bit Power supply Main power supply Backup power supply Power supply switching 24.7.2 Returning to main system clock operation When returning to main system clock operation from subsystem clock operation, the system power supply first switches to the main power supply and enables the oscillation of the main system clock (set STBC = 70H).
Page 501 CHAPTER 24 STANDBY FUNCTION Figure 24-13. Flow to Restore Main System Clock Operation Normal operation using the subsystem clock Operating with the backup power supply Switch to the main power supply. Write STBC = 70H Execute the instruction that starts the main system clock. Has the oscillation Software wait stabilization time elapsed?
Page 502 CHAPTER 24 STANDBY FUNCTION (1) HALT mode (a) Settings and operating states of HALT mode When set in the HALT mode in the low power consumption mode, set 75H in STBC. Table 24-9 shows the operating states in the HALT mode. Table 24-9.
Page 503 CHAPTER 24 STANDBY FUNCTION (b) Releasing the HALT mode (i) Releasing the HALT mode by NMI input When the valid edge specified by external interrupt edge enable registers 0 (EGP0, EGN0) is input to the NMI input, the IDLE mode is released. When released from the HALT mode, if non-maskable interrupts by the NMI pin input can be acknowledged, execution branches to the NMI interrupt service program.
Page 504 CHAPTER 24 STANDBY FUNCTION (2) IDLE mode (a) Settings and operating states of IDLE mode When the low power consumption mode is set in the IDLE mode, set 77H in STBC. Table 24-10 shows the operating states in the IDLE mode. Table 24-10.
Page 505 CHAPTER 24 STANDBY FUNCTION (b) Releasing the IDLE mode (i) Releasing the IDLE mode by NMI input When the valid edge set in external interrupt edge enable registers 0 (EGP0, EGN0) is input to the NMI input, the IDLE mode is released. When the IDLE mode is released and non-maskable interrupts by the NMI pin input can be acknowledged, execution branches to the NMI interrupt service program.
Page 506 CHAPTER 25 RESET FUNCTION When a low level is input to RESET input pin, system reset is performed. The hardware enters the states listed in Figure 25-1. Since the oscillation of the main system clock unconditionally stops during the reset period, the current consumption of the entire system can be reduced.
Page 507 CHAPTER 25 RESET FUNCTION Figure 25-2. Receiving Reset Signal Time until clock starts oscillating Analog Oscillation Analog delay Analog delay delay stabilization time RESET input Internal reset signal Internal clock Table 25-1. State After Reset for All Hardware Resets Hardware State During Reset (RESET = L) State After Reset (RESET = H) Main system clock oscillator...
Page 508 CHAPTER 26 ROM CORRECTION 26.1 ROM Correction Functions µ PD784224, 784225, 784224Y and 784225Y convert part of the program within the mask ROM into the program within the internal expansion ROM. The use of ROM correction enables command bugs discovered in the mask ROM to be repaired, and change the flow of the program.
Page 509 CHAPTER 26 ROM CORRECTION Table 26-1. Differences Between 78K/IV ROM Correction and 78K/0 ROM Correction Difference 78K/IV 78K/0 Generated command codes CALLT instruction Branch instruction for peripheral RAM (1-byte instruction: (3-byte instruction) FCH, FDH, FEH, FFH) Change of the stack pointer Yes (3-byte save) None Address comparison conditions...
Page 510 CHAPTER 26 ROM CORRECTION 26.2 ROM Correction Configuration ROM correction includes the following hardware. Table 26-2. ROM Correction Configuration Item Configuration Register ROM correction address register H, L (CORAH, CORAL) Control register ROM correction control register (CORC) A ROM correction block diagram is shown in Figure 26-1, and Figure 26-2 shows an example of memory mapping. Figure 26-1.
Page 511 CHAPTER 26 ROM CORRECTION Figure 26-2. Memory Mapping Example ( µ PD784225) 01FFFFH Internal ROM 00FEFFH 00FFFFH Internal high-speed RAM 00FD00H 00FF00H 00FCFFH 00FEFFH Internal RAM Peripheral RAM [correction program] 00EE00H 00EDFFH 00EE00H 00007FH [Reference table 3] [Reference table 2] [Reference table 1] [Reference table 0] Internal ROM...
Page 512 CHAPTER 26 ROM CORRECTION (1) ROM correction address register (CORAH, CORAL) The register that sets the header address (correction address) of the command within the mask ROM that needs to be repaired. A maximum of four program locations can be repaired with ROM correction. First of all, the channel is selected with bit 0 (CORCH0) and bit 1 (CORCH1) of the ROM correction control register (CORC), and the address is then set in the specified channel’s address pointer when the address is written in CORAH and CORAL.
Page 513 CHAPTER 26 ROM CORRECTION Figure 26-4. Format of ROM Correction Control Register (CORC) After reset: 00H Address: 0FF88H Symbol CORC COREN3 COREN2 COREN1 COREN0 CORCH1 CORCH0 CORENn Controls the match detection for the ROM correction address register and the fetch address. Disabled Enabled Channel selection...
Page 514 CHAPTER 26 ROM CORRECTION 26.4 Usage of ROM Correction <1> The correct address and post-correction instruction (correction program) are stored in the microcontroller external inactive memory (EEPROM™). <2> A substitute instruction is read from the inactive memory with the use of a serial interface when the initialization program is running after being reset, and this is stored in the peripheral RAM and external memory.
Page 515 CHAPTER 26 ROM CORRECTION 26.5 Conditions for Executing ROM Correction In order to use the ROM correction function, it is necessary for the external environment and program to satisfy the following conditions. (1) External environment Must be connected externally to an inactive memory, and be configured to read that data. (2) Target program The data setting instruction for CORC, CORAH and CORAL will be previously annotated in the target program (program stored in the ROM).
Page 516 CHAPTER 27 µ PD78F4225 AND µ PD78F4225Y PROGRAMMING Flash memories in the µ PD784225 and 784225Y Subseries are available for µ PD78F4225 and 78F4225Y. This chapter provides an explanation of using the µ PD78F4225 and 78F4225Y as substitutes for the µ PD78F4225. µ...
Page 517 CHAPTER 27 µ PD78F4225 AND µ PD78F4225Y PROGRAMMING 27.1 Internal Memory Size Switching Register (IMS) IMS is a register to prevent a certain part of the internal memory from being used by software. By setting the IMS, it is possible to establish a memory map that is the same as the mask ROM product's memory map for the internal memory (ROM, RAM) which has a different capacity.
Page 518 CHAPTER 27 µ PD78F4225 AND µ PD78F4225Y PROGRAMMING 27.2 Flash Memory Overwriting The µ PD78F4225 is equipped with an on-chip 128 KB flash memory. The following method is available for overwriting in the on-chip flash memory. • On-board overwrite mode: Overwriting performed with the use of the flash writer. Flash memory overwriting can be performed 20 times.
Page 519 CHAPTER 27 µ PD78F4225 AND µ PD78F4225Y PROGRAMMING 27.3.1 Selecting communication mode Flashpro III writes to flash memory by serial communication. The communication mode is selected from Table 27-3 then writing is performed. The selection of the communication mode has the format shown in Figure 27-2. Each communication mode is selected by the number of V pulses shown in Table 27-3.
Page 520 CHAPTER 27 µ PD78F4225 AND µ PD78F4225Y PROGRAMMING Figure 27-2. Format of Communication Mode Selection pulse 10 V RESET Flash writing mode 27.3.2 On-board overwrite mode functions By transmitting and receiving various commands and data by the selected communication protocol, operations such as writing to the flash memory are performed.
Page 521 CHAPTER 27 µ PD78F4225 AND µ PD78F4225Y PROGRAMMING 27.3.3 Connecting Flashpro III The connection between Flashpro III and the µ PD78F4225 differs with the communication mode (3-wire serial I/ O or UART). Figures 27-3 to 27-5 are the connection diagrams in each case. Figure 27-3.
Page 522 CHAPTER 27 µ PD78F4225 AND µ PD78F4225Y PROGRAMMING Figure 27-5. Connection of Flashpro III in UART Mode (When Using UART1) µ Flashpro III PD78F4225Y , AV RESET RESET RxD1 TxD1 , AV Note n = 1, 2 Caution Connect the V pin directly to V or pull down.
Page 523 CHAPTER 28 INSTRUCTION OPERATION 28.1 Conventions (1) Operand format and descriptions (1/2) Format Description Note 1 r, r’ X(R0), A(R1), C(R2), B(R3), R4, R5, R6, R7, R8, R9, R10, R11, E(R12), D(R13), L(R14), H(R15) Note 1 X(R0), A(R1), C(R2), B(R3), R4, R5, R6, R7 R8, R9, R10, R11, E(R12), D(R13), L(R14), H(R15) V, U, T, W Note 2...
Page 524 CHAPTER 28 INSTRUCTION OPERATION (1) Operand format and descriptions (2/2) Format Description Note saddr, saddr' FD20H to FF1FH Immediate data or label saddr1 FE00H to FEFFH Immediate data or label saddr2 FD20H to FDFFH, FF00H to FF1FH Immediate data or label saddrp FD20H to FF1EH Immediate data or label (when manipulating 16 bits) saddrp1...
Page 525 CHAPTER 28 INSTRUCTION OPERATION (2) Operand column symbols Symbol Description Auto increment – Auto decrement Immediate data 16-bit absolute address 24-bit/20-bit absolute address 8-bit relative address 16-bit relative address Bit reversal Indirect addressing 24-bit indirect addressing (3) Flag column symbols Symbol Description (Blank)
Page 526 CHAPTER 28 INSTRUCTION OPERATION (5) Number of bytes in instruction that has mem in operand mem Mode Register Indirect Addressing Based Addressing Indexed Addressing Based Indexed Addressing Note No. of bytes Note This becomes a 1-byte instruction only when [TDE], [WHL], [TDE+], [TDE–], [WHL+], or [WHL–] is described in mem in the MOV instruction.
Page 527 CHAPTER 28 INSTRUCTION OPERATION 28.2 List of Operations (1) 8-bit data transfer instruction: MOV Flag Mnemonic Operand Bytes Operation AC P/V CY r ← byte r, #byte (saddr) ← byte saddr, #byte sfr ← byte sfr, #byte (saddr16) ← byte !addr16,, #byte (addr24) ←...
Page 528 CHAPTER 28 INSTRUCTION OPERATION (2) 16-bit data transfer instruction: MOVW Flag Mnemonic Operand Bytes Operation AC P/V CY rp ← word MOVW rp, #word (saddrp) ← word saddrp, #word sfrp ← word sfrp, #word (addr16) ← word !addr16, #word (addr24) ← word !!addr24, #word rp ←...
Page 529 CHAPTER 28 INSTRUCTION OPERATION (3) 24-bit data transfer instruction: MOVG Flag Mnemonic Operand Bytes Operation AC P/V CY rg ← imm24 MOVG rg, #imm24 rg ← rg' rg, rg' rg ← (addr24) rg, !!addr24 (addr24) ← rg !!addr24, rg rg ← (saddrg) rg, saddrg (saddrg) ←...
Page 530 CHAPTER 28 INSTRUCTION OPERATION (5) 16-bit data exchange instruction: XCHW Flag Mnemonic Operand Bytes Operation AC P/V CY rp ↔ rp'´ XCHW rp, rp' AX ↔ (saddrp2) AX, saddrp2 rp ↔ (saddrp) rp, saddrp rp ↔ sfrp rp, sfrp AX ↔ ((saddrp)) AX, [saddrp] AX ↔...
Page 531 CHAPTER 28 INSTRUCTION OPERATION Flag Mnemonic Operand Bytes Operation AC P/V CY A, CY ← A + byte + CY × × × × ADDC A, #byte r, CY ← r + byte + CY × × × × r, #byte (saddr), CY ←...
Page 532 CHAPTER 28 INSTRUCTION OPERATION Flag Mnemonic Operand Bytes Operation AC P/V CY A, CY ← A – byte × × × × A, #byte r, CY ← r – byte × × × × r, #byte (saddr), CY ← (saddr) – byte ×...
Page 533 CHAPTER 28 INSTRUCTION OPERATION Flag Mnemonic Operand Bytes Operation AC P/V CY A, CY ← A – byte – CY × × × × SUBC A, #byte r, CY ← r – byte – CY × × × × r, #byte (saddr), CY ←...
Page 534 CHAPTER 28 INSTRUCTION OPERATION Flag Mnemonic Operand Bytes Operation AC P/V CY × × × × A, #byte A – byte × × × × r, #byte r – byte × × × × saddr, #byte (saddr) – byte × ×...
Page 535 CHAPTER 28 INSTRUCTION OPERATION Flag Mnemonic Operand Bytes Operation AC P/V CY A ← A byte × × A, #byte r ← r byte × × r, #byte (saddr) ← (saddr) × × saddr, #byte byte sfr ← sfr byte ×...
Page 536 CHAPTER 28 INSTRUCTION OPERATION Flag Mnemonic Operand Bytes Operation AC P/V CY A ← A byte × × A, #byte r ← r byte × × r, #byte (saddr) ← (saddr) × × saddr, #byte byte sfr ← sfr byte ×...
Page 537 CHAPTER 28 INSTRUCTION OPERATION Flag Mnemonic Operand Bytes Operation AC P/V CY A ← A × × A, #byte byte r ← r × × r, #byte byte (saddr) ← (saddr) × × saddr, #byte byte sfr ← sfr × ×...
Page 538 CHAPTER 28 INSTRUCTION OPERATION (7) 16-bit arithmetic instructions: ADDW, SUBW, CMPW Flag Mnemonic Operand Bytes Operation AC P/V CY AX, CY ← AX + word × × × × ADDW AX, #word rp, CY ← rp + word × × ×...
Page 539 CHAPTER 28 INSTRUCTION OPERATION (8) 24-bit arithmetic instructions: ADDG, SUBG Flag Mnemonic Operand Bytes Operation AC P/V CY rg, CY ← rg + rg' × × × × ADDG rg, rg' rg, CY ← rg + imm24 × × × ×...
Page 540 CHAPTER 28 INSTRUCTION OPERATION (11) Increment and decrement instructions: INC, DEC, INCW, DECW, INCG, DECG Flag Mnemonic Operand Bytes Operation AC P/V CY r ← r + 1 × × × (saddr) ← (saddr) + 1 × × × saddr r ←...
Page 541 CHAPTER 28 INSTRUCTION OPERATION (13) Shift and rotate instructions: ROR, ROL, RORC, ROLC, SHR, SHL, SHRW, SHLW, ROR4, ROL4 Flag Mnemonic Operand Bytes Operation AC P/V CY ← r ← r ) × n × r, n (CY, r n = 0 to 7 m–1 ←...
Page 542 CHAPTER 28 INSTRUCTION OPERATION Flag Mnemonic Operand Bytes Operation AC P/V CY CY ← CY × AND1 CY, saddr.bit (saddr.bit) CY ← CY × CY, /saddr.bit (saddr.bit) CY ← CY × CY, sfr.bit sfr.bit CY ← CY × CY, /sfr.bit sfr.bit CY ←...
Page 543 CHAPTER 28 INSTRUCTION OPERATION Flag Mnemonic Operand Bytes Operation AC P/V CY CY ← CY × XOR1 CY, saddr.bit (saddr.bit) CY ← CY × CY, sfr.bit sfr.bit CY ← CY × CY, X.bit X.bit CY ← CY × CY, A.bit A.bit CY ←...
Page 544 CHAPTER 28 INSTRUCTION OPERATION (15) Stack manipulation instructions: PUSH, PUSHU, POP, POPU, MOVG, ADDWG, SUBWG, INCG, DECG Flag Mnemonic Operand Bytes Operation AC P/V CY (SP – 2) ← PSW, SP ← SP – 2 PUSH (SP – 2) ← sfrp, SP ← SP – 2 sfrp (SP –...
Page 545 CHAPTER 28 INSTRUCTION OPERATION (16) Call return instructions: CALL, CALLF, CALLT, BRK, BRKCS, RET, RETI, RETB, RETCS, RETCSB Flag Mnemonic Operand Bytes Operation AC P/V CY (SP – 3) ← (PC + 3), SP ← SP – 3, CALL !addr16 ←...
Page 546 CHAPTER 28 INSTRUCTION OPERATION (17) Unconditional branch instruction: BR Flag Mnemonic Operand Bytes Operation AC P/V CY ← 0, PC ← addr16 !addr16 PC ← addr20 !!addr20 ← 0, PC ← rp PC ← rg ← 0, PC ← (rp) [rp] PC ←...
Page 547 CHAPTER 28 INSTRUCTION OPERATION (18) Conditional branch instructions: BNZ, BNE, BZ, BE, BNC, BNL, BC, BL, BNV, BPO, BV, BPE, BP, BN, BLT, BGE, BLE, BGT, BNH, BH, BF, BT, BTCLR, BFSET, DBNZ Flag Mnemonic Operand Bytes Operation AC P/V CY PC ←...
Page 548 CHAPTER 28 INSTRUCTION OPERATION Flag Mnemonic Operand Bytes Operation AC P/V CY PC ← PC + 3 Note 1 saddr.bit, $addr20 + jdisp8 if (saddr.bit) = 1 PC ← PC + 4 + jdisp8 if sfr.bit = 1 sfr.bit, $addr20 PC ←...
Page 549 CHAPTER 28 INSTRUCTION OPERATION Flag Mnemonic Operand Bytes Operation AC P/V CY {PC ← PC + 4 Note 2 + jdisp8, (saddr.bit) ← 1} BFSET saddr.bit, $addr20 if (saddr.bit = 0) {PC ← PC + 4 + jdisp8, sfr.bit ← 1} if sfr. bit = 0 sfr.bit, $addr20 {PC ←...
Page 550 CHAPTER 28 INSTRUCTION OPERATION (20) String instructions: MOVTBLW, MOVM, XCHM, MOVBK, XCHBK, CMPME, CMPMNE, CMPMC, CMPMNC, CMPBKE, CMPBKNE, CMPBKC, CMPBKNC Flag Mnemonic Operand Bytes Operation AC P/V CY (addr8 + 2) ← (addr8), byte ← byte – 1, MOVTBLW !addr8, byte addr8 ←...
Page 551 CHAPTER 28 INSTRUCTION OPERATION 28.3 Lists of Addressing Instructions (1) 8-bit instructions (The values enclosed by parentheses are combined to express the A description as r.) MOV, XCH, ADD, ADDC, SUB, SUBC, AND OR XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, SHR, SHL, ROR4, ROL4, DBNZ, PUSH, POP, MOVM, XCHM, CMPME, CMPMNE, CMPMNC, CMPMC, MOVBK, XCHBK, CMPBKE, CMPBKNE, CMPBKNC, CMPBKC Table 28-1.
Page 552 CHAPTER 28 INSTRUCTION OPERATION (2) 16-bit instructions (The values enclosed by parentheses are combined to express AX description as rp.) MOVM, XCHW, ADDW, SUBW, CMPW, MULUW, MULW, DIVUX, INCW, DECW, SHRW, SHLW, PUSH, POP, ADDWG, SUBWG, PUSHU, POPU, MOVTBLW, MACW, MACSW, SACW Table 28-2.
Page 553 CHAPTER 28 INSTRUCTION OPERATION (3) 24-bit instructions (The values enclosed by parentheses are combined to express WHL description as rg.) MOVG, ADDG, SUBG, INCG, DECG, PUSH, POP Table 28-3. 24-Bit Addressing Instructions Note Second #imm24 saddrg !!addr24 mem1 [%saddrg] None operand First operand (MOVG)
Page 554 CHAPTER 28 INSTRUCTION OPERATION (5) Call return instructions and branch instructions CALL, CALLF, CALLT, BRK, RET, RETI, RETB, RETCS, RETCSB, BRKCS, BR, BNZ, BNE, BZ, BE, BNC, BNL, BC, BL, BNV, BPO, BV, BPE, BP, BN, BLT, BGE, BLE, BGT, BNH, BH, BF, BT, BTCLR, BFSET, DBNZ Table 28-5.
Page 555 APPENDIX A MAJOR DIFFERENCES BETWEEN THE µ PD784216 SUBSERIES AND THE µ PD780058 SUBSERIES Series Name µ PD784225 Subseries µ PD780058 Subseries µ PD784216 Subseries Item 16-bit CPU 8-bit CPU Minimum When the main system 160 ns (@ 12.5 MHz operation) 400 ns (@ 5.0 MHz instruction clock is selected...
Page 556 APPENDIX B DEVELOPMENT TOOLS The following development tools are available for system development using the µ PD784225 Subseries. Figure B-1 shows the development tools. • For PC98-NX series Unless otherwise specified, products supported by IBM PC/AT and compatible machines can be used for the PC98-NX series.
Page 557 APPENDIX B DEVELOPMENT TOOLS Figure B-1. Development Tool Configuration (1/2) (1) When using in-circuit emulator IE-78K4-NS Language processing software • Assembler package • C compiler package • C library source file • Device file Debugging tools • System simulator • Integrated debugger •...
Page 558 APPENDIX B DEVELOPMENT TOOLS Figure B-1. Development Tool Configuration (2/2) (2) When using in-circuit emulator IE-784000-R Language processing software • Assembler package • C compiler package • C library source file • Device file Debugging tools • System simulator • Integrated debugger •...
Page 559 APPENDIX B DEVELOPMENT TOOLS B.1 Language Processing Software RA78K4 Assembler package Program that converts a program written in mnemonic to an executable microcontroller object code. In addition, this assembler package has functions to create symbol tables and optimize branch instructions, etc. automatically. Use this in combination with the device file (DF784225) sold separately.
Page 560 APPENDIX B DEVELOPMENT TOOLS Remark The ×××× part number differs depending on the host machine and operating system used. µ S××××RA78K4 µ S××××CC78K4 µ S××××DF784225 µ S××××CC78K4-L ×××× Host Machine Supply Medium Note AA13 PC-9800 series Japanese Windows 3.5-inch 2HD FD Note AB13 IBM PC/AT compatible...
Page 561 APPENDIX B DEVELOPMENT TOOLS B.3 Debugging Tools B.3.1 Hardware (1/2) (1) When using in-circuit emulator IE-78K4-NS IE-78K4-NS In-circuit emulator to debug hardware and software when developing application In-circuit emulator systems using the 78K/IV Series. Supports the integrated debugger (ID78K4-NS). Use in combination with an interface adapter to connect to the power supply unit, emulation probe, and host machine.
Page 562 APPENDIX B DEVELOPMENT TOOLS B.3.1 Hardware (2/2) (2) When using in-circuit emulator IE-784000-R IE-784000-R The IE-784000-R is an in-circuit emulator common to the 78K/IV Series, and is used in In-circuit emulator combination with IE-784000-R-EM and IE-784225-NS-EM1, which are sold separately. This in-circuit emulator debugs the connected host machine.
Page 563 APPENDIX B DEVELOPMENT TOOLS B.3.2 Software (1/2) SM78K4 This enables debugging at the C source level or assembler level while simulating System simulator operation of the target system on the host machine. The SM78K4 operates on Windows. By using the SM78K4, logic verification and performance verification can be performed separately to hardware development without using an in-circuit emulator, thus improving development efficiency and software quality.
Page 564 APPENDIX B DEVELOPMENT TOOLS B.3.2 Software (2/2) ID78K4-NS Windows and OSF/Motif are employed as the GUI for PC and EWS respectively Integrated debugger (supporting providing users with their unique look and operability. In addition, the enhanced C in-circuit emulator IE-78K4-NS) language supported debug function enables the result of a trace to be displayed at the C language level using the window integration function in which the source program, disassemble display, and memory display are linked to the result of trace.
Page 565 APPENDIX B DEVELOPMENT TOOLS B.4 Conversion Socket (EV-9200GC-80) and Conversion Adapter (TGK-080SDW) (1) The package drawing of the conversion socket (EV-9200GC-80) and recommended board installation pattern Figure B-2. Package Drawing of EV-9200GC-80 (Reference) (Unit: mm) EV-9200GC-80 No.1 pin index EV-9200GC-80-G1E ITEM MILLIMETERS INCHES...
Page 566 APPENDIX B DEVELOPMENT TOOLS Figure B-3. Recommended Board Installation Pattern of EV-9200GC-80 (Reference) (Unit: mm) EV-9200GC-80-P1E ITEM MILLIMETERS INCHES 19.7 0.776 15.0 0.591 0.65 ± 0.02 × 19=12.35 ± 0.05 +0.001 × 0.748=0.486 +0.003 0.026 –0.002 –0.002 0.65 ± 0.02 × 19=12.35 ± 0.05 +0.001 ×...
Page 567 APPENDIX B DEVELOPMENT TOOLS (2) Package drawing of the conversion adapter (TGK-080SDW) Combined with the emulation probe and mounted on the board. Figure B-4. TGK-080SDW Package Drawing (Reference) (Unit: mm) M2 screw I J J J L L LM Protrusion : 4 places ITEM MILLIMETERS INCHES...
Page 568 APPENDIX C EMBEDDED SOFTWARE The following embedded software is available for more efficient program development or maintenance of the µ PD784225 Subseries. Real-Time Operating System (1/2) This is a real-time OS complying within the µ ITRON specification. The RX78K/IV nucleus and RX78K/IV real-time OS tools to create multiple information tables (configurator) have been added.
Page 569 APPENDIX C EMBEDDED SOFTWARE Real-Time Operating System (2/2) This is the operating system of µ ITRON specification subset. The MX78K4 nucleus is added. MX78K4 OS Task management, event management, and time management are performed. Task manage- ment controls the task execution order and switches to the task executed next. <Caution on using in PC environment>...
Page 570 APPENDIX D REGISTER INDEX D.1 Register Index A/D conversion result register (ADCR) … 232 A/D converter input selection register (ADIS) … 235 A/D converter mode register (ADM) … 233 Asynchronous serial interface mode register 1 (ASIM1) … 264, 265, 270 Asynchronous serial interface mode register 2 (ASIM2) …...
Page 571 APPENDIX D REGISTER INDEX Macro service mode register … 403 Memory expansion mode register (MM) … 439 Oscillation mode selection register (CC) … 97 Oscillation stabilization time specification register (OSTS) … 99, 470 Port 0 (P0) … 111 Port 0 mode register (PM0) … 133 Port 1 (P1) …...
Page 572 APPENDIX D REGISTER INDEX Real-time output port control register (RTPC) … 143 Real-time output port mode register (RTPM) … 142 Receive shift register (RX1) … 263 Receive shift register (RX2) … 263 Receive buffer register 1 (RXB1) … 263 Receive buffer register 2 (RXB2) … 263 ROM correction address register H (CORAH) …...
Page 573 APPENDIX D REGISTER INDEX D.2 Register Index (Alphabetical Order) ADCR: A/D conversion result register … 232 ADIC: Interrupt control register … 389 ADIS: A/D converter input selection register … 235 ADM: A/D converter mode register … 233 ASIM1: Asynchronous serial interface mode register 1 … 264, 265, 270 ASIM2: Asynchronous serial interface mode register 2 …...
Page 574 APPENDIX D REGISTER INDEX IICS0: C bus status register 0 … 302 IMC: Interrupt mode control register … 374 IMS: Internal memory size switching register … 70 ISPR: In-service priority register … 373 KRIC: Interrupt control register … 362 MK0H: Interrupt mask flag register 0H …...
Page 575 APPENDIX D REGISTER INDEX PRM2: Prescaler mode register 2 … 191, 192 PRM5: Prescaler mode register 5 … 210 PRM6: Prescaler mode register 6 … 210, 211 PSW: Program status word … 377 PU0: Pull-up resistor option register 0 … 136 PU2: Pull-up resistor option register 2 …...
Page 576 APPENDIX D REGISTER INDEX TMC6: 8-bit timer mode control register 6 … 208, 209 TMIC00: Interrupt control register … 369 TMIC01: Interrupt control register … 369 TMIC1: Interrupt control register … 370 TMIC2: Interrupt control register … 370 TMIC5: Interrupt control register … 370 TMIC6: Interrupt control register …...
Page 577 APPENDIX E REVISION HISTORY (1/4) Edition Contents Applied to: Modification of power supply voltage range (only for µ PD78F4225, 78F4225Y) 2nd edition Throughout 1.8 to 5.5 V → After change: V Before change: V 1.9 to 5.5 V Modification of package Before change: GK-BE9 type →...
Page 578 APPENDIX E REVISION HISTORY (2/4) Edition Contents Applied to: 2nd edition Modification of Figure 9-1 Block Diagram of 8-Bit Timer/Event Counters 1 and CHAPTER 9 8-BIT TIMER/ Modification of caution in (1) 8-bit timer counters 1 and 2 (TM1, TM2) EVENT Modification of caution in (2) 8-bit compare registers 10 and 20 (CR10, CR20) COUNTERS 1, 2...
Page 579 APPENDIX E REVISION HISTORY (3/4) Edition Contents Applied to: 2nd edition Modification of Figure 17-1 Block Diagram of Clocked Serial Interface (in 3- CHAPTER 17 Wire Serial I/O Mode) 3-WIRE SERIAL I/O MODE Modification of Figure 18-3 Format of I C Bus Control Register (IICC0) CHAPTER 18 Addition of note about bit 3 (TRC0) to Figure 18-4 Format of I...
Page 580 APPENDIX E REVISION HISTORY (4/4) Edition Contents Applied to: 2nd edition Modified throughout APPENDIX B DEVELOPMENT TOOLS Modified throughout APPENDIX C EMBEDDED SOFTWARE 3rd edition The following products have been developed. Throughout • µ PD78F4225GC-8BT, 78F4225GK-9EU, 78F4225YGC-8BT, 78F4225YGK-9EU • Addition of Caution related to operation in one-shot pulse output mode CHAPTER 8 16-BIT TIMER/ EVENT COUNTER...
Page 581 Facsimile Message Although NEC has taken all possible steps to ensure that the documentation supplied to our customers is complete, bug free and up-to-date, we readily accept that From: errors may occur. Despite all the care and precautions we’ve taken, you may Name encounter problems in the documentation.

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NEC mPD784225 Series User Manual

Chapter 1 Overview

Chapter 2 Pin Functions

Chapter 3 Cpu Architecture

Chapter 4 Clock Generator

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