Debug Trap - NEC V850ES/F 3-L Series User Manual

32-bit single-chip microcontroller

Table of Contents

Interrupt Controller (INTC)

5.6.2 Debug trap

The debug trap is an exception that can be acknowledged every time and is

generated by execution of the DBTRAP instruction.

When the debug trap is generated, the CPU performs the following processing.

When the debug trap is generated, the CPU performs the following processing,

transfers control to the debug monitor routine, and shifts to debug mode.

1. Saves the restored PC to DBPC.

2. Saves the current PSW to DBPSW.

3. Sets the NP, EP and ID bits of the PSW.

4. Sets the handler address (00000060H) corresponding to the debug trap to

the PC and transfers control.

Figure 5-14 illustrates the processing of the debug trap.

CPU processing

Debug trap processing

Recovery from a debug trap is carried out by the DBRET instruction. By

executing the DBRET instruction, the CPU carries out the following processing

and controls the address of the restored PC.

1. Loads the restored PC and PSW from DBPC and DBPSW.

2. Transfers control to the address indicated by the restored PC and PSW.

User's Manual U18743EE1V2UM00

DBTRAP instruction

Exception processing