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CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION
5.5 Exception Trap
The exception trap is an interrupt that is requested when illegal execution of an instruction takes place. In the V854,
an illegal op code exception (ILGOP: ILeGal OPcode trap) is considered as an exception trap.
An illegal op code exception occurs if the subop code field of an instruction to be executed next is not a valid op
code.
5.5.1 Illegal op code definition
An illegal op code is defined to be a 32-bit word with bits 5 to 10 being 111111B and bits 23 to 26 being 0011B
to 1111B.
15
13
12
11
x
x
x
x
x : don't care
Caution
It is recommended that the illegal op code not be defined since an instruction may newly be
assigned later.
5.5.2 Operation
If an exception trap occurs, the CPU performs the following processing, and transfers control to the handler routine:
(1) Saves the restored PC to EIPC.
(2) Saves the current PSW to EIPSW.
(3) Writes an exception code (0060H) to the lower 16 bits (EICC) of ECR.
(4) Sets the EP and ID bits of PSW.
(5) Loads the handler address (00000060H) for the exception trap routine to the PC, and transfers control.
Figure 5-12 illustrates how the exception trap is processed.
CPU processing
10
5
4
x
1
1
1
1
1
1
x
x
x
x
Figure 5-12. Exception Trap Processing
Exception trap (ILGOP) occurs
EIPC
EIPSW
ECR.EICC
PSW.EP
PSW.ID
PC
Exception processing
User's Manual U11969EJ3V0UM00
0
31
27 26
23 22
21
0
0
1
1
to
x
x
x
x
x
x
x
1
1
1
1
← restored PC
← PSW
← exception code
← 1
← 1
← 00000060H
20
16
x
x x x x x
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