Debug Trap - NEC V850ES/KE1+ User Manual

CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION

17.6.2 Debug trap

A debug trap is an exception that occurs upon execution of the DBTRAP instruction and that can be acknowledged
at all times.
When a debug trap occurs, the CPU performs the following processing.
(1) Operation
<1> Saves the restored PC to DBPC.
<2> Saves the current PSW to DBPSW.
<3> Sets the PSW.NP, PSW.EP, and PSW.ID bits to 1.
<4> Sets the handler address (00000060H) for the debug trap routine to the PC and transfers control.
Figure 17-12 shows the debug trap processing flow.
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Figure 17-12. Debug Trap Processing
DBPC
DBPSW
PSW.NP
PSW.EP
CPU processing
PSW.ID
PC
Debug monitor routine processing
User's Manual U16896EJ2V0UD
DBTRAP instruction
Restored PC
PSW
1
1
1
00000060H