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22.1.2 On-chip debug option byte (000C3H/ 010C3H)
Control of on-chip debug operation
• On-chip debug operation is disabled or enabled.
Handling of data of flash memory in case of failure in on-chip debug security ID authentication
• Data of flash memory is erased or not erased in case of failure in on-chip debug security ID
authentication.
Caution Set the same value as 000C3H to 010C3H when the boot swap operation is used because
000C3H is replaced by 010C3H.
22.2 Format of User Option Byte
The format of user option byte is shown below.
Figure 22-1. Format of User Option Byte (000C0H/010C0H) (1/2)
Note 1
Address: 000C0H/010C0H
7
WDTINIT
WDTINIT
0
1
WINDOW1
0
0
1
1
WDTON
0
1
WDCS2
0
0
0
0
1
1
1
1
656
CHAPTER 22 OPTION BYTE
6
5
WINDOW1
WINDOW0
Use of interval interrupt of watchdog timer
Interval interrupt is not used.
Interval interrupt is generated when 75% of the overflow time is reached.
WINDOW0
0
25%
1
50%
0
75%
1
100%
Operation control of watchdog timer counter
Counter operation disabled (counting stopped after reset)
Counter operation enabled (counting started after reset)
WDCS1
WDCS0
0
0
2
0
1
2
1
0
2
1
1
2
0
0
2
0
1
2
1
0
2
1
1
2
User's Manual U17854EJ9V0UD
4
3
WDTON
WDCS2
WDCS1
Watchdog timer window open period
Watchdog timer overflow time
10
/f
(3.88 ms)
IL
11
/f
(7.76 ms)
IL
12
/f
(15.52 ms)
IL
13
/f
(31.03 ms)
IL
15
/f
(124.12 ms)
IL
17
/f
(496.48 ms)
IL
18
/f
(992.97 ms)
IL
20
/f
(3971.88 ms)
IL
2
1
0
WDCS0
WDSTBYON
Note 2
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