Page 1 Do not use this product for mass production because its reliability cannot be guaranteed after the on-chip debug function has been used, due to issues with respect to the number of times the flash memory can be rewritten. NEC Electronics Document No.
Page 2 [MEMO] Preliminary User’s Manual U17260EJ3V1UD...
Page 3 NOTES FOR CMOS DEVICES VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between V (MAX) and V (MIN) due to noise, etc., the device may malfunction.
Page 4 NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Page 5 Regional Information Some information contained in this document may vary from country to country. Before using any NEC Electronics product in your application, pIease contact the NEC Electronics office in your country to obtain a list of authorized representatives and distributors. They will verify: •...
Page 6 INTRODUCTION Readers This manual is intended for user engineers who wish to understand the functions of the 78K0/KE2 and design and develop application systems and programs for these devices. The target products are as follows. µ 78K0/KE2: PD78F0531, 78F0532, 78F0533, 78F0534, 78F0535, 78F0536, 78F0537, 78F0537D Purpose This manual is intended to give users an understanding of the functions described in the...
Page 7 Conventions Data significance: Higher digits on the left and lower digits on the right Active low representations: ××× (overscore over pin and signal name) Note Preliminary User’s Manual U17260EJ3V1UD...
Page 8 Document No. SEMICONDUCTOR SELECTION GUIDE − Products and Packages − X13769X Semiconductor Device Mount Manual Note Quality Grades on NEC Semiconductor Devices C11531E NEC Semiconductor Device Reliability/Quality Control System C10983E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E Note See the “Semiconductor Device Mount Manual”...
Page 9: Table Of Contents
CONTENTS CHAPTER 1 OUTLINE ..........................17 Features ............................ 17 Applications ..........................18 Ordering Information ....................... 19 Pin Configuration (Top View)....................23 78K0/Kx2 Series Lineup ......................26 Block Diagram.......................... 29 Outline of Functions ........................ 30 CHAPTER 2 PIN FUNCTIONS ....................... 32 Pin Function List........................
Page 11 Functions of Clock Generator ....................134 Configuration of Clock Generator..................135 Registers Controlling Clock Generator ................137 System Clock Oscillator......................146 6.4.1 X1 oscillator ..........................146 6.4.2 XT1 oscillator ...........................146 6.4.3 When subsystem clock is not used ..................149 6.4.4 Internal high-speed oscillator ....................149 6.4.5 Internal low-speed oscillator.....................149 6.4.6...
Page 12 8.4.3 Square-wave output operation ....................256 8.4.4 PWM output operation......................257 Cautions for 8-Bit Timer/Event Counters 50 and 51 ............261 CHAPTER 9 8-BIT TIMERS H0 AND H1 ..................262 Functions of 8-Bit Timers H0 and H1 ................... 262 Configuration of 8-Bit Timers H0 and H1................262 Registers Controlling 8-Bit Timers H0 and H1 ..............
Page 13 13.4.3 A/D converter operation mode ....................318 13.5 How to Read A/D Converter Characteristics Table ............320 13.6 Cautions for A/D Converter....................322 CHAPTER 14 SERIAL INTERFACE UART0 ..................326 14.1 Functions of Serial Interface UART0 ................... 326 14.2 Configuration of Serial Interface UART0 ................327 14.3 Registers Controlling Serial Interface UART0 ..............
Page 14 17.5.11 Extension code.........................434 17.5.12 Arbitration..........................435 17.5.13 Wakeup function........................436 17.5.14 Communication reservation......................437 17.5.15 Other cautions ..........................440 17.5.16 Communication operations.......................442 17.5.17 Timing of I C interrupt request (INTIIC0) occurrence..............449 17.6 Timing Charts ......................... 470 CHAPTER 18 MULTIPLIER/DIVIDER µ PD78F0534, 78F0535, 78F0536, 78F0537, AND 78F0537D ONLY) ....477 18.1 Functions of Multiplier/Divider .....................
Page 15 23.2 Configuration of Power-on-Clear Circuit................531 23.3 Operation of Power-on-Clear Circuit ................... 531 23.4 Cautions for Power-on-Clear Circuit..................534 CHAPTER 24 LOW-VOLTAGE DETECTOR ..................536 24.1 Functions of Low-Voltage Detector ..................536 24.2 Configuration of Low-Voltage Detector................536 24.3 Registers Controlling Low-Voltage Detector ..............537 24.4 Operation of Low-Voltage Detector ..................
Page 16 28.1.2 Description of operation column ....................581 28.1.3 Description of flag operation column ..................581 28.2 Operation List ......................... 582 28.3 Instructions Listed by Addressing Type ................590 CHAPTER 29 ELECTRICAL SPECIFICATIONS (TARGET).............. 593 CHAPTER 30 PACKAGE DRAWINGS ....................612 CHAPTER 31 CAUTIONS FOR WAIT....................617 31.1 Cautions for Wait........................
Page 17: Chapter 1 Outline
PD78F0537D has an on-chip debug function. Do not use this product for mass production because its reliability cannot be guaranteed after the on-chip debug function has been used, from the viewpoint of the restriction on the number of times the flash memory can be rewritten. NEC Electronics does not accept any complaint about this product.
Page 18: Applications
CHAPTER 1 OUTLINE Timer µ PD78F0531, 78F0532, 78F0533: 7 channels µ PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D: 8 channels • 16-bit timer/event counter: 2 channels Note • 8-bit timer/event counter: 2 channels • 8-bit timer: 2 channels • Watch timer: 1 channel •...
Page 19: Ordering Information
CHAPTER 1 OUTLINE 1.3 Ordering Information • Flash memory version (1/4) Part Number Package µ 64-pin plastic LQFP (10x10) PD78F0531GB(T)-UEU-A µ 64-pin plastic LQFP (10x10) PD78F0531GB(T2)-UEU-A µ 64-pin plastic LQFP (10x10) PD78F0531GB(S)-UEU-A µ 64-pin plastic LQFP (10x10) PD78F0531GB(R)-UEU-A µ 64-pin plastic LQFP (14x14) PD78F0531GC(T)-UBS-A µ...
Page 20 CHAPTER 1 OUTLINE • Flash memory version (2/4) Part Number Package µ 64-pin plastic LQFP (10x10) PD78F0533GB(T)-UEU-A µ 64-pin plastic LQFP (10x10) PD78F0533GB(T2)-UEU-A µ 64-pin plastic LQFP (10x10) PD78F0533GB(S)-UEU-A µ 64-pin plastic LQFP (10x10) PD78F0533GB(R)-UEU-A µ 64-pin plastic LQFP (14x14) PD78F0533GC(T)-UBS-A µ...
Page 21 CHAPTER 1 OUTLINE • Flash memory version (3/4) Part Number Package µ 64-pin plastic LQFP (10x10) PD78F0535GB(T)-UEU-A µ 64-pin plastic LQFP (10x10) PD78F0535GB(T2)-UEU-A µ 64-pin plastic LQFP (10x10) PD78F0535GB(S)-UEU-A µ 64-pin plastic LQFP (10x10) PD78F0535GB(R)-UEU-A µ 64-pin plastic LQFP (14x14) PD78F0535GC(T)-UBS-A µ...
Page 22 PD78F0537D has an on-chip debug function. Do not use this product for mass production, because its reliability cannot be guaranteed after the on-chip debug function has been used, with respect to the number of times the flash memory can be rewritten. NEC Electronics does not accept complaints about this product.
Page 23: Pin Configuration (Top View)
CHAPTER 1 OUTLINE 1.4 Pin Configuration (Top View) • 64-pin plastic LQFP (10 × 10) • 64-pin plastic LQFP (14 × 14) • 64-pin plastic LQFP (12 × 12) • 64-pin plastic TQFP (7 × 7) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 P120/INTP0/EXLVI P10/SCK10/TxD0 P11/SI10/RxD0...
Page 24 CHAPTER 1 OUTLINE • 64-pin plastic FLGA (5 × 5) Top View Bottom View Index mark Preliminary User’s Manual U17260EJ3V1UD...
Page 25 CHAPTER 1 OUTLINE Pin Identification ANI0 to ANI7: Analog input P60 to P63: Port 6 Analog reference voltage P70 to P77: Port 7 Analog ground P120 to P124: Port 12 BUZ: Buzzer output P130: Port 13 Power supply for port P140, P141: Port 14 Ground for port...
Page 26: 78K0/Kx2 Series Lineup
CHAPTER 1 OUTLINE 1.5 78K0/Kx2 Series Lineup 78K0/KB2 78K0/KC2 78K0/KD2 78K0/KE2 78K0/KF2 30 Pins 44 Pins 48 Pins 52 Pins 64 Pins 80 Pins µ µ µ − − − Note Note Note 128 KB 7 KB PD78F0527D PD78F0537D PD78F0547D µ...
Page 27 CHAPTER 1 OUTLINE The list of functions in the 78K0/Kx2 Series is shown below. (1/2) Part Number 78K0/KB2 78K0/KC2 Item 30/36 Pins 44 Pins 48 Pins Flash memory (KB) RAM (KB) 0.75 0.75 0.75 − Bank (flash memory) Power supply voltage = 1.8 to 5.5 V Regulator Provided...
Page 28 CHAPTER 1 OUTLINE (2/2) Part Number 78K0/KD2 78K0/KE2 78K0/KF2 Item 52 Pins 64 Pins 80 Pins Flash memory (KB) RAM (KB) 0.75 0.75 − − − Bank (flash memory) Power supply voltage = 1.8 to 5.5 V Regulator Provided µ µ...
Page 29: Block Diagram
CHAPTER 1 OUTLINE 1.6 Block Diagram TO00/TI010/P01 16-bit TIMER/ EVENT COUNTER 00 TI000/P00 (LINSEL) PORT 0 P00 to P06 RxD6/P14 (LINSEL) Note2 Note2 TO01 /TI011 /P06 16-bit TIMER/ PORT 1 P10 to P17 Note2 Note2 TI001 /P05 EVENT COUNTER 01 PORT 2 P20 to P27 TOH0/P15...
Page 30: Outline Of Functions
CHAPTER 1 OUTLINE 1.7 Outline of Functions (1/2) µ µ µ µ µ µ µ µ Item PD78F0531 PD78F0532 PD78F0533 PD78F0534 PD78F0535 PD78F0536 PD78F0537 PD78F0537D Internal Flash memory 16 K 24 K 32 K 48 K 60 K 96 K 128 K memory (self-programming...
Page 31 CHAPTER 1 OUTLINE (2/2) µ µ µ µ µ µ µ µ Item PD78F0531 PD78F0532 PD78F0533 PD78F0534 PD78F0535 PD78F0536 PD78F0537 PD78F0537D Serial interface • UART mode supporting LIN- • UART mode supporting LIN-bus: 1 channel Note bus: 1 channel • 3-wire serial I/O mode/UART mode : 1 channel •...
Page 32: Chapter 2 Pin Functions
CHAPTER 2 PIN FUNCTIONS 2.1 Pin Function List There are three types of pin I/O buffer power supplies: AV , EV , and V . The relationship between these power supplies and the pins is shown below. Table 2-1. Pin I/O Buffer Power Supplies Power Supply Corresponding Pins P20 to P27...
Page 33 CHAPTER 2 PIN FUNCTIONS (1) Port functions (2/2) Function Name Function After Reset Alternate Function − P40 to P43 Port 4. Input port 4-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting.
Page 34 CHAPTER 2 PIN FUNCTIONS (2) Non-port functions (1/2) Function Name Function After Reset Alternate Function INTP0 Input External interrupt request input for which the valid edge (rising Input port P120/EXLVI edge, falling edge, or both rising and falling edges) can be INTP1 specified Note2...
Page 35 CHAPTER 2 PIN FUNCTIONS (2) Non-port pins (2/2) Function Name Function After Reset Alternate Function TO50 Output 8-bit timer/event counter 50 output Input port P17/TI50 TO51 8-bit timer/event counter 51 output P33/TI51/INTP4 TOH0 8-bit timer H0 output TOH1 8-bit timer H1 output P16/INTP5 Clock output (for trimming of high-speed system clock, Output...
Page 36: Description Of Pin Functions
CHAPTER 2 PIN FUNCTIONS 2.2 Description of Pin Functions 2.2.1 P00 to P06 (port 0) P00 to P06 function as a 7-bit I/O port. These pins also function as timer I/O, serial interface data I/O, clock I/O, and chip select input. The following operation modes can be specified in 1-bit units.
Page 37: P10 To P17 (Port 1)
CHAPTER 2 PIN FUNCTIONS 2.2.2 P10 to P17 (port 1) P10 to P17 function as an 8-bit I/O port. These pins also function as pins for external interrupt request input, serial interface data I/O, clock I/O, and timer I/O. The following operation modes can be specified in 1-bit units. (1) Port mode P10 to P17 function as an 8-bit I/O port.
Page 38: P20 To P27 (Port 2)
CHAPTER 2 PIN FUNCTIONS 2.2.3 P20 to P27 (port 2) P20 to P27 function as an 8-bit I/O port. These pins also function as pins for A/D converter analog input. The following operation modes can be specified in 1-bit units. (1) Port mode P20 to P27 function as an 8-bit I/O port.
Page 39: P40 To P43 (Port 4)
CHAPTER 2 PIN FUNCTIONS 2.2.5 P40 to P43 (port 4) P40 to P43 function as a 4-bit I/O port. P40 to P43 can be set to input or output port in 1-bit units using port mode register 4 (PM4). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 4 (PU4). 2.2.6 P50 to P53 (port 5) P50 to P53 function as a 4-bit I/O port.
Page 40: P120 To P124 (Port 12)
CHAPTER 2 PIN FUNCTIONS 2.2.9 P120 to P124 (port 12) P120 to P124 function as a 5-bit I/O port. These pins also function as pins for external interrupt request input, potential input for external low-voltage detection, connecting resonator for main system clock, connecting resonator for subsystem clock, external clock input for main system clock, and external clock input for subsystem clock.
Page 41: P140, P141 (Port 14)
CHAPTER 2 PIN FUNCTIONS 2.2.11 P140, P141 (port 14) P140 and P141 function as a 2-bit I/O port. These pins also function as external interrupt request input, clock output, buzzer output. The following operation modes can be specified in 1-bit units. (1) Port mode P140 and P141 function as a 2-bit I/O port.
Page 42: Vdd And Ev Dd
CHAPTER 2 PIN FUNCTIONS 2.2.16 V and EV is the positive power supply pin for other than P121 to P124 and ports. is the positive power supply pin for ports other than P20 to P27 and P121 to P124. 2.2.17 V and EV is the ground potential pin for other than P121 to P124 and ports.
Page 43: Pin I/O Circuits And Recommended Connection Of Unused Pins
CHAPTER 2 PIN FUNCTIONS 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins Table 2-2 shows the types of pin I/O circuits and the recommended connections of unused pins. See Figure 2-1 for the configuration of the I/O circuit of each type. Table 2-2.
Page 44 CHAPTER 2 PIN FUNCTIONS Table 2-2. Pin I/O Circuit Types (2/2) Pin Name I/O Circuit Type Recommended Connection of Unused Pins Note 1 P121/X1 Input: Independently connect to EV or EV via a resistor. Output: Leave open. Note 1 P122/X2/EXCLK Note 1 P123/XT1 Note 1...
Page 45 CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuit List (1/2) Type 2 Type 5-AH Pull-up P-ch enable Data P-ch IN/OUT Output N-ch Schmitt-triggered input with hysteresis characteristics disable Input enable Type 3-C Type 11-G Data P-ch IN/OUT P-ch Output N-ch disable Data...
Page 46 CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuit List (2/2) Type 13-AD Type 38 IN/OUT Data Output N-ch disable Input enable Input enable Type 37 RESET Data P-ch Output N-ch disable Input enable RESET Data P-ch Output N-ch disable Input enable Preliminary User’s Manual U17260EJ3V1UD...
Page 47: Chapter 3 Cpu Architecture
CHAPTER 3 CPU ARCHITECTURE 3.1 Memory Space Products in the 78K0/KE2 can access a 64 KB memory space. Figures 3-1 to 3-8 show the memory maps. Cautions 1. Regardless of the internal memory capacity, the initial values of the internal memory size switching register (IMS) and internal expansion RAM size switching register (IXS) of all products in the 78K0/KE2 are fixed (IMS = CFH, IXS = 0CH).
Page 48 CHAPTER 3 CPU ARCHITECTURE µ Figure 3-1. Memory Map ( PD78F0531) F F F F H Special function registers (SFR) 256 x 8 bits F F 0 0 H F E F F H General-purpose registers 32 x 8 bits F E E 0 H 3 F F F H F E D F H...
Page 49 CHAPTER 3 CPU ARCHITECTURE µ Figure 3-2. Memory Map ( PD78F0532) F F F F H Special function registers (SFR) 256 x 8 bits F F 0 0 H F E F F H General-purpose registers 32 x 8 bits F E E 0 H 5 F F F H F E D F H...
Page 50 CHAPTER 3 CPU ARCHITECTURE µ Figure 3-3. Memory Map ( PD78F0533) F F F F H Special function registers (SFR) 256 x 8 bits F F 0 0 H F E F F H General-purpose registers 32 x 8 bits F E E 0 H 7 F F F H F E D F H...
Page 51 CHAPTER 3 CPU ARCHITECTURE µ Figure 3-4. Memory Map ( PD78F0534) F F F F H Special function registers (SFR) 256 x 8 bits F F 0 0 H F E F F H General-purpose registers 32 x 8 bits F E E 0 H B F F F H F E D F H...
Page 52 CHAPTER 3 CPU ARCHITECTURE µ Figure 3-5. Memory Map ( PD78F0535) F F F F H Special function registers (SFR) 256 x 8 bits F F 0 0 H F E F F H General-purpose registers 32 x 8 bits F E E 0 H E F F F H F E D F H...
Page 53 CHAPTER 3 CPU ARCHITECTURE µ Figure 3-6. Memory Map ( PD78F0536) Preliminary User’s Manual U17260EJ3V1UD...
Page 54 CHAPTER 3 CPU ARCHITECTURE µ Figure 3-7. Memory Map ( PD78F0537) F F F F H Special function registers (SFR) 256 x 8 bits F F 0 0 H F E F F H General-purpose registers 32 x 8 bits F E E 0 H F E D F H Internal high-speed RAM...
Page 55 CHAPTER 3 CPU ARCHITECTURE µ Figure 3-8. Memory Map ( PD78F0537D) F F F F H Special function registers (SFR) 256 x 8 bits F F 0 0 H 7 F F F H F E F F H General-purpose registers Program area 32 x 8 bits...
Page 56: Internal Program Memory Space
CHAPTER 3 CPU ARCHITECTURE 3.1.1 Internal program memory space The internal program memory space stores the program and table data. Normally, it is addressed with the program counter (PC). 78K0/KE2 products incorporate internal ROM (flash memory), as shown below. Table 3-2. Internal ROM Capacity Part Number Internal ROM Structure...
Page 57 CHAPTER 3 CPU ARCHITECTURE Table 3-3. Vector Table Vector Table Address Interrupt Source Vector Table Address Interrupt Source 0000H RESET input, POC, LVI, WDT 0020H INTTM000 0004H INTLVI 0022H INTTM010 0006H INTP0 0024H INTAD 0008H INTP1 0026H INTSR0 000AH INTP2 0028H INTWTI 000CH...
Page 58: Memory Bank ( Μ Pd78F0536, 78F0537, And 78F0537D Only)
CHAPTER 3 CPU ARCHITECTURE µ 3.1.2 Memory bank ( PD78F0536, 78F0537, and 78F0537D only) µ The 16 KB area 8000H to BFFFH is assigned to memory banks 0 to 3 in the PD78F0536, and assigned to µ memory banks 0 to 5 in the PD78F0537 and 78F0537D.
Page 59: Special Function Register (Sfr) Area
CHAPTER 3 CPU ARCHITECTURE (2) Internal expansion RAM Table 3-5. Internal Expansion RAM Capacity Part Number Internal Expansion RAM µ − PD78F0531 µ PD78F0532 µ PD78F0533 µ 1024 × 8 bits (F400H to F7FFH) PD78F0534 µ 2048 × 8 bits (F000H to F7FFH) PD78F0535 µ...
Page 60 CHAPTER 3 CPU ARCHITECTURE µ Figure 3-9. Correspondence Between Data Memory and Addressing ( PD78F0531) F F F F H Special function registers SFR addressing (SFR) 256 x 8 bits F F 2 0 H F F 1 F H F F 0 0 H F E F F H General-purpose...
Page 61 CHAPTER 3 CPU ARCHITECTURE µ Figure 3-10. Correspondence Between Data Memory and Addressing ( PD78F0532) F F F F H Special function registers SFR addressing (SFR) 256 x 8 bits F F 2 0 H F F 1 F H F F 0 0 H F E F F H General-purpose...
Page 62 CHAPTER 3 CPU ARCHITECTURE µ Figure 3-11. Correspondence Between Data Memory and Addressing ( PD78F0533) F F F F H Special function registers SFR addressing (SFR) 256 x 8 bits F F 2 0 H F F 1 F H F F 0 0 H F E F F H General-purpose...
Page 63 CHAPTER 3 CPU ARCHITECTURE µ Figure 3-12. Correspondence Between Data Memory and Addressing ( PD78F0534) F F F F H Special function registers SFR addressing (SFR) 256 x 8 bits F F 2 0 H F F 1 F H F F 0 0 H F E F F H General-purpose...
Page 64 CHAPTER 3 CPU ARCHITECTURE µ Figure 3-13. Correspondence Between Data Memory and Addressing ( PD78F0535) F F F F H Special function registers SFR addressing (SFR) 256 x 8 bits F F 2 0 H F F 1 F H F F 0 0 H F E F F H General-purpose...
Page 65 CHAPTER 3 CPU ARCHITECTURE µ Figure 3-14. Correspondence Between Data Memory and Addressing ( PD78F0536) F F F F H Special function registers SFR addressing (SFR) 256 x 8 bits F F 2 0 H F F 1 F H F F 0 0 H F E F F H General-purpose...
Page 66 CHAPTER 3 CPU ARCHITECTURE µ Figure 3-15. Correspondence Between Data Memory and Addressing ( PD78F0537, 78F0537D) F F F F H Special function registers SFR addressing (SFR) 256 x 8 bits F F 2 0 H F F 1 F H F F 0 0 H F E F F H General-purpose...
Page 67: Processor Registers
CHAPTER 3 CPU ARCHITECTURE 3.2 Processor Registers The 78K0/KE2 products incorporate the following processor registers. 3.2.1 Control registers The control registers control the program sequence, statuses and stack memory. The control registers consist of a program counter (PC), a program status word (PSW) and a stack pointer (SP). (1) Program counter (PC) The program counter is a 16-bit register that holds the address information of the next program to be executed.
Page 68 CHAPTER 3 CPU ARCHITECTURE (b) Zero flag (Z) When the operation result is zero, this flag is set (1). It is reset (0) in all other cases. (c) Register bank select flags (RBS0 and RBS1) These are 2-bit flags to select one of the four register banks. In these flags, the 2-bit information that indicates the register bank selected by SEL RBn instruction execution is stored.
Page 69 CHAPTER 3 CPU ARCHITECTURE Figure 3-19. Data to Be Saved to Stack Memory (a) PUSH rp instruction (when SP = FEE0H) FEE0H FEE0H FEDFH Register pair higher FEDEH Register pair lower FEDEH (b) CALL, CALLF, CALLT instructions (when SP = FEE0H) FEE0H FEE0H FEDFH...
Page 70 CHAPTER 3 CPU ARCHITECTURE Figure 3-20. Data to Be Restored from Stack Memory (a) POP rp instruction (when SP = FEDEH) FEE0H FEE0H FEDFH Register pair higher FEDEH Register pair lower FEDEH (b) RET instruction (when SP = FEDEH) FEE0H FEE0H FEDFH PC15 to PC8...
Page 71: General-Purpose Registers
CHAPTER 3 CPU ARCHITECTURE 3.2.2 General-purpose registers General-purpose registers are mapped at particular addresses (FEE0H to FEFFH) of the data memory. The general-purpose registers consists of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L, and H). Each register can be used as an 8-bit register, and two 8-bit registers can also be used in a pair as a 16-bit register (AX, BC, DE, and HL).
Page 72: Special Function Registers (Sfrs)
CHAPTER 3 CPU ARCHITECTURE 3.2.3 Special function registers (SFRs) Unlike a general-purpose register, each special function register has a special function. SFRs are allocated to the FF00H to FFFFH area. Special function registers can be manipulated like general-purpose registers, using operation, transfer, and bit manipulation instructions.
Page 73 CHAPTER 3 CPU ARCHITECTURE Table 3-6. Special Function Register List (1/4) Address Special Function Register (SFR) Name Symbol Manipulatable Bit Unit After Reset 1 Bit 8 Bits 16 Bits √ √ − FF00H Port register 0 √ √ − FF01H Port register 1 √...
Page 74 CHAPTER 3 CPU ARCHITECTURE Table 3-6. Special Function Register List (2/4) Address Special Function Register (SFR) Name Symbol Manipulatable Bit Unit After Reset 1 Bit 8 Bits 16 Bits √ √ − FF30H Pull-up resistor option register 0 √ √ −...
Page 75 CHAPTER 3 CPU ARCHITECTURE Table 3-6. Special Function Register List (3/4) Address Special Function Register (SFR) Name Symbol Manipulatable Bit Unit After Reset 1 Bit 8 Bits 16 Bits √ √ − FF70H Asynchronous serial interface operation mode ASIM0 register 0 −...
Page 76 CHAPTER 3 CPU ARCHITECTURE Table 3-6. Special Function Register List (4/4) Address Special Function Register (SFR) Name Symbol Manipulatable Bit Unit After Reset 1 Bit 8 Bits 16 Bits √ √ − FFBBH Prescaler mode register 00 PRM00 √ √ −...
Page 77 CHAPTER 3 CPU ARCHITECTURE 3.3 Instruction Address Addressing An instruction address is determined by contents of the program counter (PC) and memory bank select register (BANK), and is normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed.
Page 78 CHAPTER 3 CPU ARCHITECTURE 3.3.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16 or BR !addr16 or CALLF !addr11 instruction is executed. CALL !addr16 and BR !addr16 instructions can be branched to the entire memory space.
Page 79 CHAPTER 3 CPU ARCHITECTURE 3.3.3 Table indirect addressing [Function] Table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the immediate data of an operation code are transferred to the program counter (PC) and branched. This function is carried out when the CALLT [addr5] instruction is executed.
Page 80 CHAPTER 3 CPU ARCHITECTURE 3.4 Operand Address Addressing The following methods are available to specify the register and memory (addressing) to undergo manipulation during instruction execution. 3.4.1 Implied addressing [Function] The register that functions as an accumulator (A and AX) among the general-purpose registers is automatically (implicitly) addressed.
Page 81 CHAPTER 3 CPU ARCHITECTURE 3.4.2 Register addressing [Function] The general-purpose register to be specified is accessed as an operand with the register bank select flags (RBS0 to RBS1) and the register specify codes of an operation code. Register addressing is carried out when an instruction with the following operand format is executed. When an 8-bit register is specified, one of the eight registers is specified with 3 bits in the operation code.
Page 82 CHAPTER 3 CPU ARCHITECTURE 3.4.3 Direct addressing [Function] The memory to be manipulated is directly addressed with immediate data in an instruction word becoming an operand address. This addressing can be carried out for all of the memory spaces. However, before addressing a memory bank that is not set by the memory bank select register (BANK), change the setting of the memory bank by using BANK.
Page 83 CHAPTER 3 CPU ARCHITECTURE 3.4.4 Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. This addressing is applied to the 256-byte space FE20H to FF1FH. Internal high-speed RAM and special function registers (SFRs) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively.
Page 84 CHAPTER 3 CPU ARCHITECTURE 3.4.5 Special function register (SFR) addressing [Function] A memory-mapped special function register (SFR) is addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the SFRs mapped at FF00H to FF1FH can be accessed with short direct addressing.
Page 85 CHAPTER 3 CPU ARCHITECTURE 3.4.6 Register indirect addressing [Function] Register pair contents specified by a register pair specify code in an instruction word and by a register bank select flag (RBS0 and RBS1) serve as an operand address for addressing the memory. This addressing can be carried out for all of the memory spaces.
Page 86 CHAPTER 3 CPU ARCHITECTURE 3.4.7 Based addressing [Function] 8-bit immediate data is added as offset data to the contents of the base register, that is, the HL register pair in the register bank specified by the register bank select flag (RBS0 and RBS1), and the sum is used to address the memory.
Page 87 CHAPTER 3 CPU ARCHITECTURE 3.4.8 Based indexed addressing [Function] The B or C register contents specified in an instruction word are added to the contents of the base register, that is, the HL register pair in the register bank specified by the register bank select flag (RBS0 and RBS1), and the sum is used to address the memory.
Page 88 CHAPTER 3 CPU ARCHITECTURE 3.4.9 Stack addressing [Function] The stack area is indirectly addressed with the stack pointer (SP) contents. This addressing method is automatically employed when the PUSH, POP, subroutine call and return instructions are executed or the register is saved/reset upon generation of an interrupt request. With stack addressing, only the internal high-speed RAM area can be accessed.
Page 89 CHAPTER 4 MEMORY BANK SELECT FUNCTION µ PD78F0536, 78F0537, AND 78F0537D ONLY) 4.1 Memory Bank µ PD78F0536, 78F0537, and 78F0537D implement a ROM capacity of 96 KB or 128 KB by selecting a memory bank from a memory space of 8000H to BFFFH. µ...
Page 90 µ CHAPTER 4 MEMORY BANK SELECT FUNCTION ( PD78F0536, 78F0537, AND 78F0537D ONLY) 4.2 Memory Bank Select Register (BANK) The memory bank select register (BANK) is used to select a memory bank to be used. BANK can be set by an 8-bit memory manipulation instruction. Reset signal generation clears BANK to 00H.
Page 91 µ CHAPTER 4 MEMORY BANK SELECT FUNCTION ( PD78F0536, 78F0537, AND 78F0537D ONLY) 4.3 Selecting Memory Bank The memory bank selected by the memory bank select register (BANK) is reflected on the bank area and can be addressed. Therefore, to access a memory bank different from the one currently selected, that memory bank must be selected by using the BANK register.
Page 92 µ CHAPTER 4 MEMORY BANK SELECT FUNCTION ( PD78F0536, 78F0537, AND 78F0537D ONLY) • Software example (to store a value to be referenced in register A) RAMD DSEG SADDR R_BNKA: ; Secures RAM for specifying an address at the reference destination. R_BNKN: ;...
Page 93 µ CHAPTER 4 MEMORY BANK SELECT FUNCTION ( PD78F0536, 78F0537, AND 78F0537D ONLY) 4.3.2 Branching instruction between memory banks Instructions cannot branch directly from one memory bank to another. To branch an instruction from one memory bank to another, branch once to the common area (0000H to 7FFFH), change the setting of the BANK register there, and then execute the branch instruction again.
Page 94 µ CHAPTER 4 MEMORY BANK SELECT FUNCTION ( PD78F0536, 78F0537, AND 78F0537D ONLY) • Software example RAMD DSEG SADDR R_BNKA: ; Secures RAM for specifying a memory bank at the branch destination. R_BNKN: ; Secures RAM for specifying a memory bank number at the branch destination. R_BNKN,#BANKNUM TEST ;...
Page 95 µ CHAPTER 4 MEMORY BANK SELECT FUNCTION ( PD78F0536, 78F0537, AND 78F0537D ONLY) 4.3.3 Subroutine call between memory banks Subroutines cannot be directly called between memory banks. To call a subroutine between memory banks, branch once to the common area (0000H to 7FFFH), specify the memory bank at the calling destination by using the BANK register there, execute the CALL instruction, and branch to the call destination by that instruction.
Page 96 µ CHAPTER 4 MEMORY BANK SELECT FUNCTION ( PD78F0536, 78F0537, AND 78F0537D ONLY) • Software example RAMD DSEG SADDR R_BNKA: ; Secures RAM for specifying an address at the calling destination. R_BNKN: ; Secures RAM for specifying a memory bank number at the calling destination. R_BNKRN: DS ;...
Page 97 µ CHAPTER 4 MEMORY BANK SELECT FUNCTION ( PD78F0536, 78F0537, AND 78F0537D ONLY) 4.3.4 Instruction branch to bank area by interrupt When an interrupt occurs, instructions can branch to the memory bank specified by the BANK register by using the vector table, but it is difficult to identify the BANK register when the interrupt occurs.
Page 98 µ CHAPTER 4 MEMORY BANK SELECT FUNCTION ( PD78F0536, 78F0537, AND 78F0537D ONLY) Remark Note the following points to use the memory bank select function efficiently. • Allocate a routine that is used often in the common area. • If a value that is planned to be referenced is placed in RAM, it can be referenced from all of the areas. •...
Page 99 CHAPTER 5 PORT FUNCTIONS 5.1 Port Functions There are three types of pin I/O buffer power supplies: AV , EV , and V . The relationship between these power supplies and the pins is shown below. Table 5-1. Pin I/O Buffer Power Supplies Power Supply Corresponding Pins P20 to P27...
Page 100 CHAPTER 5 PORT FUNCTIONS Table 5-2. Port Functions (1/2) Pin Name Function After Reset Alternate Function Port 0. Input port TI000 7-bit I/O port. TI010/TO00 Input/output can be specified in 1-bit units. Note1 SO11 Use of an on-chip pull-up resistor can be specified by a Note1 SI11 software setting.
Page 101 CHAPTER 5 PORT FUNCTIONS Table 5-2. Port Functions (2/2) Function Name Function After Reset Alternate Function P120 Port 12. Input port INTP0/EXLVI 5-bit I/O port. Note P121 X1/OCD0A Input/output can be specified in 1-bit units. Note P122 X2/EXCLK/OCD0B Only for P120, use of an on-chip pull-up resistor can be P123 specified by a software setting.
Page 102 CHAPTER 5 PORT FUNCTIONS 5.2.1 Port 0 Port 0 is a 7-bit I/O port with an output latch. Port 0 can be set to the input mode or output mode in 1-bit units using port mode register 0 (PM0). When the P00 to P06 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 0 (PU0).
Page 103 CHAPTER 5 PORT FUNCTIONS Figure 5-3. Block Diagram of P01 PU01 P-ch Alternate function PORT Output latch P01/TI010/TO00 (P01) PM01 Alternate function Port register 0 PU0: Pull-up resistor option register 0 PM0: Port mode register 0 Read signal WR××: Write signal Preliminary User’s Manual U17260EJ3V1UD...
Page 104 CHAPTER 5 PORT FUNCTIONS Figure 5-4. Block Diagram of P02 PU02 P-ch PORT Output latch Note P02/SO11 (P02) PM02 Alternate Note function Port register 0 PU0: Pull-up resistor option register 0 PM0: Port mode register 0 Read signal WR××: Write signal µ...
Page 105 CHAPTER 5 PORT FUNCTIONS Figure 5-5. Block Diagram of P03 and P05 µ PD78F0531, 78F0532, 78F0533 PU03, PU05 P-ch PORT Output latch P03, P05 (P03, P05) PM03, PM05 µ PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D PU03, PU05 P-ch Alternate function PORT Output latch P03/SI11, (P03, P05)
Page 106 CHAPTER 5 PORT FUNCTIONS Figure 5-6. Block Diagram of P04 µ PD78F0531, 78F0532, 78F0533 Preliminary User’s Manual U17260EJ3V1UD...
Page 107 CHAPTER 5 PORT FUNCTIONS Figure 5-7. Block Diagram of P06 µ PD78F0531, 78F0532, 78F0533 PU06 P-ch PORT Output latch (P06) PM06 µ PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D PU06 P-ch Alternate function PORT Output latch P06/TI011/TO01 (P06) PM06 Alternate function Port register 0 PU0: Pull-up resistor option register 0 PM0:...
Page 108 CHAPTER 5 PORT FUNCTIONS 5.2.2 Port 1 Port 1 is an 8-bit I/O port with an output latch. Port 1 can be set to the input mode or output mode in 1-bit units using port mode register 1 (PM1). When the P10 to P17 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 1 (PU1).
Page 109 CHAPTER 5 PORT FUNCTIONS Figure 5-9. Block Diagram of P11 and P14 PU11, PU14 P-ch Alternate function PORT Output latch P11/SI10/RxD0, (P11, P14) P14/RxD6 PM11, PM14 Port register 1 PU1: Pull-up resistor option register 1 PM1: Port mode register 1 Read signal WR××: Write signal Preliminary User’s Manual U17260EJ3V1UD...
Page 110 CHAPTER 5 PORT FUNCTIONS Figure 5-10. Block Diagram of P12 and P15 PU12, PU15 P-ch PORT Output latch P12/SO10 (P12, P15) P15/TOH0 PM12, PM15 Alternate function Port register 1 PU1: Pull-up resistor option register 1 PM1: Port mode register 1 Read signal WR××: Write signal Preliminary User’s Manual U17260EJ3V1UD...
Page 111 CHAPTER 5 PORT FUNCTIONS Figure 5-11. Block Diagram of P13 PU13 P-ch PORT Output latch P13/TxD6 (P13) PM13 Alternate function Port register 1 PU1: Pull-up resistor option register 1 PM1: Port mode register 1 Read signal WR××: Write signal Preliminary User’s Manual U17260EJ3V1UD...
Page 112 CHAPTER 5 PORT FUNCTIONS Figure 5-12. Block Diagram of P16 and P17 PU16, PU17 P-ch Alternate function PORT Output latch P16/TOH1/INTP5, (P16, P17) P17/TI50/TO50 PM16, PM17 Alternate function Port register 1 PU1: Pull-up resistor option register 1 PM1: Port mode register 1 Read signal WR××: Write signal Preliminary User’s Manual U17260EJ3V1UD...
Page 113 CHAPTER 5 PORT FUNCTIONS 5.2.3 Port 2 Port 2 is an 8-bit I/O port with an output latch. Port 2 can be set to the input mode or output mode in 1-bit units using port mode register 2 (PM2). This port can also be used for A/D converter analog input. To use P20/ANI0 to P27/ANI7 as digital input pins, set them in the digital I/O mode by using the A/D port configuration register (ADPC) and in the input mode by using PM2.
Page 114 CHAPTER 5 PORT FUNCTIONS 5.2.4 Port 3 Port 3 is a 4-bit I/O port with an output latch. Port 3 can be set to the input mode or output mode in 1-bit units using port mode register 3 (PM3). When the P30 to P33 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 3 (PU3).
Page 115 CHAPTER 5 PORT FUNCTIONS Figure 5-15. Block Diagram of P33 PU33 P-ch Alternate function PORT Output latch P33/INTP4/TI51/TO51 (P33) PM33 Alternate function Port register 3 PU3: Pull-up resistor option register 3 PM3: Port mode register 3 Read signal WR××: Write signal Preliminary User’s Manual U17260EJ3V1UD...
Page 116 CHAPTER 5 PORT FUNCTIONS 5.2.5 Port 4 Port 4 is a 4-bit I/O port with an output latch. Port 4 can be set to the input mode or output mode in 1-bit units using port mode register 4 (PM4). When the P40 to P43 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 4 (PU4).
Page 117 CHAPTER 5 PORT FUNCTIONS 5.2.6 Port 5 Port 5 is a 4-bit I/O port with an output latch. Port 5 can be set to the input mode or output mode in 1-bit units using port mode register 5 (PM5). When the P50 to P53 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 5 (PU5).
Page 118 CHAPTER 5 PORT FUNCTIONS 5.2.7 Port 6 Port 6 is a 4-bit I/O port with an output latch. Port 6 can be set to the input mode or output mode in 1-bit units using port mode register 6 (PM6). The output of the P60 to P63 pins is N-ch open-drain output (6 V tolerance). This port can also be used for serial interface data I/O, clock I/O, and external clock input.
Page 119 CHAPTER 5 PORT FUNCTIONS Figure 5-19. Block Diagram of P62 Alternate function PORT Output latch P62/EXSCL0 (P62) PM62 Port register 6 PM6: Port mode register 6 Read signal WR××: Write signal Figure 5-20. Block Diagram of P63 PORT Output latch (P63) PM63 Port register 6...
Page 121 CHAPTER 5 PORT FUNCTIONS 5.2.9 Port 12 Port 12 is a 5-bit I/O port with an output latch. Port 12 can be set to the input mode or output mode in 1-bit units using port mode register 12 (PM12). When used as an input port only for P120, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 12 (PU12).
Page 122 CHAPTER 5 PORT FUNCTIONS Figure 5-23. Block Diagram of P121 to P124 OSCCTL OSCSEL/ OSCSELS PORT Output latch Note P122/X2/EXCLK/OCD0B (P122/P124) P124/XT2/EXCLKS PM12 PM122/PM124 OSCCTL OSCSEL/ OSCSELS OSCCTL EXCLK, OSCSEL/ EXCLKS, OSCSELS PORT Output latch Note (P121/P123) P121/X1/OCD0A P123/XT1 PM12 PM121/PM123 OSCCTL OSCSEL/...
Page 123 CHAPTER 5 PORT FUNCTIONS 5.2.10 Port 13 Port 13 is a 1-bit output-only port. Figure 5-24 shows a block diagram of port 13. Figure 5-24. Block Diagram of P130 PORT Output latch P130 (P130) P13: Port register 13 Read signal WR××: Write signal Remark When reset is effected, P130 outputs a low level.
Page 124 CHAPTER 5 PORT FUNCTIONS 5.2.11 Port 14 Port 14 is a 6-bit I/O port with an output latch. Port 14 can be set to the input mode or output mode in 1-bit units using port mode register 14 (PM14). When the P140 and P141 pins are used as an input port, use of an on-chip pull- up resistor can be specified in 1-bit units by pull-up resistor option register 14 (PU14).
Page 125 CHAPTER 5 PORT FUNCTIONS 5.3 Registers Controlling Port Function Port functions are controlled by the following four types of registers. • Port mode registers (PM0 to PM7, PM12, PM14) • Port registers (P0 to P7, P12 to P14) • Pull-up resistor option registers (PU0, PU1, PU3 to PU5, PU7, PU12, PU14) •...
Page 126 CHAPTER 5 PORT FUNCTIONS Figure 5-26. Format of Port Mode Register Symbol Address After reset PM06 PM05 PM04 PM03 PM02 PM01 PM00 FF20H PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10 FF21H PM27 PM26 PM25 PM24 PM23 PM22 PM21 PM20 FF22H PM33 PM32...
Page 127 CHAPTER 5 PORT FUNCTIONS (2) Port registers (P0 to P7, P12 to P14) These registers write the data that is output from the chip when data is output from a port. If the data is read in the input mode, the pin level is read. If it is read in the output mode, the value of the output latch is read.
Page 128 CHAPTER 5 PORT FUNCTIONS (3) Pull-up resistor option registers (PU0, PU1, PU3 to PU5, PU7, PU12, and PU14) These registers specify whether the on-chip pull-up resistors of P00 to P06, P10 to P17, P30 to P33, P40 to P43, P50 to P53, P70 to P77, P120, or P140 and P141 are to be used or not. On-chip pull-up resistors can be used in 1-bit units only for the bits set to input mode of the pins to which the use of an on-chip pull-up resistor has been specified in PU0, PU1, PU3 to PU5, PU7, PU12, and PU14.
Page 129 CHAPTER 5 PORT FUNCTIONS (4) A/D port configuration register (ADPC) This register switches the P20/ANI0 to P27/ANI7 pins to digital I/O of port or analog input of A/D converter. ADPC can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 00H.
Page 130 CHAPTER 5 PORT FUNCTIONS 5.4 Port Function Operations Port operations differ depending on whether the input or output mode is set, as shown below. Caution In the case of 1-bit memory manipulation instruction, although a single bit is manipulated, the port is accessed as an 8-bit unit.
Page 131 CHAPTER 5 PORT FUNCTIONS 5.5 Settings of Port Mode Register and Output Latch When Using Alternate Function To use the alternate function of a port pin, set the port mode register and output latch as shown in Table 5-5. Table 5-5. Settings of Port Mode Register and Output Latch When Using Alternate Function (1/2) Pin Name Alternate Function PM××...
Page 132 CHAPTER 5 PORT FUNCTIONS Table 5-5. Settings of Port Mode Register and Output Latch When Using Alternate Function (2/2) Pin Name Alternate Function PM×× P×× Function Name × Note 1 Note 1 P20 to P27 ANI0 to ANI7 Input × P30 to P32 INTP1 to INTP3 Input...
Page 133 CHAPTER 5 PORT FUNCTIONS Notes 1. The function of the ANI0/P20 to ANI7/P27 pins can be selected by using the A/D port configuration register (ADPC), the analog input channel specification register (ADS), and PM2. Table 5-6. Setting Functions of ANI0/P20 to ANI7/P27 Pins ADPC ANI0/P20 to ANI7/P27 Pins Analog input selection...
Page 134: Functions Of Clock Generator
CHAPTER 6 CLOCK GENERATOR 6.1 Functions of Clock Generator The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following three kinds of system clocks and clock oscillators are selectable. (1) Main system clock <1>...
Page 135: Configuration Of Clock Generator
CHAPTER 6 CLOCK GENERATOR (3) Internal low-speed oscillation clock (clock for watchdog timer) • Internal low-speed oscillator This circuit oscillates a clock of f = 240 kHz (TYP.). After a reset release, the internal low-speed oscillation clock always starts operating. Oscillation can be stopped by using the internal oscillation mode register (RCM) when “internal low-speed oscillator can be stopped by software”...
Page 136 Figure 6-1. Block Diagram of Clock Generator Internal bus Clock operation mode Main OSC Main clock Processor clock Main clock Oscillation stabilization mode register control register select register control register mode register time select register (OSTS) (OSCCTL) (MOC) (MCM) (PCC) (MCM) AMPH EXCLK OSCSEL...
Page 137: Registers Controlling Clock Generator
CHAPTER 6 CLOCK GENERATOR Remarks 1. f X1 clock oscillation frequency 2. f Internal high-speed oscillation clock frequency 3. f External main system clock frequency EXCLK 4. f High-speed system clock oscillation frequency 5. f Main system clock oscillation frequency 6.
Page 138 CHAPTER 6 CLOCK GENERATOR Figure 6-2. Format of Clock Operation Mode Select Register (OSCCTL) Address: FF9FH After reset: 00H Symbol <7> <6> <5> <4> <0> Note Note OSCCTL EXCLK OSCSEL EXCLKS OSCSELS AMPH EXCLK OSCSEL High-speed system clock P121/X1 pin P122/X2/EXCLK pin pin operation mode I/O port mode...
Page 139 CHAPTER 6 CLOCK GENERATOR (2) Processor clock control register (PCC) This register is used to select the CPU clock, the division ratio, and operation mode for subsystem clock. PCC is set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets PCC to 01H. Figure 6-3.
Page 140 CHAPTER 6 CLOCK GENERATOR Table 6-2. Relationship Between CPU Clock and Minimum Instruction Execution Time CPU Clock (f Minimum Instruction Execution Time: 2/f Main System Clock Subsystem Clock Note High-Speed System Clock Internal High-Speed Note Oscillation Clock At 10 MHz At 20 MHz At 8 MHz (TYP.) Operation At 32.768 kHz Operation...
Page 141 CHAPTER 6 CLOCK GENERATOR (4) Internal oscillation mode register (RCM) This register sets the operation mode of internal oscillator. RCM can be set by a 1-bit or 8-bit memory manipulation instruction. Note 1 Reset signal generation sets this register to 80H Figure 6-4.
Page 142 CHAPTER 6 CLOCK GENERATOR (5) Main OSC control register (MOC) This register selects the operation mode of the high-speed system clock. This register is used to stop the X1 oscillator or to disable an external clock input from the EXCLK pin when the CPU operates with a clock other than the high-speed system clock.
Page 143 CHAPTER 6 CLOCK GENERATOR (6) Main clock mode register (MCM) This register selects the main system clock supplied to CPU clock and clock supplied to peripheral hardware clock. MCM can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 00H.
Page 144 CHAPTER 6 CLOCK GENERATOR (7) Oscillation stabilization time counter status register (OSTC) This is the register that indicates the count status of the X1 clock oscillation stabilization time counter. When X1 clock oscillation starts with the internal high-speed oscillation clock or subsystem clock used as the CPU clock, the X1 clock oscillation stabilization time can be checked.
Page 145 CHAPTER 6 CLOCK GENERATOR (8) Oscillation stabilization time select register (OSTS) This register is used to select the X1 clock oscillation stabilization wait time when the STOP mode is released. When the X1 clock is selected as the CPU clock, the operation waits for the time set using OSTS after the STOP mode is released.
Page 146: System Clock Oscillator
CHAPTER 6 CLOCK GENERATOR 6.4 System Clock Oscillator 6.4.1 X1 oscillator The X1 oscillator oscillates with a crystal resonator or ceramic resonator (1 to 20 MHz) connected to the X1 and X2 pins. Figure 6-9 shows an example of the external circuit of the X1 oscillator. Figure 6-9.
Page 147 CHAPTER 6 CLOCK GENERATOR Cautions 1. When using the X1 oscillator and XT1 oscillator, wire as follows in the area enclosed by the broken lines in the Figures 6-9 and 6-10 to avoid an adverse effect from wiring capacitance. • Keep the wiring length as short as possible. •...
Page 148 CHAPTER 6 CLOCK GENERATOR Figure 6-11. Examples of Incorrect Resonator Connection (2/2) (c) Wiring near high alternating current (d) Current flowing through ground line of oscillator (potential at points A, B, and C fluctuates) High current (e) Signals are fetched Remark When using the subsystem clock, replace X1 and X2 with XT1 and XT2, respectively.
Page 149: When Subsystem Clock Is Not Used
CHAPTER 6 CLOCK GENERATOR 6.4.3 When subsystem clock is not used If it is not necessary to use the subsystem clock for low power consumption operations, or if not using the subsystem clock as an I/O port, set the XT1 and XT2 pins to I/O mode (OSCSELS = 0) and connect them as follows. Input (PM123/PM124 = 1): Independently connect to V or V...
Page 150: Clock Generator Operation
CHAPTER 6 CLOCK GENERATOR 6.5 Clock Generator Operation The clock generator generates the following clocks and controls the operation modes of the CPU, such as standby mode (see Figure 6-1). • Main system clock f • High-speed system clock f X1 clock f External main system clock f EXCLK...
Page 151 CHAPTER 6 CLOCK GENERATOR Figure 6-12. Clock Generator Operation When Power Supply Voltage Is Turned On (When 1.59 V POC Mode Is Set (Option Byte: POCMODE = 0)) Power supply 1.8 V voltage (V 1.59 V (TYP.) 0.5 V/ms (MAX.) Internal reset signal <1>...
Page 152 CHAPTER 6 CLOCK GENERATOR Remark While the microcontroller is operating, a clock that is not used as the CPU clock can be stopped via software settings. The internal high-speed oscillation clock and high-speed system clock can be stopped by executing the STOP instruction (see (4) in 6.6.1 Example of controlling high-speed system clock, (3) in 6.6.2 Example of controlling internal high-speed oscillation clock, and (4) in 6.6.3 Example of controlling subsystem clock).
Page 153: Controlling Clock
CHAPTER 6 CLOCK GENERATOR Remark While the microcontroller is operating, a clock that is not used as the CPU clock can be stopped via software settings. The internal high-speed oscillation clock and high-speed system clock can be stopped by executing the STOP instruction (see (4) in 6.6.1 Example of controlling high-speed system clock, (3) in 6.6.2 Example of controlling internal high-speed oscillation clock, and (4) in 6.6.3 Example of controlling subsystem clock).
Page 154 CHAPTER 6 CLOCK GENERATOR <4> Waiting for the stabilization of the oscillation of X1 clock Check the OSTC register and wait for the necessary time. During the wait time, other software processing can be executed with the internal high-speed oscillation clock.
Page 155 CHAPTER 6 CLOCK GENERATOR <2> Setting the high-speed system clock as the main system clock (MCM register) When XSEL and MCM0 are set to 1, the high-speed system clock is supplied as the main system clock and peripheral hardware clock. XSEL MCM0 Selection of Main System Clock and Clock Supplied to Peripheral Hardware...
Page 156: Example Of Controlling Internal High-Speed Oscillation Clock
CHAPTER 6 CLOCK GENERATOR (b) To stop X1 oscillation (disabling external clock input) by setting MSTOP to 1 <1> Confirming the CPU clock status (PCC and MCM registers) Confirm with CLS and MCS that the CPU is operating on a clock other than the high-speed system clock.
Page 157 CHAPTER 6 CLOCK GENERATOR (2) Example of setting procedure when using internal high-speed oscillation clock as CPU clock, and internal high-speed oscillation clock or high-speed system clock as peripheral hardware clock <1> • Restarting oscillation of the internal high-speed oscillation clock Note (See 6.6.2 (1) Example of setting procedure when restarting internal high-speed oscillation clock).
Page 158: Example Of Controlling Subsystem Clock
CHAPTER 6 CLOCK GENERATOR (b) To stop internal high-speed oscillation clock by setting RSTOP to 1 <1> Confirming the CPU clock status (PCC and MCM registers) Confirm with CLS and MCS that the CPU is operating on a clock other than the internal high-speed oscillation clock.
Page 159 CHAPTER 6 CLOCK GENERATOR (2) Example of setting procedure when using the external subsystem clock <1> Setting XT1 and XT2 pins, selecting XT1 clock/external clock and controlling oscillation (PCC and OSCCTL registers) When XTSTART is cleared to 0 and EXCLKS and OSCSELS are set to 1, the mode is switched from port mode to external clock input mode.
Page 160: Example Of Controlling Internal Low-Speed Oscillation Clock
CHAPTER 6 CLOCK GENERATOR 6.6.4 Example of controlling internal low-speed oscillation clock The internal low-speed oscillation clock cannot be used as the CPU clock. Only the following peripheral hardware can operate with this clock. • Watchdog timer • 8-bit timer H1 (if f is selected as the count clock) In addition, the following operation modes can be selected by the option byte.
Page 161: Cpu Clock Status Transition Diagram
CHAPTER 6 CLOCK GENERATOR 6.6.6 CPU clock status transition diagram Figure 6-14 shows the CPU clock status transition diagram of this product. Figure 6-14. CPU Clock Status Transition Diagram (When 1.59 V POC Mode Is Set (Option Byte: POCMODE = 0)) Internal low-speed oscillation: Woken up Power ON Internal high-speed oscillation: Woken up...
Page 162 CHAPTER 6 CLOCK GENERATOR Table 6-5 shows transition of the CPU clock and examples of setting the SFR registers. Table 6-5. CPU Clock Transition and SFR Register Setting Examples (1/4) (1) CPU operating with internal high-speed oscillation clock (B) after reset release (A) Status Transition SFR Register Setting (A) →...
Page 163 CHAPTER 6 CLOCK GENERATOR Table 6-5. CPU Clock Transition and SFR Register Setting Examples (2/4) (4) CPU clock changing from internal high-speed oscillation clock (B) to high-speed system clock (C) (Setting sequence of SFR registers) Note Note Setting Flag of SFR Register AMPH EXCLK OSCSEL...
Page 164 CHAPTER 6 CLOCK GENERATOR Table 6-5. CPU Clock Transition and SFR Register Setting Examples (3/4) (6) CPU clock changing from high-speed system clock (C) to internal high-speed oscillation clock (B) (Setting sequence of SFR registers) Setting Flag of SFR Register RSTOP RSTS MCM0...
Page 165 CHAPTER 6 CLOCK GENERATOR Table 6-5. CPU Clock Transition and SFR Register Setting Examples (4/4) (9) CPU clock changing from subsystem clock (D) to high-speed system clock (C) (Setting sequence of SFR registers) Note Note Setting Flag of SFR Register AMPH EXCLK OSCSEL...
Page 166: Condition Before Changing Cpu Clock And Processing After Changing Cpu Clock
CHAPTER 6 CLOCK GENERATOR 6.6.7 Condition before changing CPU clock and processing after changing CPU clock Condition before changing the CPU clock and processing after changing the CPU clock are shown below. Table 6-6. Changing CPU Clock CPU Clock Condition Before Change Processing After Change Before Change After Change...
Page 167: Time Required For Switchover Of Cpu Clock And Main System Clock
CHAPTER 6 CLOCK GENERATOR 6.6.8 Time required for switchover of CPU clock and main system clock By setting bits 0 to 2 (PCC0 to PCC2) and bit 4 (CSS) of the processor clock control register (PCC), the CPU clock can be switched (between the main system clock and the subsystem clock) and the division ratio of the main system clock can be changed.
Page 168: Conditions Before Clock Oscillation Is Stopped
CHAPTER 6 CLOCK GENERATOR Table 6-8. Maximum Time Required for Main System Clock Switchover Set Value Before Switchover Set Value After Switchover MCM0 MCM0 1 + 2f clock 1 + 2f clock Caution When switching the internal high-speed oscillation clock to the high-speed system clock, bit 2 (XSEL) of MCM must be set to 1 in advance.
Page 169: Peripheral Hardware And Source Clocks
CHAPTER 6 CLOCK GENERATOR 6.6.10 Peripheral hardware and source clocks The following lists peripheral hardware and source clocks incorporated in the 78K0/KE2. Table 6-10. Peripheral Hardware and Source Clocks Source Clock Peripheral Subsystem Clock Internal Low- TM50 Output External Clock Hardware Clock Speed Oscillation from Peripheral...
Page 170: Chapter 7 16-Bit Timer/Event Counters 00 And 01
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 µ µ PD78F0531, 78F0532, and 78F0533 incorporate 16-bit timer/event counter 00, and the PD78F0534, 78F0535, 78F0536, 78F0537, and 78F0537D incorporate 16-bit timer/event counters 00 and 01. 7.1 Functions of 16-Bit Timer/Event Counters 00 and 01 Note 16-bit timer/event counters 00 and 01 have the following functions.
Page 171: Configuration Of 16-Bit Timer/Event Counters 00 And 01
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 7.2 Configuration of 16-Bit Timer/Event Counters 00 and 01 16-bit timer/event counters 00 and 01 include the following hardware. Table 7-1. Configuration of 16-Bit Timer/Event Counters 00 and 01 Item Configuration Time/counter 16-bit timer counter 0n (TM0n) Register 16-bit timer capture/compare registers 00n, 01n (CR00n, CR01n)
Page 172 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-2. Block Diagram of 16-Bit Timer/Event Counter 01 µ (Available only in the PD78F0534, 78F0535, 78F0536, 78F0537, and 78F0537D) Internal bus Capture/compare control register 01 (CRC01) CRC012CRC011 CRC010 To CR011 INTTM001 16-bit timer capture/compare Noise elimi-...
Page 173 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 The count value of TM0n can be read by reading TM0n when the value of bits 3 and 2 (TMC0n3 and TMC0n2) of 16-bit timer mode control register 0n (TMC0n) is other than 00. The value of TM0n is 0000H if it is read when TMC0n3 and TMC0n2 = 00.
Page 174 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (i) When CR00n is used as a compare register The value set in CR00n is constantly compared with the TM0n count value, and an interrupt request signal (INTTM00n) is generated if they match. The value is held until CR00n is rewritten. (ii) When CR00n is used as a capture register The count value of TM0n is captured to CR00n when a capture trigger is input.
Page 175 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Table 7-2. Capture Operation of CR00n and CR01n External Input Signal TI00n Pin Input TI01n Pin Input Capture Operation Capture operation of CRC0n1 = 1 Set values of ES0n1 and CRC0n1 bit = 0 Set values of ES1n1 and CR00n TI00n pin input...
Page 176: Registers Controlling 16-Bit Timer/Event Counters 00 And 01
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 7.3 Registers Controlling 16-Bit Timer/Event Counters 00 and 01 Registers used to control 16-bit timer/event counters 00 and 01 are shown below. • 16-bit timer mode control register 0n (TMC0n) • Capture/compare control register 0n (CRC0n) •...
Page 177 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-6. Format of 16-Bit Timer Mode Control Register 00 (TMC00) Address: FFBAH After reset: 00H Symbol <0> TMC00 TMC003 TMC002 TMC001 OVF00 TMC003 TMC002 Operation enable of 16-bit timer/event counter 00 Disables TM00 operation.
Page 178 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-7. Format of 16-Bit Timer Mode Control Register 01 (TMC01) Address: FFB6H After reset: 00H Symbol <0> TMC01 TMC013 TMC012 TMC011 OVF01 TMC013 TMC012 Operation enable of 16-bit timer/event counter 01 Disables TM01 operation.
Page 179 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (2) Capture/compare control register 0n (CRC0n) CRC0n is the register that controls the operation of CR00n and CR01n. Changing the value of CRC0n is prohibited during operation (when TMC0n3 and TMC0n2 = other than 00). CRC0n can be set by a 1-bit or 8-bit memory manipulation instruction.
Page 180 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-9. Example of CR01n Capture Operation (When Rising Edge Is Specified) Valid edge Count clock N − 3 N − 2 N − 1 TM0n N + 1 TI00n Rising edge detection CR01n INTTM01n µ...
Page 181 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (3) 16-bit timer output control register 0n (TOC0n) TOC0n is an 8-bit register that controls the TO0n pin output. TOC0n can be rewritten while only OSPT0n is operating (when TMC0n3 and TMC0n2 = other than 00). Rewriting the other bits is prohibited during operation.
Page 182 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-11. Format of 16-Bit Timer Output Control Register 00 (TOC00) Address: FFBDH After reset: 00H Symbol <6> <5> <3> <2> <0> TOC00 OSPT00 OSPE00 TOC004 LVS00 LVR00 TOC001 TOE00 OSPT00 One-shot pulse output trigger via software −...
Page 183 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-12. Format of 16-Bit Timer Output Control Register 01 (TOC01) Address: FFB9H After reset: 00H Symbol <6> <5> <3> <2> <0> TOC01 OSPT01 OSPE01 TOC014 LVS01 LVR01 TOC011 TOE01 OSPT01 One-shot pulse output trigger via software −...
Page 184 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (4) Prescaler mode register 0n (PRM0n) PRM0n is the register that sets the TM0n count clock and TI00n and TI01n pin input valid edges. Rewriting PRM0n is prohibited during operation (when TMC0n3 and TMC0n2 = other than 00). PRM0n can be set by a 1-bit or 8-bit memory manipulation instruction.
Page 185 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-13. Format of Prescaler Mode Register 00 (PRM00) Address: FFBBH After reset: 00H Symbol PRM00 ES101 ES100 ES001 ES000 PRM001 PRM000 ES101 ES100 TI010 pin valid edge selection Falling edge Rising edge Setting prohibited Both falling and rising edges ES001...
Page 186 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-14. Format of Prescaler Mode Register 01 (PRM01) Address: FFB7H After reset: 00H Symbol PRM01 ES111 ES110 ES011 ES010 PRM011 PRM010 ES111 ES110 TI011 pin valid edge selection Falling edge Rising edge Setting prohibited Both falling and rising edges ES011...
Page 187 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (5) Port mode register 0 (PM0) This register sets port 0 input/output in 1-bit units. When using the P01/TO00/TI010 and P06/TO01/TI011 pins for timer output, set PM01 and PM06 and the output latches of P01 and P06 to 0.
Page 188: Operation Of 16-Bit Timer/Event Counters 00 And 01
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 7.4 Operation of 16-Bit Timer/Event Counters 00 and 01 7.4.1 Interval timer operation If bits 3 and 2 (TMC0n3 and TMC0n2) of the 16-bit timer mode control register (TMC0n) are set to 11 (clear & start mode entered upon a match between TM0n and CR00n), the count operation is started in synchronization with the count clock.
Page 189 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-18. Example of Register Settings for Interval Timer Operation (a) 16-bit timer mode control register 0n (TMC0n) TMC0n3 TMC0n2 TMC0n1 OVF0n Clears and starts on match between TM0n and CR00n. (b) Capture/compare control register 0n (CRC0n) CRC0n2 CRC0n1 CRC0n0 CR00n used as compare register...
Page 190 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-19. Example of Software Processing for Interval Timer Function TM0n register 0000H Operable bits (TMC0n3, TMC0n2) CR00n register INTTM00n signal <1> <2> <1> Count operation start flow START Register initial setting Initial setting of these registers is performed before PRM0n register, setting the TMC0n3 and TMC0n2 bits to 11.
Page 191: Square Wave Output Operation
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 7.4.2 Square wave output operation When 16-bit timer/event counter 0n operates as an interval timer (see 7.4.1), a square wave can be output from the TO0n pin by setting the 16-bit timer output control register 0n (TOC0n) to 03H. When TMC0n3 and TMC0n2 are set to 11 (count clear &...
Page 192 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-22. Example of Register Settings for Square Wave Output Operation (a) 16-bit timer mode control register 0n (TMC0n) TMC0n3 TMC0n2 TMC0n1 OVF0n Clears and starts on match between TM0n and CR00n. (b) Capture/compare control register 0n (CRC0n) CRC0n2 CRC0n1 CRC0n0 CR00n used as...
Page 193 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-23. Example of Software Processing for Square Wave Output Function TM0n register 0000H Operable bits (TMC0n3, TMC0n2) CR00n register TO0n pin output INTTM00n signal TO0n output control bit (TOE0n) <1> <2> <1>...
Page 194: External Event Counter Operation
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 7.4.3 External event counter operation When bits 1 and 0 (PRM0n1 and PRM0n0) of the prescaler mode register 0n (PRM0n) are set to 11 (for counting up with the valid edge of the TI00n pin) and bits 3 and 2 (TMC0n3 and TMC0n2) of 16-bit timer mode control register 0n (TMC0n) are set to 11, the valid edge of an external event input is counted, and a match interrupt signal indicating matching between TM0n and CR00n (INTTM00n) is generated.
Page 195 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-25. Example of Register Settings in External Event Counter Mode (a) 16-bit timer mode control register 0n (TMC0n) TMC0n3 TMC0n2 TMC0n1 OVF0n Clears and starts on match between TM0n and CR00n. (b) Capture/compare control register 0n (CRC0n) CRC0n2 CRC0n1 CRC0n0 CR00n used as...
Page 196 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-26. Example of Software Processing in External Event Counter Mode TM0n register 0000H Operable bits (TMC0n3, TMC0n2) Compare register (CR00n) Compare match signal (INTTM00n) <1> <2> <1> Count operation start flow START Register initial setting Initial setting of these registers is performed before...
Page 197: Operation In Clear & Start Mode Entered By Ti00N Pin Valid Edge Input
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 7.4.4 Operation in clear & start mode entered by TI00n pin valid edge input When bits 3 and 2 (TMC0n3 and TMC0n2) of 16-bit timer mode control register 0n (TMC0n) are set to 10 (clear & start mode entered by the TI00n pin valid edge input) and the count clock (set by PRM0n) is supplied to the timer/event counter, TM0n starts counting up.
Page 198 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (1) Operation in clear & start mode entered by TI00n pin valid edge input (CR00n: compare register, CR01n: compare register) Figure 7-27. Block Diagram of Clear & Start Mode Entered by TI00n Pin Valid Edge Input (CR00n: Compare Register, CR01n: Compare Register) Edge TI00n pin...
Page 199 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-28. Timing Example of Clear & Start Mode Entered by TI00n Pin Valid Edge Input (CR00n: Compare Register, CR01n: Compare Register) (a) TOC0n = 13H, PRM0n = 10H, CRC0n, = 00H, TMC0n = 08H TM0n register 0000H Operable bits...
Page 200 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (2) Operation in clear & start mode entered by TI00n pin valid edge input (CR00n: compare register, CR01n: capture register) Figure 7-29. Block Diagram of Clear & Start Mode Entered by TI00n Pin Valid Edge Input (CR00n: Compare Register, CR01n: Capture Register) Edge TI00n pin...
Page 201 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-30. Timing Example of Clear & Start Mode Entered by TI00n Pin Valid Edge Input (CR00n: Compare Register, CR01n: Capture Register) (1/2) (a) TOC0n = 13H, PRM0n = 10H, CRC0n, = 04H, TMC0n = 08H, CR00n = 0001H TM0n register 0000H Operable bits...
Page 202 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-30. Timing Example of Clear & Start Mode Entered by TI00n Pin Valid Edge Input (CR00n: Compare Register, CR01n: Capture Register) (2/2) (b) TOC0n = 13H, PRM0n = 10H, CRC0n, = 04H, TMC0n = 0AH, CR00n = 0003H TM0n register 0003H 0000H...
Page 203 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (3) Operation in clear & start mode by entered TI00n pin valid edge input (CR00n: capture register, CR01n: compare register) Figure 7-31. Block Diagram of Clear & Start Mode Entered by TI00n Pin Valid Edge Input (CR00n: Capture Register, CR01n: Compare Register) Edge TI00n pin...
Page 204 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-32. Timing Example of Clear & Start Mode Entered by TI00n Pin Valid Edge Input (CR00n: Capture Register, CR01n: Compare Register) (1/2) (a) TOC0n = 13H, PRM0n = 10H, CRC0n, = 03H, TMC0n = 08H, CR01n = 0001H TM0n register 0000H Operable bits...
Page 205 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-32. Timing Example of Clear & Start Mode Entered by TI00n Pin Valid Edge Input (CR00n: Capture Register, CR01n: Compare Register) (2/2) (b) TOC0n = 13H, PRM0n = 10H, CRC0n, = 03H, TMC0n = 0AH, CR01n = 0003H TM0n register 0003H 0000H...
Page 206 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (4) Operation in clear & start mode entered by TI00n pin valid edge input (CR00n: capture register, CR01n: capture register) Figure 7-33. Block Diagram of Clear & Start Mode Entered by TI00n Pin Valid Edge Input (CR00n: Capture Register, CR01n: Capture Register) Operable bits TMC0n3, TMC0n2...
Page 207 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-34. Timing Example of Clear & Start Mode Entered by TI00n Pin Valid Edge Input (CR00n: Capture Register, CR01n: Capture Register) (1/3) (a) TOC0n = 13H, PRM0n = 30H, CRC0n = 05H, TMC0n = 0AH TM0n register 0000H Operable bits...
Page 208 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-34. Timing Example of Clear & Start Mode Entered by TI00n Pin Valid Edge Input (CR00n: Capture Register, CR01n: Capture Register) (2/3) (b) TOC0n = 13H, PRM0n = C0H, CRC0n = 05H, TMC0n = 0AH FFFFH TM0n register 0000H...
Page 209 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-34. Timing Example of Clear & Start Mode Entered by TI00n Pin Valid Edge Input (CR00n: Capture Register, CR01n: Capture Register) (3/3) (c) TOC0n = 13H, PRM0n = 00H, CRC0n = 07H, TMC0n = 0AH TM0n register 0000H Operable bits...
Page 210 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-35. Example of Register Settings in Clear & Start Mode Entered by TI00n Pin Valid Edge Input (1/2) (a) 16-bit timer mode control register 0n (TMC0n) TMC0n3 TMC0n2 TMC0n1 OVF0n 0: Inverts TO0n output on match between CR00n and CR01n.
Page 211 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-35. Example of Register Settings in Clear & Start Mode Entered by TI00n Pin Valid Edge Input (2/2) (d) Prescaler mode register 0n (PRM0n) ES1n1 ES1n0 ES0n1 ES0n0 PRM0n1 PRM0n0 Count clock selection (setting TI00n valid edge is prohibited) 00: Falling edge detection 01: Rising edge detection...
Page 212 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-36. Example of Software Processing in Clear & Start Mode Entered by TI00n Pin Valid Edge Input TM0n register 0000H Operable bits (TMC0n3, TMC0n2) Count clear input (TI00n pin input) Compare register (CR00n) Compare match interrupt (INTTM00n)
Page 213: Free-Running Timer Operation
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 7.4.5 Free-running timer operation When bits 3 and 2 (TMC0n3 and TMC0n2) of 16-bit timer mode control register 0n (TMC0n) are set to 01 (free- running timer mode), 16-bit timer/event counter 0n continues counting up in synchronization with the count clock. When it has counted up to FFFFH, the overflow flag (OVF0n) is set to 1 at the next clock, and TM0n is cleared (to 0000H) and continues counting.
Page 214 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-38. Timing Example of Free-Running Timer Mode (CR00n: Compare Register, CR01n: Compare Register) • TOC0n = 13H, PRM0n = 00H, CRC0n = 00H, TMC0n = 04H FFFFH TM0n register 0000H Operable bits (TMC0n3, TMC0n2) Compare register (CR00n)
Page 215 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-40. Timing Example of Free-Running Timer Mode (CR00n: Compare Register, CR01n: Capture Register) • TOC0n = 13H, PRM0n = 10H, CRC0n = 04H, TMC0n = 04H FFFFH TM0n register 0000H Operable bits (TMC0n3, TMC0n2) Capture trigger input (TI00n)
Page 216 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (3) Free-running timer mode operation (CR00n: capture register, CR01n: capture register) Figure 7-41. Block Diagram of Free-Running Timer Mode (CR00n: Capture Register, CR01n: Capture Register) Operable bits TMC0n3, TMC0n2 Timer counter Count clock (TM0n) Capture register Interrupt signal...
Page 217 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-42. Timing Example of Free-Running Timer Mode (CR00n: Capture Register, CR01n: Capture Register) (1/2) (a) TOC0n = 13H, PRM0n = 50H, CRC0n = 05H, TMC0n = 04H FFFFH TM0n register 0000H Operable bits (TMC0n3, TMC0n2) Capture trigger input...
Page 218 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-42. Timing Example of Free-Running Timer Mode (CR00n: Capture Register, CR01n: Capture Register) (2/2) (b) TOC0n = 13H, PRM0n = C0H, CRC0n = 05H, TMC0n = 04H FFFFH TM0n register 0000H Operable bits (TMC0n3, TMC0n2) Capture trigger input...
Page 219 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-43. Example of Register Settings in Free-Running Timer Mode (1/2) (a) 16-bit timer mode control register 0n (TMC0n) TMC0n3 TMC0n2 TMC0n1 OVF0n 0: Inverts TO0n pin output on match between CR00n and CR01n. 1: Inverts TO0n pin output on match between CR00n and CR01n and valid edge of TI00n pin.
Page 220 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-43. Example of Register Settings in Free-Running Timer Mode (2/2) (d) Prescaler mode register 0n (PRM0n) ES1n1 ES1n0 ES0n1 ES0n0 PRM0n1 PRM0n0 Count clock selection (setting TI00n valid edge is prohibited) 00: Falling edge detection 01: Rising edge detection 10: Setting prohibited...
Page 221 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-44. Example of Software Processing in Free-Running Timer Mode FFFFH TM0n register 0000H Operable bits (TMC0n3, TMC0n2) Compare register (CR00n) Compare match interrupt (INTTM00n) Compare register (CR01n) Compare match interrupt (INTTM01n) Timer output control bits (TOE0n, TOC0n4, TOC0n1) TO0n pin output...
Page 222: Ppg Output Operation
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 7.4.6 PPG output operation A square wave having a pulse width set in advance by CR01n is output from the TO0n pin as a PPG (Programmable Pulse Generator) signal during a cycle set by CR00n when bits 3 and 2 (TMC0n3 and TMC0n2) of 16- bit timer mode control register 0n (TMC0n) are set to 11 (clear &...
Page 223 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-46. Example of Register Settings for PPG Output Operation (a) 16-bit timer mode control register 0n (TMC0n) TMC0n3 TMC0n2 TMC0n1 OVF0n Clears and starts on match between TM0n and CR00n. (b) Capture/compare control register 0n (CRC0n) CRC0n2 CRC0n1 CRC0n0 CR00n used as compare register...
Page 224 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-47. Example of Software Processing for PPG Output Operation TM0n register 0000H Operable bits (TMC0n3, TMC0n2) Compare register (CR00n) Compare match interrupt (INTTM00n) Compare register (CR01n) Compare match interrupt (INTTM01n) Timer output control bits (TOE0n, TOC0n4, TOC0n1) TO0n pin output N + 1...
Page 225: One-Shot Pulse Output Operation
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 7.4.7 One-shot pulse output operation A one-shot pulse can be output by setting bits 3 and 2 (TMC0n3 and TMC0n2) of the 16-bit timer mode control register 0n (TMC0n) to 01 (free-running timer mode) or to 10 (clear & start mode entered by the TI00n pin valid edge) and setting bit 5 (OSPE0n) of 16-bit timer output control register 0n (TOC0n) to 1.
Page 226 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-49. Example of Register Settings for One-Shot Pulse Output Operation (1/2) (a) 16-bit timer mode control register 0n (TMC0n) TMC0n3 TMC0n2 TMC0n1 OVF0n 01: Free running timer mode 10: Clear and start mode by valid edge of TI00n pin.
Page 227 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-49. Example of Register Settings for One-Shot Pulse Output Operation (2/2) (e) 16-bit timer counter 0n (TM0n) By reading TM0n, the count value can be read. (f) 16-bit capture/compare register 00n (CR00n) This register is used as a compare register when a one-shot pulse is output.
Page 228 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-50. Example of Software Processing for One-Shot Pulse Output Operation (1/2) FFFFH TM0n register 0000H Operable bits 01 or 10 (TMC0n3, TMC0n2) One-shot pulse enable bit (OSPEn) One-shot pulse trigger bit (OSPTn) One-shot pulse trigger input (TI00n pin)
Page 229 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-50. Example of Software Processing for One-Shot Pulse Output Operation (2/2) <1> Count operation start flow START Register initial setting Initial setting of these registers is performed PRM0n register, before setting the TMC0n3 and TMC0n2 bits. CRC0n register, Note TOC0n register...
Page 230: Pulse Width Measurement Operation
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 7.4.8 Pulse width measurement operation TM0n can be used to measure the pulse width of the signal input to the TI00n and TI01n pins. Measurement can be accomplished by operating the 16-bit timer/event counter 0n in the free-running timer mode or by restarting the timer in synchronization with the signal input to the TI00n pin.
Page 231 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 A pulse width can be measured in the following three ways. • Measuring the pulse width by using two input signals of the TI00n and TI01n pins (free-running timer mode) • Measuring the pulse width by using one input signal of the TI00n pin (free-running timer mode) •...
Page 232 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-53. Timing Example of Pulse Width Measurement (1) • TMC0n = 04H, PRM0n = F0H, CRC0n = 05H FFFFH TM0n register 0000H Operable bits (TMC0n3, TMC0n2) Capture trigger input (TI00n) Capture register 0000H (CR01n) Capture interrupt...
Page 233 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (2) Measuring the pulse width by using one input signal of the TI00n pin (free-running mode) Set the free-running timer mode (TMC0n3 and TMC0n2 = 01). The count value of TM0n is captured to CR00n in the phase reverse to the valid edge detected on the TI00n pin.
Page 234 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (3) Measuring the pulse width by using one input signal of the TI00n pin (clear & start mode entered by the TI00n pin valid edge input) Set the clear & start mode entered by the TI00n pin valid edge (TMC0n3 and TMC0n2 = 10). The count value of TM0n is captured to CR00n in the phase reverse to the valid edge of the TI00n pin, and the count value of TM0n is captured to CR01n and TM0n is cleared (0000H) when the valid edge of the TI00n pin is detected.
Page 235 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-56. Example of Register Settings for Pulse Width Measurement (1/2) (a) 16-bit timer mode control register 0n (TMC0n) TMC0n3 TMC0n2 TMC0n1 OVF0n 01: Free running timer mode 10: Clear and start mode entered by valid edge of TI00n pin.
Page 236 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-56. Example of Register Settings for Pulse Width Measurement (2/2) (e) 16-bit timer counter 0n (TM0n) By reading TM0n, the count value can be read. (f) 16-bit capture/compare register 00n (CR00n) This register is used as a capture register.
Page 237 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-57. Example of Software Processing for Pulse Width Measurement (1/2) (a) Example of free-running timer mode Preliminary User’s Manual U17260EJ3V1UD...
Page 238 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-57. Example of Software Processing for Pulse Width Measurement (2/2) <1> Count operation start flow START Register initial setting Initial setting of these registers is performed PRM0n register, before setting the TMC0n3 and TMC0n2 bits. CRC0n register, port setting TMC0n3, TMC0n2 bits =...
Page 239: Special Use Of Tm0N
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 7.5 Special Use of TM0n 7.5.1 Rewriting CR01n during TM0n operation In principle, rewriting CR00n and CR01n of the 78K0/KE2 when they are used as compare registers is prohibited while TM0n is operating (TMC0n3 and TMC0n2 = other than 00). However, the value of CR01n can be changed, even while TM0n is operating, using the following procedure if CR01n is used for PPG output and the duty factor is changed (change the value of CR01n immediately after its value matches the value of TM0n.
Page 240 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (2) Setting LVS0n and LVR0n Set LVS0n and LVR0n using the following procedure. Figure 7-58. Example of Flow for Setting LVS0n and LVR0n Bits Setting TOC0n.OSPE0n, TOC0n4, TOC0n1 bits <1> Setting of timer output operation Setting TOC0n.TOE0n Setting...
Page 241: Cautions For 16-Bit Timer/Event Counters 00 And 01
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 7.6 Cautions for 16-Bit Timer/Event Counters 00 and 01 (1) Restrictions for each channel of 16-bit timer/event counter 0n Table 7-5 shows the restrictions for each channel. Table 7-5. Restrictions for Each Channel of 16-Bit Timer/Event Counter 0n Operation Restriction −...
Page 242 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (4) Timing of holding data by capture register (a) When the valid edge is input to the TI00n/TI01n pin and the reverse phase of the TI00n pin is detected while CR00n/CR01n is read, CR01n performs a capture operation but the read value of CR00n/CR01n is not guaranteed.
Page 243 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (7) Operation of OVF0n flag (a) Setting OVF0n flag (1) The OVF0n flag is set to 1 in the following case, as well as when TM0n overflows. Select the clear & start mode entered upon a match between TM0n and CR00n. ↓...
Page 244 CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (9) Capture operation (a) When valid edge of TI00n is specified as count clock When the valid edge of TI00n is specified as the count clock, the capture register for which TI00n is specified as a trigger does not operate correctly.
Page 245: Chapter 8 8-Bit Timer/Event Counters 50 And 51
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 8.1 Functions of 8-Bit Timer/Event Counters 50 and 51 8-bit timer/event counters 50 and 51 have the following functions. • Interval timer • External event counter • Square-wave output • PWM output 8.2 Configuration of 8-Bit Timer/Event Counters 50 and 51 8-bit timer/event counters 50 and 51 include the following hardware.
Page 246 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 8-1. Block Diagram of 8-Bit Timer/Event Counter 50 Internal bus 8-bit timer compare Selector INTTM50 register 50 (CR50) TI50/TO50/P17 Note 1 To TMH0 Match To UART0 To UART6 8-bit timer TO50/TI50/ counter 50 (TM50) Note 2 Output latch...
Page 247 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (1) 8-bit timer counter 5n (TM5n) TM5n is an 8-bit register that counts the count pulses and is read-only. The counter is incremented in synchronization with the rising edge of the count clock. Figure 8-3.
Page 248: Registers Controlling 8-Bit Timer/Event Counters 50 And 51
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 8.3 Registers Controlling 8-Bit Timer/Event Counters 50 and 51 The following four registers are used to control 8-bit timer/event counters 50 and 51. • Timer clock selection register 5n (TCL5n) • 8-bit timer mode control register 5n (TMC5n) •...
Page 249 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 8-6. Format of Timer Clock Selection Register 51 (TCL51) Address: FF8CH After reset: 00H Symbol TCL51 TCL512 TCL511 TCL510 TCL512 TCL511 TCL510 Count clock selection 2 MHz 5 MHz 10 MHz 20 MHz TI51 pin falling edge TI51 pin rising edge...
Page 250 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (2) 8-bit timer mode control register 5n (TMC5n) TMC5n is a register that performs the following five types of settings. <1> 8-bit timer counter 5n (TM5n) count operation control <2> 8-bit timer counter 5n (TM5n) operating mode selection <3>...
Page 251 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 8-8. Format of 8-Bit Timer Mode Control Register 51 (TMC51) Note Address: FF43H After reset: 00H Symbol <7> <3> <2> <0> TMC51 TCE51 TMC516 LVS51 LVR51 TMC511 TOE51 TCE51 TM51 count operation control After clearing to 0, count operation disabled (counter stopped) Count operation start TMC516...
Page 252 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (3) Port mode registers 1 and 3 (PM1, PM3) These registers set port 1 and 3 input/output in 1-bit units. When using the P17/TO50/TI50 and P33/TO51/TI51/INTP4 pins for timer output, clear PM17 and PM33 and the output latches of P17 and P33 to 0.
Page 253: Operations Of 8-Bit Timer/Event Counters 50 And 51
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 8.4 Operations of 8-Bit Timer/Event Counters 50 and 51 8.4.1 Operation as interval timer 8-bit timer/event counter 5n operates as an interval timer that generates interrupt requests repeatedly at intervals of the count value preset to 8-bit timer compare register 5n (CR5n). When the count value of 8-bit timer counter 5n (TM5n) matches the value set to CR5n, counting continues with the TM5n value cleared to 0 and an interrupt request signal (INTTM5n) is generated.
Page 254 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 8-11. Interval Timer Operation Timing (2/2) (b) When CR5n = 00H Count clock TM5n CR5n TCE5n INTTM5n Interval time (c) When CR5n = FFH Count clock TM5n FEH FFH 00H CR5n TCE5n INTTM5n Interrupt acknowledged...
Page 255: Operation As External Event Counter
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 8.4.2 Operation as external event counter The external event counter counts the number of external clock pulses to be input to the TI5n pin by 8-bit timer counter 5n (TM5n). TM5n is incremented each time the valid edge specified by timer clock selection register 5n (TCL5n) is input. Either the rising or falling edge can be selected.
Page 256: Square-Wave Output Operation
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 8.4.3 Square-wave output operation A square wave with any selected frequency is output at intervals determined by the value preset to 8-bit timer compare register 5n (CR5n). The TO5n pin output status is inverted at intervals determined by the count value preset to CR5n by setting bit 0 (TOE5n) of 8-bit timer mode control register 5n (TMC5n) to 1.
Page 257: Pwm Output Operation
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 8-13. Square-Wave Output Operation Timing Count clock N − 1 N − 1 TM5n count value Count start CR5n Note TO5n Note The initial value of TO5n output can be set by bits 2 and 3 (LVR5n, LVS5n) of 8-bit timer mode control register 5n (TMC5n).
Page 258 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (1) PWM output basic operation Setting <1> Set each register. • Clear the port output latch (P17 or P33) Note Note and port mode register (PM17 or PM33) to 0. • TCL5n: Select the count clock. •...
Page 259 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 8-14. PWM Output Operation Timing (a) Basic operation (active level = H) Count clock TM5n 00H 01H FFH 00H 01H 02H N N + 1 FFH 00H 01H 02H CR5n TCE5n INTTM5n TO5n <2>...
Page 260 CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (2) Operation with CR5n changed Figure 8-15. Timing of Operation with CR5n Changed (a) CR5n value is changed from N to M before clock rising edge of FFH → Value is transferred to CR5n at overflow immediately after change. Count clock TM5n N N + 1 N + 2...
Page 261: Cautions For 8-Bit Timer/Event Counters 50 And 51
CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51 8.5 Cautions for 8-Bit Timer/Event Counters 50 and 51 (1) Timer start error An error of up to one clock may occur in the time required for a match signal to be generated after timer start. This is because 8-bit timer counters 50 and 51 (TM50, TM51) are started asynchronously to the count clock.
Page 262: Chapter 9 8-Bit Timers H0 And H1
CHAPTER 9 8-BIT TIMERS H0 AND H1 9.1 Functions of 8-Bit Timers H0 and H1 8-bit timers H0 and H1 have the following functions. • Interval timer • Square-wave output • PWM output • Carrier generator (8-bit timer H1 only) 9.2 Configuration of 8-Bit Timers H0 and H1 8-bit timers H0 and H1 include the following hardware.
Page 263 Figure 9-1. Block Diagram of 8-Bit Timer H0 Internal bus 8-bit timer H mode register 0 (TMHMD0) TMHE0 CKS02 CKS01 CKS00 TMMD01 TMMD00 TOLEV0 TOEN0 8-bit timer H 8-bit timer H compare register compare register 00 (CMP00) 10 (CMP10) Decoder TOH0/P15 Selector Output latch...
Page 264 Figure 9-2. Block Diagram of 8-Bit Timer H1 Internal bus 8-bit timer H mode 8-bit timer H carrier register 1 (TMHMD1) control register 1 (TMCYC1) TMHE1 CKS12 CKS11 CKS10 TMMD11 TMMD10 TOLEV1 TOEN1 8-bit timer H 8-bit timer H RMC1 NRZB1 NRZ1 compare compare register 1 1...
Page 265 CHAPTER 9 8-BIT TIMERS H0 AND H1 (1) 8-bit timer H compare register 0n (CMP0n) This register can be read or written by an 8-bit memory manipulation instruction. This register is used in all of the timer operation modes. This register constantly compares the value set to CMP0n with the count value of the 8-bit timer counter Hn and, when the two values match, generates an interrupt request signal (INTTMHn) and inverts the output level of TOHn.
Page 266: Registers Controlling 8-Bit Timers H0 And H1
CHAPTER 9 8-BIT TIMERS H0 AND H1 9.3 Registers Controlling 8-Bit Timers H0 and H1 The following four registers are used to control 8-bit timers H0 and H1. • 8-bit timer H mode register n (TMHMDn) • 8-bit timer H carrier control register 1 (TMCYC1) Note •...
Page 267 CHAPTER 9 8-BIT TIMERS H0 AND H1 Figure 9-5. Format of 8-Bit Timer H Mode Register 0 (TMHMD0) Address: FF69H After reset: 00H <7> <1> <0> TMHMD0 TMHE0 CKS02 CKS01 CKS00 TMMD01 TMMD00 TOLEV0 TOEN0 TMHE0 Timer operation enable Stops timer count operation (counter is cleared to 0) Enables timer count operation (count operation started by inputting clock) CKS02 CKS01...
Page 268 CHAPTER 9 8-BIT TIMERS H0 AND H1 Cautions 1. When TMHE0 = 1, setting the other bits of TMHMD0 is prohibited. 2. In the PWM output mode, be sure to set the 8-bit timer H compare register 10 (CMP10) when starting the timer count operation (TMHE0 = 1) after the timer count operation was stopped (TMHE0 = 0) (be sure to set again even if setting the same value to CMP10).
Page 269 CHAPTER 9 8-BIT TIMERS H0 AND H1 Figure 9-6. Format of 8-Bit Timer H Mode Register 1 (TMHMD1) Address: FF6CH After reset: 00H <7> <1> <0> TMHMD1 TMHE1 CKS12 CKS11 CKS10 TMMD11 TMMD10 TOLEV1 TOEN1 TMHE1 Timer operation enable Stops timer count operation (counter is cleared to 0) Enables timer count operation (count operation started by inputting clock) CKS12 CKS11...
Page 270 CHAPTER 9 8-BIT TIMERS H0 AND H1 (2) 8-bit timer H carrier control register 1 (TMCYC1) This register controls the remote control output and carrier pulse output status of 8-bit timer H1. This register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 00H.
Page 271: Operation Of 8-Bit Timers H0 And H1
CHAPTER 9 8-BIT TIMERS H0 AND H1 9.4 Operation of 8-Bit Timers H0 and H1 9.4.1 Operation as interval timer/square-wave output When the 8-bit timer counter Hn and compare register 0n (CMP0n) match, an interrupt request signal (INTTMHn) is generated and the 8-bit timer counter Hn is cleared to 00H. Compare register 1n (CMP1n) is not used in interval timer mode.
Page 272 CHAPTER 9 8-BIT TIMERS H0 AND H1 Figure 9-10. Timing of Interval Timer/Square-Wave Output Operation (1/2) (a) Basic operation (Operation When 01H ≤ CMP0n ≤ FEH) Count clock Count start 01H 00H 8-bit timer counter Hn Clear Clear CMP0n TMHEn INTTMHn Interval time TOHn...
Page 273 CHAPTER 9 8-BIT TIMERS H0 AND H1 Figure 9-10. Timing of Interval Timer/Square-Wave Output Operation (2/2) (b) Operation when CMP0n = FFH Count clock Count start 8-bit timer counter Hn Clear Clear CMP0n TMHEn INTTMHn TOHn Interval time (c) Operation when CMP0n = 00H Count clock Count start 8-bit timer counter Hn...
Page 274: Operation As Pwm Output
CHAPTER 9 8-BIT TIMERS H0 AND H1 9.4.2 Operation as PWM output In PWM output mode, a pulse with an arbitrary duty and arbitrary cycle can be output. The 8-bit timer compare register 0n (CMP0n) controls the cycle of timer output (TOHn). Rewriting the CMP0n register during timer operation is prohibited.
Page 275 CHAPTER 9 8-BIT TIMERS H0 AND H1 <5> By performing procedures <3> and <4> repeatedly, a pulse with an arbitrary duty can be obtained. <6> To stop the count operation, set TMHEn = 0. If the setting value of the CMP0n register is N, the setting value of the CMP1n register is M, and the count clock frequency is f , the PWM pulse output cycle and duty are as follows.
Page 276 CHAPTER 9 8-BIT TIMERS H0 AND H1 Figure 9-12. Operation Timing in PWM Output Mode (1/4) (a) Basic operation Count clock 8-bit timer counter Hn 00H 01H A5H 00H 01H 02H A5H 00H 01H 02H A5H 00H CMP0n CMP1n TMHEn INTTMHn TOHn (TOLEVn = 0)
Page 277 CHAPTER 9 8-BIT TIMERS H0 AND H1 Figure 9-12. Operation Timing in PWM Output Mode (2/4) (b) Operation when CMP0n = FFH, CMP1n = 00H Count clock 8-bit timer counter Hn 00H 01H FFH 00H 01H 02H FFH 00H 01H 02H FFH 00H CMP0n CMP1n...
Page 278 CHAPTER 9 8-BIT TIMERS H0 AND H1 Figure 9-12. Operation Timing in PWM Output Mode (3/4) (d) Operation when CMP0n = 01H, CMP1n = 00H Count clock 01H 00H 01H 00H 00H 01H 00H 01H 8-bit timer counter Hn CMP0n CMP1n TMHEn INTTMHn...
Page 279 CHAPTER 9 8-BIT TIMERS H0 AND H1 Figure 9-12. Operation Timing in PWM Output Mode (4/4) (e) Operation by changing CMP1n (CMP1n = 02H → 03H, CMP0n = A5H) Count clock 8-bit timer 00H 01H 02H A5H 00H 01H 02H 03H A5H 00H 01H 02H 03H A5H 00H counter Hn...
Page 280: Carrier Generator Operation (8-Bit Timer H1 Only)
CHAPTER 9 8-BIT TIMERS H0 AND H1 9.4.3 Carrier generator operation (8-bit timer H1 only) In the carrier generator mode, the 8-bit timer H1 is used to generate the carrier signal of an infrared remote controller, and the 8-bit timer/event counter 51 is used to generate an infrared remote control signal (time count). The carrier clock generated by the 8-bit timer H1 is output in the cycle set by the 8-bit timer/event counter 51.
Page 281 CHAPTER 9 8-BIT TIMERS H0 AND H1 To control the carrier pulse output during a count operation, the NRZ1 and NRZB1 bits of the TMCYC1 register have a master and slave bit configuration. The NRZ1 bit is read-only but the NRZB1 bit can be read and written. The INTTM51 signal is synchronized with the 8-bit timer H1 count clock and is output as the INTTM5H1 signal.
Page 282 CHAPTER 9 8-BIT TIMERS H0 AND H1 Setting <1> Set each register. Figure 9-14. Register Setting in Carrier Generator Mode Setting 8-bit timer H mode register 1 (TMHMD1) TMHE1 CKS12 CKS11 CKS10 TMMD11 TMMD10 TOLEV1 TOEN1 TMHMD1 Timer output enabled Default setting of timer output level Carrier generator mode selection Count clock (f...
Page 283 CHAPTER 9 8-BIT TIMERS H0 AND H1 <10> By performing the procedures above, an arbitrary carrier Preliminary User’s Manual U17260EJ3V1UD...
Page 284 CHAPTER 9 8-BIT TIMERS H0 AND H1 Figure 9-15. Carrier Generator Mode Operation Timing (1/3) (a) Operation when CMP01 = N, CMP11 = N N 00H N 00H N 00H N 00H N 00H CMP01 CMP11 TMHE11 INTTMH1 Carrier clock 8-bit timer 51 count clock TM51 count value...
Page 285 CHAPTER 9 8-BIT TIMERS H0 AND H1 Figure 9-15. Carrier Generator Mode Operation Timing (2/3) (b) Operation when CMP01 = N, CMP11 = M 8-bit timer H1 count clock 8-bit timer counter N 00H 01H M 00H N 00H 01H M 00H H1 count value CMP01...
Page 286 CHAPTER 9 8-BIT TIMERS H0 AND H1 Figure 9-15. Carrier Generator Mode Operation Timing (3/3) (c) Operation when CMP11 is changed 8-bit timer H1 count clock 8-bit timer counter 00H 01H 00H 01H H1 count value CMP01 <3> <3>’ CMP11 M (L) TMHE1 INTTMH1...
Page 287: Chapter 10 Watch Timer
CHAPTER 10 WATCH TIMER 10.1 Functions of Watch Timer The watch timer has the following functions. • Watch timer • Interval timer The watch timer and the interval timer can be used simultaneously. Figure 10-1 shows the watch timer block diagram. Figure 10-1.
Page 288: Configuration Of Watch Timer
CHAPTER 10 WATCH TIMER (1) Watch timer When the peripheral hardware clock or subsystem clock is used, interrupt request signals (INTWT) are generated at preset intervals. Table 10-1. Watch Timer Interrupt Time Interrupt Time When Operated at When Operated at When Operated at When Operated at When Operated at...
Page 289: Register Controlling Watch Timer
CHAPTER 10 WATCH TIMER 10.3 Register Controlling Watch Timer The watch timer is controlled by the watch timer operation mode register (WTM). • Watch timer operation mode register (WTM) This register sets the watch timer count clock, enables/disables operation, prescaler interval time, and 5-bit counter operation control.
Page 290 CHAPTER 10 WATCH TIMER Caution Do not change the count clock and interval time (by setting bits 4 to 7 (WTM4 to WTM7) of WTM) during watch timer operation. Remarks 1. f Watch timer clock frequency (f or f 2. f : Peripheral hardware clock frequency 3.
Page 291: Watch Timer Operations
CHAPTER 10 WATCH TIMER 10.4 Watch Timer Operations 10.4.1 Watch timer operation The watch timer generates an interrupt request signal (INTWT) at a specific time interval by using the peripheral hardware clock or subsystem clock. When bit 0 (WTM0) and bit 1 (WTM1) of the watch timer operation mode register (WTM) are set to 1, the count operation starts.
Page 292: Cautions For Watch Timer
CHAPTER 10 WATCH TIMER Figure 10-3. Operation Timing of Watch Timer/Interval Timer 5-bit counter Overflow Overflow Start Count clock Watch timer interrupt INTWT Interrupt time of watch timer (0.5 s) Interrupt time of watch timer (0.5 s) Interval timer interrupt INTWTI Interval time Remark : Watch timer clock frequency...
Page 293: Chapter 11 Watchdog Timer
CHAPTER 11 WATCHDOG TIMER 11.1 Functions of Watchdog Timer The watchdog timer operates on the internal low-speed oscillation clock. The watchdog timer is used to detect an inadvertent program loop. If a program loop is detected, an internal reset signal is generated. Program loop is detected in the following cases.
Page 294: Configuration Of Watchdog Timer
CHAPTER 11 WATCHDOG TIMER 11.2 Configuration of Watchdog Timer The watchdog timer includes the following hardware. Table 11-1. Configuration of Watchdog Timer Item Configuration Control register Watchdog timer enable register (WDTE) How the counter operation is controlled, overflow time, and window open period are set by the option byte. Table 11-2.
Page 295: Register Controlling Watchdog Timer
CHAPTER 11 WATCHDOG TIMER 11.3 Register Controlling Watchdog Timer The watchdog timer is controlled by the watchdog timer enable register (WDTE). (1) Watchdog timer enable register (WDTE) Writing ACH to WDTE clears the watchdog timer counter and starts counting again. This register can be set by an 8-bit memory manipulation instruction.
Page 296: Operation Of Watchdog Timer
CHAPTER 11 WATCHDOG TIMER 11.4 Operation of Watchdog Timer 11.4.1 Controlling operation of watchdog timer When the watchdog timer is used, its operation is specified by the option byte (0080H). • Enable counting operation of the watchdog timer by setting bit 4 (WDTON) of the option byte (0080H) to 1 (the counter starts operating after a reset release) (for details, see CHAPTER 25).
Page 297: Setting Overflow Time Of Watchdog Timer
CHAPTER 11 WATCHDOG TIMER Cautions 4. The operation of the watchdog timer in the HALT and STOP modes differs as follows depending on the set value of bit 0 (LSROSC) of the option byte. LSROSC = 0 (Internal Low-Speed LSROSC = 1 (Internal Low-Speed Oscillator Can Be Stopped by Software) Oscillator Cannot Be Stopped) In HALT mode...
Page 298: Setting Window Open Period Of Watchdog Timer
CHAPTER 11 WATCHDOG TIMER 11.4.3 Setting window open period of watchdog timer Set the window open period of the watchdog timer by using bits 6 and 5 (WINDOW1, WINDOW0) of the option byte (0080H). The outline of the window is as follows. •...
Page 299 CHAPTER 11 WATCHDOG TIMER Remark If the overflow time is set to 2 , the window close time and open time are as follows. Setting of Window Open Period 100% Window close time 0 to 3.56 ms 0 to 2.37 ms 0 to 0.119 ms None Window open time...
Page 300: Chapter 12 Clock Output/Buzzer Output Controller
CHAPTER 12 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER 12.1 Functions of Clock Output/Buzzer Output Controller The clock output controller is intended for carrier output during remote controlled transmission and clock output for supply to peripheral ICs. The clock selected with the clock output selection register (CKS) is output. In addition, the buzzer output is intended for square-wave output of buzzer frequency selected with CKS.
Page 301: Configuration Of Clock Output/Buzzer Output Controller
CHAPTER 12 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER 12.2 Configuration of Clock Output/Buzzer Output Controller The clock output/buzzer output controller includes the following hardware. Table 12-1. Configuration of Clock Output/Buzzer Output Controller Item Configuration Control registers Clock output selection register (CKS) Port mode register 14 (PM14) Port register 14 (P14) 12.3 Registers Controlling Clock Output/Buzzer Output Controller The following two registers are used to control the clock output/buzzer output controller.
Page 302 CHAPTER 12 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER Figure 12-2. Format of Clock Output Selection Register (CKS) Address: FF40H After reset: 00H Symbol <7> <4> BZOE BCS1 BCS0 CLOE CCS3 CCS2 CCS1 CCS0 BZOE BUZ output enable/disable specification Clock division circuit operation stopped. BUZ fixed to low level. Clock division circuit operation enabled.
Page 303: Operations Of Clock Output/Buzzer Output Controller
CHAPTER 12 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER (2) Port mode register 14 (PM14) This register sets port 14 input/output in 1-bit units. When using the P140/INTP6/PCL pin for clock output and the P141/INTP7/BUZ pin for buzzer output, clear PM140 and PM141 and the output latches of P140 and P141 to 0. PM14 is set by a 1-bit or 8-bit memory manipulation instruction.
Page 304: Chapter 13 A/D Converter
CHAPTER 13 A/D CONVERTER 13.1 Function of A/D Converter The A/D converter converts an analog input signal into a digital value, and consists of up to eight channels (ANI0 to ANI7) with a resolution of 10 bits. The A/D converter has the following function. •...
Page 305: Configuration Of A/D Converter
CHAPTER 13 A/D CONVERTER 13.2 Configuration of A/D Converter The A/D converter includes the following hardware. (1) ANI0 to ANI7 pins These are the analog input pins of the 8-channel A/D converter. They input analog signals to be converted into digital signals.
Page 306 CHAPTER 13 A/D CONVERTER (7) 8-bit A/D conversion result register (ADCRH) The A/D conversion result is loaded from the successive approximation register to this register each time A/D conversion is completed, and the ADCRH register stores the higher 8 bits of the A/D conversion result. Caution When data is read from ADCR and ADCRH, a wait cycle is generated.
Page 307: Registers Used In A/D Converter
CHAPTER 13 A/D CONVERTER 13.3 Registers Used in A/D Converter The A/D converter uses the following six registers. • A/D converter mode register (ADM) • A/D port configuration register (ADPC) • Analog input channel specification register (ADS) • Port mode register 2 (PM2) •...
Page 308 CHAPTER 13 A/D CONVERTER Figure 13-4. Timing Chart When Comparator Is Used Comparator: 1/2AV operation ADCE Comparator Conversion Conversion Conversion Conversion operation waiting operation stopped ADCS Note Note To stabilize the internal circuit, the time from the rising of the ADCE bit to the falling of the ADCS bit must be µ...
Page 309 CHAPTER 13 A/D CONVERTER Table 13-2. A/D Conversion Time Selection (1) 2.7 V ≤ AV ≤ 5.5 V A/D Converter Mode Register (ADM) Conversion Time Selection Conversion Time Configuration Conversion Clock Sampling Successive ADCR Note 2 MHz 10 MHz 20 MHz Clear Conversion Transfer,...
Page 310 CHAPTER 13 A/D CONVERTER Figure 13-5. A/D Converter Sampling and A/D Conversion Timing ← ADCS 1 or ADS rewrite ADCS Sampling timing INTAD Wait Sampling time Successive Sampling time Transfer Note period clear conversion time to ADCR, clear INTAD generation Conversion time Conversion time Note For details of wait period, see CHAPTER 31 CAUTIONS FOR WAIT.
Page 311 CHAPTER 13 A/D CONVERTER (3) 8-bit A/D conversion result register (ADCRH) This register is an 8-bit register that stores the A/D conversion result. The higher 8 bits of 10-bit resolution are stored. ADCRH can be read by an 8-bit memory manipulation instruction. Reset signal generation sets this register to 00H.
Page 312 CHAPTER 13 A/D CONVERTER (4) Analog input channel specification register (ADS) This register specifies the input channel of the analog voltage to be A/D converted. ADS can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 00H. Figure 13-8.
Page 313 CHAPTER 13 A/D CONVERTER (5) A/D port configuration register (ADPC) This register switches the ANI0/P20 to ANI7/P27 pins to analog input of A/D converter or digital I/O of port. ADPC can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 00H.
Page 314 CHAPTER 13 A/D CONVERTER (6) Port mode register 2 (PM2) When using the ANI0/P20 to ANI7/P27 pins for analog input port, set PM20 to PM27 to 1. The output latches of P20 to P27 at this time may be 0 or 1. If PM20 to PM27 are set to 0, they cannot be used as analog input port pins.
Page 315: A/D Converter Operations
CHAPTER 13 A/D CONVERTER 13.4 A/D Converter Operations 13.4.1 Basic operations of A/D converter <1> Set bit 0 (ADCE) of the A/D converter mode register (ADM) to 1 to start the operation of the comparator. <2> Set channels for A/D conversion to analog input by using the A/D port configuration register (ADPC) and set to input mode by using port mode register 2 (PM2).
Page 316 CHAPTER 13 A/D CONVERTER Figure 13-11. Basic Operation of A/D Converter Conversion time Sampling time A/D converter Sampling A/D conversion operation Conversion Undefined result Conversion ADCR result INTAD A/D conversion operations are performed continuously until bit 7 (ADCS) of the A/D converter mode register (ADM) is reset (0) by software.
Page 317: Input Voltage And Conversion Results
CHAPTER 13 A/D CONVERTER 13.4.2 Input voltage and conversion results The relationship between the analog input voltage input to the analog input pins (ANI0 to ANI7) and the theoretical A/D conversion result (stored in the 10-bit A/D conversion result register (ADCR)) is shown by the following expression.
Page 318: A/D Converter Operation Mode
CHAPTER 13 A/D CONVERTER 13.4.3 A/D converter operation mode The operation mode of the A/D converter is the select mode. One channel of analog input is selected from ANI0 to ANI7 by the analog input channel specification register (ADS) and A/D conversion is executed. (1) A/D conversion operation By setting bit 7 (ADCS) of the A/D converter mode register (ADM) to 1, the A/D conversion operation of the voltage, which is applied to the analog input pin specified by the analog input channel specification register...
Page 319 CHAPTER 13 A/D CONVERTER The setting methods are described below. <1> Set bit 0 (ADCE) of the A/D converter mode register (ADM) to 1. <2> Set the channel to be used in the analog input mode by using bits 3 to 0 (ADPC3 to ADPC0) of the A/D port configuration register (ADPC) and bits 7 to 0 (PM27 to PM20) of port mode register 2 (PM2).
Page 320: How To Read A/D Converter Characteristics Table
CHAPTER 13 A/D CONVERTER 13.5 How to Read A/D Converter Characteristics Table Here, special terms unique to the A/D converter are explained. (1) Resolution This is the minimum analog input voltage that can be identified. That is, the percentage of the analog input voltage per bit of digital output is called 1LSB (Least Significant Bit).
Page 321 CHAPTER 13 A/D CONVERTER (5) Full-scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value (Full-scale − 3/2LSB) when the digital output changes from 1..110 to 1..111. (6) Integral linearity error This shows the degree to which the conversion characteristics deviate from the ideal linear relationship.
Page 322: Cautions For A/D Converter
CHAPTER 13 A/D CONVERTER 13.6 Cautions for A/D Converter (1) Operating current in STOP mode The A/D converter stops operating in the STOP mode. At this time, the operating current can be reduced by clearing bit 7 (ADCS) and bit 0 (ADCE) of the A/D converter mode register (ADM) to 0. To restart from the standby status, clear bit 0 (ADIF) of interrupt request flag register 1L (IF1L) to 0 and start operation.
Page 323 CHAPTER 13 A/D CONVERTER Figure 13-20. Analog Input Pin Connection If there is a possibility that noise equal to or higher than AV equal to or lower than AV may enter, clamp with a diode with a small V value (0.3 V or lower). Reference voltage input...
Page 324 CHAPTER 13 A/D CONVERTER (8) Interrupt request flag (ADIF) The interrupt request flag (ADIF) is not cleared even if the analog input channel specification register (ADS) is changed. Therefore, if an analog input pin is changed during A/D conversion, the A/D conversion result and ADIF for the pre-change analog input may be set just before the ADS rewrite.
Page 325 CHAPTER 13 A/D CONVERTER (11) Internal equivalent circuit The equivalent circuit of the analog input block is shown below. Figure 13-22. Internal Equivalent Circuit of ANIn Pin ANIn Table 13-4. Resistance and Capacitance Values of Equivalent Circuit (Reference Values) 4.0 V ≤ AV ≤...
Page 326: Chapter 14 Serial Interface Uart0
CHAPTER 14 SERIAL INTERFACE UART0 14.1 Functions of Serial Interface UART0 Serial interface UART0 has the following two modes. (1) Operation stop mode This mode is used when serial communication is not executed and can enable a reduction in the power consumption.
Page 327: Configuration Of Serial Interface Uart0
CHAPTER 14 SERIAL INTERFACE UART0 14.2 Configuration of Serial Interface UART0 Serial interface UART0 includes the following hardware. Table 14-1. Configuration of Serial Interface UART0 Item Configuration Registers Receive buffer register 0 (RXB0) Receive shift register 0 (RXS0) Transmit shift register 0 (TXS0) Control registers Asynchronous serial interface operation mode register 0 (ASIM0) Asynchronous serial interface reception error status register 0 (ASIS0)
Page 328 Figure 14-1. Block Diagram of Serial Interface UART0 Filter SI10/P11 Receive shift register 0 (RXS0) Asynchronous serial Asynchronous serial INTSR0 Reception control Baud rate Receive buffer register 0 interface operation mode interface reception error (RXB0) generator register 0 (ASIM0) status register 0 (ASIS0) Reception unit Internal bus 8-bit timer/...
Page 329 CHAPTER 14 SERIAL INTERFACE UART0 (1) Receive buffer register 0 (RXB0) This 8-bit register stores parallel data converted by receive shift register 0 (RXS0). Each time 1 byte of data has been received, new receive data is transferred to this register from receive shift register 0 (RXS0).
Page 330: Registers Controlling Serial Interface Uart0
CHAPTER 14 SERIAL INTERFACE UART0 14.3 Registers Controlling Serial Interface UART0 Serial interface UART0 is controlled by the following five registers. • Asynchronous serial interface operation mode register 0 (ASIM0) • Asynchronous serial interface reception error status register 0 (ASIS0) •...
Page 331 CHAPTER 14 SERIAL INTERFACE UART0 Figure 14-2. Format of Asynchronous Serial Interface Operation Mode Register 0 (ASIM0) (2/2) PS01 PS00 Transmission operation Reception operation Does not output parity bit. Reception without parity Note Outputs 0 parity. Reception as 0 parity Outputs odd parity.
Page 332 CHAPTER 14 SERIAL INTERFACE UART0 (2) Asynchronous serial interface reception error status register 0 (ASIS0) This register indicates an error status on completion of reception by serial interface UART0. It includes three error flag bits (PE0, FE0, OVE0). This register is read-only by an 8-bit memory manipulation instruction. Reset signal generation sets this register to 00H if bit 7 (POWER0) and bit 5 (RXE0) of ASIM0 = 0.
Page 333 CHAPTER 14 SERIAL INTERFACE UART0 (3) Baud rate generator control register 0 (BRGC0) This register selects the base clock of serial interface UART0 and the division value of the 5-bit counter. BRGC0 can be set by an 8-bit memory manipulation instruction. Reset signal generation sets this register to 1FH.
Page 334 CHAPTER 14 SERIAL INTERFACE UART0 Cautions 1. Make sure that bit 6 (TXE0) and bit 5 (RXE0) of the ASIM0 register = 0 when rewriting the MDL04 to MDL00 bits. 2. The baud rate value is the output clock of the 5-bit counter divided by 2. Remarks 1.
Page 335: Operation Of Serial Interface Uart0
CHAPTER 14 SERIAL INTERFACE UART0 14.4 Operation of Serial Interface UART0 Serial interface UART0 has the following two modes. • Operation stop mode • Asynchronous serial interface (UART) mode 14.4.1 Operation stop mode In this mode, serial communication cannot be executed, thus reducing the power consumption. In addition, the pins can be used as ordinary port pins in this mode.
Page 336: Asynchronous Serial Interface (Uart) Mode
CHAPTER 14 SERIAL INTERFACE UART0 14.4.2 Asynchronous serial interface (UART) mode In this mode, 1-byte data is transmitted/received following a start bit, and a full-duplex operation can be performed. A dedicated UART baud rate generator is incorporated, so that communication can be executed at a wide range of baud rates.
Page 337 CHAPTER 14 SERIAL INTERFACE UART0 (2) Communication operation (a) Format and waveform example of normal transmit/receive data Figures 14-6 and 14-7 show the format and waveform example of the normal transmit/receive data. Figure 14-6. Format of Normal UART Transmit/Receive Data 1 data frame Start Parity...
Page 338 CHAPTER 14 SERIAL INTERFACE UART0 (b) Parity types and operation The parity bit is used to detect a bit error in communication data. Usually, the same type of parity bit is used on both the transmission and reception sides. With even parity and odd parity, a 1-bit (odd number) error can be detected.
Page 339 CHAPTER 14 SERIAL INTERFACE UART0 (c) Transmission If bit 7 (POWER0) of asynchronous serial interface operation mode register 0 (ASIM0) is set to 1 and bit 6 (TXE0) of ASIM0 is then set to 1, transmission is enabled. Transmission can be started by writing transmit data to transmit shift register 0 (TXS0).
Page 340 CHAPTER 14 SERIAL INTERFACE UART0 (d) Reception Reception is enabled and the R D0 pin input is sampled when bit 7 (POWER0) of asynchronous serial interface operation mode register 0 (ASIM0) is set to 1 and then bit 5 (RXE0) of ASIM0 is set to 1. The 5-bit counter of the baud rate generator starts counting when the falling edge of the R D0 pin input is detected.
Page 341 CHAPTER 14 SERIAL INTERFACE UART0 (e) Reception error Three types of errors may occur during reception: a parity error, framing error, or overrun error. If the error flag of asynchronous serial interface reception error status register 0 (ASIS0) is set as a result of data reception, a reception error interrupt (INTSR0) is generated.
Page 342: Dedicated Baud Rate Generator
CHAPTER 14 SERIAL INTERFACE UART0 14.4.3 Dedicated baud rate generator The dedicated baud rate generator consists of a source clock selector and a 5-bit programmable counter, and generates a serial clock for transmission/reception of UART0. Separate 5-bit counters are provided for transmission and reception. (1) Configuration of baud rate generator •...
Page 343 CHAPTER 14 SERIAL INTERFACE UART0 (2) Generation of serial clock A serial clock to be generated can be specified by using baud rate generator control register 0 (BRGC0). Select the clock to be input to the 5-bit counter by using bits 7 and 6 (TPS01 and TPS00) of BRGC0. Bits 4 to 0 (MDL04 to MDL00) of BRGC0 can be used to select the division value (f /8 to f /31) of the 5-bit...
Page 344 CHAPTER 14 SERIAL INTERFACE UART0 (3) Example of setting baud rate Table 14-5. Set Data of Baud Rate Generator Baud = 2.0 MHz = 5.0 MHz = 10.0 MHz = 20.0 MHz Rate TPS01, Calculated TPS01, Calculated TPS01, Calculated TPS01, Calculated [bps] TPS00...
Page 345 CHAPTER 14 SERIAL INTERFACE UART0 (4) Permissible baud rate range during reception The permissible error from the baud rate at the transmission destination during reception is shown below. Caution Make sure that the baud rate error during reception is within the permissible error range, by using the calculation expression shown below.
Page 346 CHAPTER 14 SERIAL INTERFACE UART0 k − 2 21k + 2 Minimum permissible data frame length: FLmin = 11 × FL − × FL = Therefore, the maximum receivable baud rate at the transmission destination is as follows. − BRmax = (FLmin/11) Brate 21k + 2 Similarly, the maximum permissible data frame length can be calculated as follows.
Page 347: Chapter 15 Serial Interface Uart6
CHAPTER 15 SERIAL INTERFACE UART6 15.1 Functions of Serial Interface UART6 Serial interface UART6 has the following two modes. (1) Operation stop mode This mode is used when serial communication is not executed and can enable a reduction in the power consumption.
Page 348 CHAPTER 15 SERIAL INTERFACE UART6 Remark LIN stands for Local Interconnect Network and is a low-speed (1 to 20 kbps) serial communication protocol intended to aid the cost reduction of an automotive network. LIN communication is single-master communication, and up to 15 slaves can be connected to one master.
Page 349 CHAPTER 15 SERIAL INTERFACE UART6 Figure 15-2. LIN Reception Operation Wakeup Sync Sync field Identifier Data field Data field Checksum signal frame break field field field LIN Bus 13-bit Data Data Data SBF reception reception reception reception reception reception <5> <2>...
Page 350 CHAPTER 15 SERIAL INTERFACE UART6 Figure 15-3. Port Configuration for LIN Reception Operation Selector P14/RxD6 RXD6 input Port mode (PM14) Output latch (P14) Selector Selector P120/INTP0/EXLVI INTP0 input Port mode Port input (PM120) switch control (ISC0) Output latch <ISC0> (P120) 0: Select INTP0 (P120) 1: Select RxD6 (P14) Selector...
Page 351: Configuration Of Serial Interface Uart6
CHAPTER 15 SERIAL INTERFACE UART6 15.2 Configuration of Serial Interface UART6 Serial interface UART6 includes the following hardware. Table 15-1. Configuration of Serial Interface UART6 Item Configuration Registers Receive buffer register 6 (RXB6) Receive shift register 6 (RXS6) Transmit buffer register 6 (TXB6) Transmit shift register 6 (TXS6) Control registers Asynchronous serial interface operation mode register 6 (ASIM6)
Page 352 Figure 15-4. Block Diagram of Serial Interface UART6 Internal bus Asynchronous serial interface Transmit buffer register 6 control register 6 (ASICL6) (TXB6) Transmit shift register 6 (TXS6)
Page 353 CHAPTER 15 SERIAL INTERFACE UART6 (1) Receive buffer register 6 (RXB6) This 8-bit register stores parallel data converted by receive shift register 6 (RXS6). Each time 1 byte of data has been received, new receive data is transferred to this register from RXS6. If the data length is set to 7 bits, data is transferred as follows.
Page 354: Registers Controlling Serial Interface Uart6
CHAPTER 15 SERIAL INTERFACE UART6 15.3 Registers Controlling Serial Interface UART6 Serial interface UART6 is controlled by the following nine registers. • Asynchronous serial interface operation mode register 6 (ASIM6) • Asynchronous serial interface reception error status register 6 (ASIS6) •...
Page 355 CHAPTER 15 SERIAL INTERFACE UART6 Figure 15-5. Format of Asynchronous Serial Interface Operation Mode Register 6 (ASIM6) (2/2) PS61 PS60 Transmission operation Reception operation Does not output parity bit. Reception without parity Note Outputs 0 parity. Reception as 0 parity Outputs odd parity.
Page 356 CHAPTER 15 SERIAL INTERFACE UART6 (2) Asynchronous serial interface reception error status register 6 (ASIS6) This register indicates an error status on completion of reception by serial interface UART6. It includes three error flag bits (PE6, FE6, OVE6). This register is read-only by an 8-bit memory manipulation instruction. Reset signal generation sets this register to 00H if bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 0.
Page 357 CHAPTER 15 SERIAL INTERFACE UART6 (3) Asynchronous serial interface transmission status register 6 (ASIF6) This register indicates the status of transmission by serial interface UART6. It includes two status flag bits (TXBF6 and TXSF6). Transmission can be continued without disruption even during an interrupt period, by writing the next data to the TXB6 register after data has been transferred from the TXB6 register to the TXS6 register.
Page 358 CHAPTER 15 SERIAL INTERFACE UART6 (4) Clock selection register 6 (CKSR6) This register selects the base clock of serial interface UART6. CKSR6 can be set by an 8-bit memory manipulation instruction. Reset signal generation sets this register to 00H. Remark CKSR6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = Figure 15-8.
Page 359 CHAPTER 15 SERIAL INTERFACE UART6 (5) Baud rate generator control register 6 (BRGC6) This register sets the division value of the 8-bit counter of serial interface UART6. BRGC6 can be set by an 8-bit memory manipulation instruction. Reset signal generation sets this register to FFH. Remark BRGC6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 1).
Page 360 CHAPTER 15 SERIAL INTERFACE UART6 (6) Asynchronous serial interface control register 6 (ASICL6) This register controls the serial communication operations of serial interface UART6. ASICL6 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 16H. Caution ASICL6 can be refreshed (the same value is written) by software during a communication operation (when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 1).
Page 361 CHAPTER 15 SERIAL INTERFACE UART6 Figure 15-10. Format of Asynchronous Serial Interface Control Register 6 (ASICL6) (2/2) SBL62 SBL61 SBL60 SBF transmission output width control SBF is output with 13-bit length. SBF is output with 14-bit length. SBF is output with 15-bit length. SBF is output with 16-bit length.
Page 362 CHAPTER 15 SERIAL INTERFACE UART6 (7) Input switch control register (ISC) The input switch control register (ISC) is used to receive a status signal transmitted from the master during LIN (Local Interconnect Network) reception. The signal input from the P14/R D6 pin is selected as the input source of INTP0 and TI000 when ISC0 and ISC1 are set to 1.
Page 363: Operation Of Serial Interface Uart6
CHAPTER 15 SERIAL INTERFACE UART6 15.4 Operation of Serial Interface UART6 Serial interface UART6 has the following two modes. • Operation stop mode • Asynchronous serial interface (UART) mode 15.4.1 Operation stop mode In this mode, serial communication cannot be executed; therefore, the power consumption can be reduced. In addition, the pins can be used as ordinary port pins in this mode.
Page 364: Asynchronous Serial Interface (Uart) Mode
CHAPTER 15 SERIAL INTERFACE UART6 15.4.2 Asynchronous serial interface (UART) mode In this mode, data of 1 byte is transmitted/received following a start bit, and a full-duplex operation can be performed. A dedicated UART baud rate generator is incorporated, so that communication can be executed at a wide range of baud rates.
Page 365 CHAPTER 15 SERIAL INTERFACE UART6 (2) Communication operation (a) Format and waveform example of normal transmit/receive data Figures 15-13 and 15-14 show the format and waveform example of the normal transmit/receive data. Figure 15-13. Format of Normal UART Transmit/Receive Data 1.
Page 366 CHAPTER 15 SERIAL INTERFACE UART6 Figure 15-14. Example of Normal UART Transmit/Receive Data Waveform 1. Data length: 8 bits, LSB first, Parity: Even parity, Stop bit: 1 bit, Communication data: 55H 1 data frame Start Parity Stop 2. Data length: 8 bits, MSB first, Parity: Even parity, Stop bit: 1 bit, Communication data: 55H 1 data frame Start Parity...
Page 367 CHAPTER 15 SERIAL INTERFACE UART6 (b) Parity types and operation The parity bit is used to detect a bit error in communication data. Usually, the same type of parity bit is used on both the transmission and reception sides. With even parity and odd parity, a 1-bit (odd number) error can be detected.
Page 368 CHAPTER 15 SERIAL INTERFACE UART6 (c) Normal transmission When bit 7 (POWER6) of asynchronous serial interface operation mode register 6 (ASIM6) is set to 1 and bit 6 (TXE6) of ASIM6 is then set to 1, transmission is enabled. Transmission can be started by writing transmit data to transmit buffer register 6 (TXB6).
Page 369 CHAPTER 15 SERIAL INTERFACE UART6 (d) Continuous transmission The next transmit data can be written to transmit buffer register 6 (TXB6) as soon as transmit shift register 6 (TXS6) has started its shift operation. Consequently, even while the INTST6 interrupt is being serviced after transmission of one data frame, data can be continuously transmitted and an efficient communication rate can be realized.
Page 370 CHAPTER 15 SERIAL INTERFACE UART6 Figure 15-16 shows an example of the continuous transmission processing flow. Figure 15-16. Example of Continuous Transmission Processing Flow Set registers. Write TXB6. Transfer executed necessary number of times? Read ASIF6 TXBF6 = 0? Write TXB6. Transmission completion interrupt occurs?
Page 371 CHAPTER 15 SERIAL INTERFACE UART6 Figure 15-17 shows the timing of starting continuous transmission, and Figure 15-18 shows the timing of ending continuous transmission. Figure 15-17. Timing of Starting Continuous Transmission Start Data (1) Parity Stop Start Data (2) Parity Stop Start INTST6...
Page 372 CHAPTER 15 SERIAL INTERFACE UART6 Figure 15-18. Timing of Ending Continuous Transmission Data (n − 1) Start Start Parity Data (n) Parity Stop Stop Stop INTST6 Data (n − 1) TXB6 Data (n) Data (n − 1) TXS6 Data (n) TXBF6 TXSF6 POWER6 or TXE6...
Page 373 CHAPTER 15 SERIAL INTERFACE UART6 (e) Normal reception Reception is enabled and the R D6 pin input is sampled when bit 7 (POWER6) of asynchronous serial interface operation mode register 6 (ASIM6) is set to 1 and then bit 5 (RXE6) of ASIM6 is set to 1. The 8-bit counter of the baud rate generator starts counting when the falling edge of the R D6 pin input is detected.
Page 374 CHAPTER 15 SERIAL INTERFACE UART6 (f) Reception error Three types of errors may occur during reception: a parity error, framing error, or overrun error. If the error flag of asynchronous serial interface reception error status register 6 (ASIS6) is set as a result of data reception, a reception error interrupt request (INTSR6/INTSRE6) is generated.
Page 375 CHAPTER 15 SERIAL INTERFACE UART6 (g) Noise filter of receive data The RXD6 signal is sampled with the base clock output by the prescaler block. If two sampled values are the same, the output of the match detector changes, and the data is sampled as input data.
Page 376 CHAPTER 15 SERIAL INTERFACE UART6 SBF reception When the device is incorporated in LIN, the SBF (Synchronous Break Field) reception control function is used for reception. For the reception operation of LIN, see Figure 15-2 LIN Reception Operation. Reception is enabled when bit 7 (POWER6) of asynchronous serial interface operation mode register 6 (ASIM6) is set to 1 and then bit 5 (RXE6) of ASIM6 is set to 1.
Page 377: Dedicated Baud Rate Generator
CHAPTER 15 SERIAL INTERFACE UART6 15.4.3 Dedicated baud rate generator The dedicated baud rate generator consists of a source clock selector and an 8-bit programmable counter, and generates a serial clock for transmission/reception of UART6. Separate 8-bit counters are provided for transmission and reception. (1) Configuration of baud rate generator •...
Page 378 CHAPTER 15 SERIAL INTERFACE UART6 Figure 15-24. Configuration of Baud Rate Generator POWER6 Baud rate generator POWER6, TXE6 (or RXE6) Selector 8-bit counter XCLK6 Match detector Baud rate 8-bit timer/ event counter 50 output CKSR6: TPS63 to TPS60 BRGC6: MDL67 to MDL60 Remark POWER6: Bit 7 of asynchronous serial interface operation mode register 6 (ASIM6) TXE6: Bit 6 of ASIM6...
Page 379 CHAPTER 15 SERIAL INTERFACE UART6 (a) Baud rate The baud rate can be calculated by the following expression. XCLK6 • Baud rate = [bps] 2 × k : Frequency of base clock selected by TPS63 to TPS60 bits of CKSR6 register XCLK6 Value set by MDL67 to MDL60 bits of BRGC6 register (k = 8, 9, 10, ..., 255) (b) Error of baud rate...
Page 380 CHAPTER 15 SERIAL INTERFACE UART6 (3) Example of setting baud rate Table 15-5. Set Data of Baud Rate Generator Baud = 2.0 MHz = 5.0 MHz = 10.0 MHz = 20.0 MHz Rate TPS63- Calculated TPS63- Calculated TPS63- Calculated TPS63- Calculated [bps] TPS60...
Page 381 CHAPTER 15 SERIAL INTERFACE UART6 (4) Permissible baud rate range during reception The permissible error from the baud rate at the transmission destination during reception is shown below. Caution Make sure that the baud rate error during reception is within the permissible error range, by using the calculation expression shown below.
Page 382 CHAPTER 15 SERIAL INTERFACE UART6 k − 2 21k + 2 Minimum permissible data frame length: FLmin = 11 × FL − × FL = Therefore, the maximum receivable baud rate at the transmission destination is as follows. − BRmax = (FLmin/11) Brate 21k + 2 Similarly, the maximum permissible data frame length can be calculated as follows.
Page 383 CHAPTER 15 SERIAL INTERFACE UART6 (5) Data frame length during continuous transmission When data is continuously transmitted, the data frame length from a stop bit to the next start bit is extended by two clocks of base clock from the normal value. However, the result of communication is not affected because the timing is initialized on the reception side when the start bit is detected.
Page 384: Chapter 16 Serial Interfaces Csi10 And Csi11
CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 µ µ PD78F0531, 78F0532, and 78F0533 incorporate serial interface CSI10, and the PD78F0534, 78F0535, 78F0536, 78F0537, and 78F0537D incorporate serial interfaces CSI10 and CSI11. 16.1 Functions of Serial Interfaces CSI10 and CSI11 Serial interfaces CSI10 and CSI11 have the following two modes. •...
Page 385: Configuration Of Serial Interfaces Csi10 And Csi11
CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 16.2 Configuration of Serial Interfaces CSI10 and CSI11 Serial interfaces CSI10 and CSI11 include the following hardware. Table 16-1. Configuration of Serial Interfaces CSI10 and CSI11 Item Configuration Controller Transmit controller Clock start/stop controller & clock phase controller Registers Transmit buffer register 1n (SOTB1n) Serial I/O shift register 1n (SIO1n)
Page 386 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 Figure 16-2. Block Diagram of Serial Interface CSI11 µ (Available only in the PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D) Internal bus Serial I/O shift Transmit buffer Output SI11/P03 register 11 (SIO11) register 11 (SOTB11) selector SO11/P02 Output latch...
Page 387 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 (2) Serial I/O shift register 1n (SIO1n) This is an 8-bit register that converts data from parallel data into serial data and vice versa. This register can be read by an 8-bit memory manipulation instruction. Reception is started by reading data from SIO1n if bit 6 (TRMD1n) of serial operation mode register 1n (CSIM1n) is 0.
Page 388: Registers Controlling Serial Interfaces Csi10 And Csi11
CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 16.3 Registers Controlling Serial Interfaces CSI10 and CSI11 Serial interfaces CSI10 and CSI11 are controlled by the following four registers. • Serial operation mode register 1n (CSIM1n) • Serial clock selection register 1n (CSIC1n) •...
Page 389 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 Figure 16-4. Format of Serial Operation Mode Register 11 (CSIM11) Note 1 Address: FF88H After reset: 00H R/W Symbol <7> CSIM11 CSIE11 TRMD11 SSE11 DIR11 CSOT11 CSIE11 Operation control in 3-wire serial I/O mode Note 2 Note 3 Disables operation...
Page 390 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 (2) Serial clock selection register 1n (CSIC1n) This register specifies the timing of the data transmission/reception and sets the serial clock. CSIC1n can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 00H.
Page 391 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 Figure 16-6. Format of Serial Clock Selection Register 11 (CSIC11) Address: FF89H After reset: 00H R/W Symbol CSIC11 CKP11 DAP11 CKS112 CKS111 CKS110 CKP11 DAP11 Specification of data transmission/reception timing Type SCK11 SO11 D7 D6 D5 D4 D3 D2 D1 D0 SI11 input timing SCK11...
Page 392 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 (3) Port mode registers 0 and 1 (PM0, PM1) These registers set port 0 and 1 input/output in 1-bit units. Note When using P10/SCK10 and P04/SCK11 as the clock output pins of the serial interface, clear PM10 and PM04 to 0, and set the output latches of P10 and P04 to 1.
Page 393: Operation Of Serial Interfaces Csi10 And Csi11
CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 16.4 Operation of Serial Interfaces CSI10 and CSI11 Serial interfaces CSI10 and CSI11 can be used in the following two modes. • Operation stop mode • 3-wire serial I/O mode 16.4.1 Operation stop mode Serial communication is not executed in this mode.
Page 394: 3-Wire Serial I/O Mode
CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 16.4.2 3-wire serial I/O mode The 3-wire serial I/O mode is used for connecting peripheral ICs and display controllers with a clocked serial interface. In this mode, communication is executed by using three lines: the serial clock (SCK1n), serial output (SO1n), and serial input (SI1n) lines.
Page 395 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 The relationship between the register settings and pins is shown below. Table 16-2. Relationship Between Register Settings and Pins (1/2) (a) Serial interface CSI10 CSIE10 TRMD10 PM11 PM12 PM10 CSI10 Pin Function Operation SI10/R SO10/P12 SCK10/...
Page 396 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 Table 16-2. Relationship Between Register Settings and Pins (2/2) µ (b) Serial interface CSI11 (Available only in the PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D) CSIE11 TRMD11 SSE11 PM03 P03 PM02 P02 PM04 P04 PM05 P05 CSI11 Pin Function Operation...
Page 397 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 (2) Communication operation In the 3-wire serial I/O mode, data is transmitted or received in 8-bit units. Each bit of the data is transmitted or received in synchronization with the serial clock. Data can be transmitted or received if bit 6 (TRMD1n) of serial operation mode register 1n (CSIM1n) is 1. Transmission/reception is started when a value is written to transmit buffer register 1n (SOTB1n).
Page 398 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 Figure 16-9. Timing in 3-Wire Serial I/O Mode (1/2) Note (a) Transmission/reception timing (Type 1: TRMD1n = 1, DIR1n = 0, CKP1n = 0, DAP1n = 0, SSE11 = 1 Note SSI11 SCK1n Read/write trigger SOTB1n 55H (communication data)
Page 399 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 Figure 16-9. Timing in 3-Wire Serial I/O Mode (2/2) Note (b) Transmission/reception timing (Type 2: TRMD1n = 1, DIR1n = 0, CKP1n = 0, DAP1n = 1, SSE11 = 1 Note SSI11 SCK1n Read/write trigger SOTB1n 55H (communication data)
Page 400 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 Figure 16-10. Timing of Clock/Data Phase (a) Type 1: CKP1n = 0, DAP1n = 0, DIR1n = 0 SCK1n SI1n capture SO1n Writing to SOTB1n or reading from SIO1n CSIIF1n CSOT1n (b) Type 2: CKP1n = 0, DAP1n = 1, DIR1n = 0 SCK1n SI1n capture SO1n...
Page 401 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 (3) Timing of output to SO1n pin (first bit) When communication is started, the value of transmit buffer register 1n (SOTB1n) is output from the SO1n pin. The output operation of the first bit at this time is described below. Figure 16-11.
Page 402 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 Figure 16-11. Output Operation of First Bit (2/2) (c) Type 2: CKP1n = 0, DAP1n = 1 SCK1n Writing to SOTB1n or reading from SIO1n SOTB1n SIO1n Output latch SO1n First bit 2nd bit 3rd bit (d) Type 4: CKP1n = 1, DAP1n = 1 SCK1n...
Page 403 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 (4) Output value of SO1n pin (last bit) After communication has been completed, the SO1n pin holds the output value of the last bit. Figure 16-12. Output Value of SO1n Pin (Last Bit) (1/2) (a) Type 1: CKP1n = 0, DAP1n = 0 SCK1n ( ←...
Page 404 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 Figure 16-12. Output Value of SO1n Pin (Last Bit) (2/2) (c) Type 2: CKP1n = 0, DAP1n = 1 SCK1n Writing to SOTB1n or ( ← Next request is issued.) reading from SIO1n SOTB1n SIO1n Output latch...
Page 405 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 (5) SO1n output (see (a) in Figures 16-1 and 16-2) The status of the SO1n output is as follows if bit 7 (CSIE1n) of serial operation mode register 1n (CSIM1n) is cleared to 0. Table 16-3.
Page 406: Chapter 17 Serial Interface Iic0
CHAPTER 17 SERIAL INTERFACE IIC0 17.1 Functions of Serial Interface IIC0 Serial interface IIC0 has the following two modes. (1) Operation stop mode This mode is used when serial transfers are not performed. It can therefore be used to reduce power consumption.
Page 407 CHAPTER 17 SERIAL INTERFACE IIC0 Figure 17-1. Block Diagram of Serial Interface IIC0 Internal bus IIC status register 0 (IICS0) MSTS0 ALD0 EXC0 COI0 TRC0 ACKD0 STD0 SPD0 IIC control register 0 (IICC0) IICE0 LREL0 WREL0 SPIE0 WTIM0 ACKE0 STT0 SPT0 Slave address Start Clear...
Page 408 CHAPTER 17 SERIAL INTERFACE IIC0 Figure 17-2 shows a serial bus configuration example. Figure 17-2. Serial Bus Configuration Example Using I C Bus Serial data bus Master CPU2 Master CPU1 SDA0 SDA0 Slave CPU1 Slave CPU2 Serial clock SCL0 SCL0 Address 0 Address 1 SDA0...
Page 409: Configuration Of Serial Interface Iic0
CHAPTER 17 SERIAL INTERFACE IIC0 17.2 Configuration of Serial Interface IIC0 Serial interface IIC0 includes the following hardware. Table 17-1. Configuration of Serial Interface IIC0 Item Configuration Registers IIC shift register 0 (IIC0) Slave address register 0 (SVA0) Control registers IIC control register 0 (IICC0) IIC status register 0 (IICS0) IIC flag register 0 (IICF0)
Page 410 CHAPTER 17 SERIAL INTERFACE IIC0 (3) SO latch The SO latch is used to retain the SDA0 pin’s output level. (4) Wake-up controller This circuit generates an interrupt request (INTIIC0) when the address received by this register matches the address value set to slave address register 0 (SVA0) or when an extension code is received. (5) Prescaler This selects the sampling clock to be used.
Page 411 CHAPTER 17 SERIAL INTERFACE IIC0 (14) Bus status detector This circuit detects whether or not the bus is released by detecting start conditions and stop conditions. However, as the bus status cannot be detected immediately following operation, the initial status is set by the STCEN bit.
Page 412: Registers To Control Serial Interface Iic0
CHAPTER 17 SERIAL INTERFACE IIC0 17.3 Registers to Control Serial Interface IIC0 Serial interface IIC0 is controlled by the following seven registers. • IIC control register 0 (IICC0) • IIC flag register 0 (IICF0) • IIC status register 0 (IICS0) •...
Page 413 CHAPTER 17 SERIAL INTERFACE IIC0 Figure 17-5. Format of IIC Control Register 0 (IICC0) (1/4) Address: FFA6H After reset: 00H Symbol <7> <6> <5> <4> <3> <2> <1> <0> IICC0 IICE0 LREL0 WREL0 SPIE0 WTIM0 ACKE0 STT0 SPT0 IICE0 C operation enable Note 1 Stop operation.
Page 414 CHAPTER 17 SERIAL INTERFACE IIC0 Figure 17-5. Format of IIC Control Register 0 (IICC0) (2/4) Note 1 SPIE0 Enable/disable generation of interrupt request when stop condition is detected Disable Enable Condition for clearing (SPIE0 = 0) Condition for setting (SPIE0 = 1) •...
Page 415 CHAPTER 17 SERIAL INTERFACE IIC0 Figure 17-5. Format of IIC Control Register 0 (IICC0) (3/4) Note STT0 Start condition trigger Do not generate a start condition. When bus is released (in STOP mode): Generate a start condition (for starting as master). When the SCL0 line is high level, the SDA0 line is changed from high level to low level and then the start condition is generated.
Page 416 CHAPTER 17 SERIAL INTERFACE IIC0 Figure 17-5. Format of IIC Control Register 0 (IICC0) (4/4) SPT0 Stop condition trigger Stop condition is not generated. Stop condition is generated (termination of master device’s transfer). After the SDA0 line goes to low level, either set the SCL0 line to high level or wait until it goes to high level. Next, after the rated amount of time has elapsed, the SDA0 line changes from low level to high level and a stop condition is generated.
Page 417 CHAPTER 17 SERIAL INTERFACE IIC0 (2) IIC status register 0 (IICS0) This register indicates the status of I IICS0 is read by a 1-bit or 8-bit memory manipulation instruction only when STT0 = 1 and during the wait period. Reset signal generation sets IICS0 to 00H. Caution If data is read from IICS0, a wait cycle is generated.
Page 418 CHAPTER 17 SERIAL INTERFACE IIC0 Figure 17-6. Format of IIC Status Register 0 (IICS0) (2/3) COI0 Detection of matching addresses Addresses do not match. Addresses match. Condition for clearing (COI0 = 0) Condition for setting (COI0 = 1) • When a start condition is detected •...
Page 419 CHAPTER 17 SERIAL INTERFACE IIC0 Figure 17-6. Format of IIC Status Register 0 (IICS0) (3/3) ACKD0 Detection of acknowledge (ACK) Acknowledge was not detected. Acknowledge was detected. Condition for clearing (ACKD0 = 0) Condition for setting (ACKD0 = 1) • When a stop condition is detected •...
Page 420 CHAPTER 17 SERIAL INTERFACE IIC0 Figure 17-7. Format of IIC Flag Register 0 (IICF0) Note Address: FFABH After reset: 00H <7> <6> <1> <0> Symbol IICF0 STCF IICBSY STCEN IICRSV STCF STT0 clear flag Generate start condition Start condition generation unsuccessful: clear STT0 flag Condition for clearing (STCF = 0) Condition for setting (STCF = 1) •...
Page 421 CHAPTER 17 SERIAL INTERFACE IIC0 (4) IIC clock selection register 0 (IICCL0) This register is used to set the transfer clock for the I C bus. IICCL0 is set by a 1-bit or 8-bit memory manipulation instruction. However, the CLD0 and DAD0 bits are read- only.
Page 422 CHAPTER 17 SERIAL INTERFACE IIC0 (5) IIC function expansion register 0 (IICX0) This register sets the function expansion of I IICX0 is set by a 1-bit or 8-bit memory manipulation instruction. The CLX0 bit is set in combination with bits 3, 1, and 0 (SMC0, CL01, and CL00) of IIC clock selection register 0 (IICCL0) (see 17.3 (6) I C transfer clock setting method).
Page 423 CHAPTER 17 SERIAL INTERFACE IIC0 For example, the I C transfer clock frequency (f ) when f /2 = 4.19 MHz, m = 86, t = 200 ns, and t 50 ns is calculated using following expression. = 1/(88 × 238.7 ns + 200 ns + 50 ns) ≅ 48.1 kHz m ×...
Page 424 CHAPTER 17 SERIAL INTERFACE IIC0 (7) Port mode register 6 (PM6) This register sets the input/output of port 6 in 1-bit units. When using the P60/SCL0 pin as clock I/O and the P61/SDA0 pin as serial data I/O, clear PM60 and PM61, and the output latches of P60 and P61 to 0.
Page 425: I C Bus Mode Functions
CHAPTER 17 SERIAL INTERFACE IIC0 17.4 I C Bus Mode Functions 17.4.1 Pin configuration The serial clock pin (SCL0) and serial data bus pin (SDA0) are configured as follows. (1) SCL0 ..This pin is used for serial clock input and output. This pin is an N-ch open-drain output for both master and slave devices.
Page 426: I C Bus Definitions And Control Methods
CHAPTER 17 SERIAL INTERFACE IIC0 17.5 I C Bus Definitions and Control Methods The following section describes the I C bus’s serial data communication format and the signals used by the I C bus. Figure 17-12 shows the transfer timing for the “start condition”, “address”, “data”, and “stop condition” output via the C bus’s serial data bus.
Page 427: Addresses
CHAPTER 17 SERIAL INTERFACE IIC0 17.5.2 Addresses The address is defined by the 7 bits of data that follow the start condition. An address is a 7-bit data segment that is output in order to select one of the slave devices that are connected to the master device via the bus lines.
Page 428: Acknowledge (Ack)
CHAPTER 17 SERIAL INTERFACE IIC0 17.5.4 Acknowledge (ACK) ACK is used to check the status of serial data at the transmission and reception sides. The reception side returns ACK each time it has received 8-bit data. The transmission side usually receives ACK after transmitting 8-bit data. When ACK is returned from the reception side, it is assumed that reception has been correctly performed and processing is continued.
Page 429: Stop Condition
CHAPTER 17 SERIAL INTERFACE IIC0 17.5.5 Stop condition When the SCL0 pin is at high level, changing the SDA0 pin from low level to high level generates a stop condition. A stop condition is a signal that the master device generates to the slave device when serial transfer has been completed.
Page 430: Wait
CHAPTER 17 SERIAL INTERFACE IIC0 17.5.6 Wait The wait is used to notify the communication partner that a device (master or slave) is preparing to transmit or receive data (i.e., is in a wait state). Setting the SCL0 pin to low level notifies the communication partner of the wait state. When wait state has been canceled for both the master and slave devices, the next data transfer can begin.
Page 431 CHAPTER 17 SERIAL INTERFACE IIC0 Figure 17-18. Wait (2/2) (2) When master and slave devices both have a nine-clock wait (master transmits, slave receives, and ACKE0 = 1) Master Master and slave both wait after output of ninth clock IIC0 data write (cancel wait) IIC0 SCL0 Slave...
Page 432: Canceling Wait
CHAPTER 17 SERIAL INTERFACE IIC0 17.5.7 Canceling wait The I C usually cancels a wait state by the following processing. • Writing data to IIC shift register 0 (IIC0) • Setting bit 5 (WREL0) of IIC control register 0 (IICC0) (canceling wait) •...
Page 433: Address Match Detection Method
CHAPTER 17 SERIAL INTERFACE IIC0 (1) During address transmission/reception • Slave device operation: Interrupt and wait timing are determined depending on the conditions described in Notes 1 and 2 above, regardless of the WTIM0 bit. • Master device operation: Interrupt and wait timing occur at the falling edge of the ninth clock regardless of the WTIM0 bit.
Page 434: Extension Code
CHAPTER 17 SERIAL INTERFACE IIC0 17.5.11 Extension code (1) When the higher 4 bits of the receive address are either “0000” or “1111”, the extension code reception flag (EXC0) is set to 1 for extension code reception and an interrupt request (INTIIC0) is issued at the falling edge of the eighth clock.
Page 435: Arbitration
CHAPTER 17 SERIAL INTERFACE IIC0 17.5.12 Arbitration When several master devices simultaneously generate a start condition (when STT0 is set to 1 before STD0 is set to 1), communication among the master devices is performed as the number of clocks are adjusted until the data differs.
Page 436: Wakeup Function
CHAPTER 17 SERIAL INTERFACE IIC0 Table 17-5. Status During Arbitration and Interrupt Request Generation Timing Status During Arbitration Interrupt Request Generation Timing Note 1 During address transmission At falling edge of eighth or ninth clock following byte transfer Read/write data after address transmission During extension code transmission Read/write data after extension code transmission During data transmission...
Page 437: Communication Reservation
CHAPTER 17 SERIAL INTERFACE IIC0 17.5.14 Communication reservation (1) When communication reservation function is enabled (bit 0 (IICRSV) of IIC flag register 0 (IICF0) = 0) To start master device communications when not currently using a bus, a communication reservation can be made to enable transmission of a start condition when the bus is released.
Page 438 CHAPTER 17 SERIAL INTERFACE IIC0 Figure 17-20. Communication Reservation Timing Write to Program processing STT0 = 1 IIC0 Communi- Set SPD0 cation Hardware processing STD0 reservation INTIIC0 SCL0 SDA0 Generate by master device with bus mastership Remark IIC0: IIC shift register 0 STT0: Bit 1 of IIC control register 0 (IICC0) STD0: Bit 1 of IIC status register 0 (IICS0)
Page 439 CHAPTER 17 SERIAL INTERFACE IIC0 Figure 17-22. Communication Reservation Protocol SET1 STT0 Sets STT0 flag (communication reservation) Defines that communication reservation is in effect Define communication (defines and sets user flag to any part of RAM) reservation Secures wait period set by software (see Table 18-6). Wait Note (Communication reservation)
Page 440: Other Cautions
CHAPTER 17 SERIAL INTERFACE IIC0 Table 17-7. Wait Periods CL01 CL00 Wait Period 6 clocks 6 clocks 12 clocks 3 clocks 17.5.15 Other cautions (1) When STCEN (bit 1 of IIC flag register 0 (IICF0)) = 0 Immediately after I C operation is enabled (IICE0 = 1), the bus communication status (IICBSY (bit 6 of IICF0) = 1) is recognized regardless of the actual bus status.
Page 441 CHAPTER 17 SERIAL INTERFACE IIC0 (5) Setting STT0 and SPT0 (bits 1 and 0 of IICC0) again after they are set and before they are cleared to 0 is prohibited. (6) When transmission is reserved, set SPIE0 (bit 4 of IICL0) to 1 so that an interrupt request is generated when the stop condition is detected.
Page 442: Communication Operations
CHAPTER 17 SERIAL INTERFACE IIC0 17.5.16 Communication operations (1) Master operation (single-master system) Figure 17-23. Master Operation Flowchart (Single-Master System) START Note Initializing I C bus Setting port Sets each pin in the I C mode (see 17.3 (7) Port mode register 6 (PM6)). IICX0 ←...
Page 443 CHAPTER 17 SERIAL INTERFACE IIC0 (2) Master operation (multi-master system) Figure 17-24. Master Operation Flowchart (Multi-Master System) (1/3) START Setting port Sets each pin in the I C mode (see 17.3 (7) Port mode register 6 (PM6)). IICX0 ← 0XH Selects a transfer clock.
Page 444 CHAPTER 17 SERIAL INTERFACE IIC0 Figure 17-24. Master Operation Flowchart (Multi-Master System) (2/3) Enables reserving communication. Prepares for starting communication STT0 = 1 (generates a start condition). Secure wait time by software Wait (see Table 17-6). MSTS0 = 1? INTIIC0 interrupt occurs? Waits for bus release (communication being reserved).
Page 445 CHAPTER 17 SERIAL INTERFACE IIC0 Figure 17-24. Master Operation Flowchart (Multi-Master System) (3/3) Starts communication Writing IIC0 (specifies an address and transfer direction). INTIIC0 interrupt occurs? Waits for detection of ACK. MSTS0 = 1? ACKD0 = 1? TRC0 = 1? ACKE0 = 1 WTIM0 = 0 WTIM0 = 1...
Page 446 CHAPTER 17 SERIAL INTERFACE IIC0 (3) Slave operation The processing procedure of the slave operation is as follows. Basically, the slave operation is event-driven. Therefore, processing by the INTIIC0 interrupt (processing that must substantially change the operation status such as detection of a stop condition during communication) is necessary.
Page 447 CHAPTER 17 SERIAL INTERFACE IIC0 The main processing of the slave operation is explained next. Start serial interface IIC0 and wait until communication is enabled. When communication is enabled, execute communication by using the communication mode flag and ready flag (processing of the stop condition and start condition is performed by an interrupt.
Page 448 CHAPTER 17 SERIAL INTERFACE IIC0 An example of the processing procedure of the slave with the INTIIC0 interrupt is explained below (processing is performed assuming that no extension code is used). The INTIIC0 interrupt checks the status, and the following operations are performed. <1>...
Page 449: Timing Of I 2 C Interrupt Request (Intiic0) Occurrence
CHAPTER 17 SERIAL INTERFACE IIC0 17.5.17 Timing of I C interrupt request (INTIIC0) occurrence The timing of transmitting or receiving data and generation of interrupt request signal INTIIC0, and the value of the IICS0 register when the INTIIC0 signal is generated are shown below. Remark Start condition AD6 to AD0: Address...
Page 450 CHAPTER 17 SERIAL INTERFACE IIC0 (1) Master device operation (a) Start ~ Address ~ Data ~ Data ~ Stop (transmission/reception) (i) When WTIM0 = 0 SPT0 = 1 ↓ AD6 to AD0 R/W ACK D7 to D0 D7 to D0 1: IICS0 = 1000×110B 2: IICS0 = 1000×000B Note...
Page 451 CHAPTER 17 SERIAL INTERFACE IIC0 (b) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (restart) (i) When WTIM0 = 0 STT0 = 1 SPT0 = 1 ↓ ↓ AD6 to AD0 R/W ACK D7 to D0 AD6 to AD0 D7 to D0 1: IICS0 = 1000×110B...
Page 452 CHAPTER 17 SERIAL INTERFACE IIC0 (c) Start ~ Code ~ Data ~ Data ~ Stop (extension code transmission) (i) When WTIM0 = 0 SPT0 = 1 ↓ AD6 to AD0 R/W ACK D7 to D0 D7 to D0 1: IICS0 = 1010×110B 2: IICS0 = 1010×000B Note 3: IICS0 = 1010×000B (Sets WTIM0 to 1)
Page 453 CHAPTER 17 SERIAL INTERFACE IIC0 (2) Slave device operation (slave address data reception) (a) Start ~ Address ~ Data ~ Data ~ Stop (i) When WTIM0 = 0 AD6 to AD0 R/W ACK D7 to D0 D7 to D0 1: IICS0 = 0001×110B 2: IICS0 = 0001×000B 3: IICS0 = 0001×000B 4: IICS0 = 00000001B...
Page 454 CHAPTER 17 SERIAL INTERFACE IIC0 (b) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (i) When WTIM0 = 0 (after restart, matches with SVA0) AD6 to AD0 R/W ACK D7 to D0 AD6 to AD0 D7 to D0 1: IICS0 = 0001×110B 2: IICS0 = 0001×000B...
Page 455 CHAPTER 17 SERIAL INTERFACE IIC0 (c) Start ~ Address ~ Data ~ Start ~ Code ~ Data ~ Stop (i) When WTIM0 = 0 (after restart, does not match address (= extension code)) AD6 to AD0 R/W ACK D7 to D0 AD6 to AD0 D7 to D0 1: IICS0 = 0001×110B...
Page 456 CHAPTER 17 SERIAL INTERFACE IIC0 (d) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (i) When WTIM0 = 0 (after restart, does not match address (= not extension code)) AD6 to AD0 R/W ACK D7 to D0 AD6 to AD0 D7 to D0 1: IICS0 = 0001×110B...
Page 457 CHAPTER 17 SERIAL INTERFACE IIC0 (3) Slave device operation (when receiving extension code) The device is always participating in communication when it receives an extension code. (a) Start ~ Code ~ Data ~ Data ~ Stop (i) When WTIM0 = 0 AD6 to AD0 R/W ACK D7 to D0 D7 to D0...
Page 458 CHAPTER 17 SERIAL INTERFACE IIC0 (b) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop (i) When WTIM0 = 0 (after restart, matches SVA0) AD6 to AD0 R/W ACK D7 to D0 AD6 to AD0 D7 to D0 1: IICS0 = 0010×010B 2: IICS0 = 0010×000B 3: IICS0 = 0001×110B...
Page 459 CHAPTER 17 SERIAL INTERFACE IIC0 (c) Start ~ Code ~ Data ~ Start ~ Code ~ Data ~ Stop (i) When WTIM0 = 0 (after restart, extension code reception) AD6 to AD0 R/W ACK D7 to D0 AD6 to AD0 D7 to D0 1: IICS0 = 0010×010B 2: IICS0 = 0010×000B...
Page 460 CHAPTER 17 SERIAL INTERFACE IIC0 (d) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop (i) When WTIM0 = 0 (after restart, does not match address (= not extension code)) AD6 to AD0 R/W ACK D7 to D0 AD6 to AD0 D7 to D0 1: IICS0 = 00100010B...
Page 461 CHAPTER 17 SERIAL INTERFACE IIC0 (4) Operation without communication (a) Start ~ Code ~ Data ~ Data ~ Stop AD6 to AD0 R/W ACK D7 to D0 D7 to D0 1: IICS0 = 00000001B Remark : Generated only when SPIE0 = 1 (5) Arbitration loss operation (operation as slave after arbitration loss) When the device is used as a master in a multi-master system, read the MSTS0 bit each time interrupt request signal INTIIC0 has occurred to check the arbitration result.
Page 462 CHAPTER 17 SERIAL INTERFACE IIC0 (ii) When WTIM0 = 1 AD6 to AD0 R/W ACK D7 to D0 D7 to D0 1: IICS0 = 0101×110B 2: IICS0 = 0001×100B 3: IICS0 = 0001××00B 4: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 ×: Don’t care...
Page 463 CHAPTER 17 SERIAL INTERFACE IIC0 (ii) When WTIM0 = 1 AD6 to AD0 R/W ACK D7 to D0 D7 to D0 1: IICS0 = 0110×010B 2: IICS0 = 0010×110B 3: IICS0 = 0010×100B 4: IICS0 = 0010××00B 5: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1...
Page 464 CHAPTER 17 SERIAL INTERFACE IIC0 (b) When arbitration loss occurs during transmission of extension code AD6 to AD0 R/W ACK D7 to D0 D7 to D0 1: IICS0 = 0110×010B Sets LREL0 = 1 by software 2: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1...
Page 465 CHAPTER 17 SERIAL INTERFACE IIC0 (ii) When WTIM0 = 1 AD6 to AD0 R/W ACK D7 to D0 D7 to D0 1: IICS0 = 10001110B 2: IICS0 = 01000100B 3: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 (d) When loss occurs due to restart condition during data transfer (i) Not extension code (Example: unmatches with SVA0) AD6 to AD0 R/W ACK...
Page 466 CHAPTER 17 SERIAL INTERFACE IIC0 (ii) Extension code AD6 to AD0 R/W ACK D7 to Dn AD6 to AD0 D7 to D0 1: IICS0 = 1000×110B 2: IICS0 = 01100010B Sets LREL0 = 1 by software 3: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1...
Page 467 CHAPTER 17 SERIAL INTERFACE IIC0 (f) When arbitration loss occurs due to low-level data when attempting to generate a restart condition (i) When WTIM0 = 0 STT0 = 1 ↓ AD6 to AD0 R/W ACK D7 to D0 D7 to D0 D7 to D0 1: IICS0 = 1000×110B 2: IICS0 = 1000×000B (Sets WTIM0 to 1)
Page 468 CHAPTER 17 SERIAL INTERFACE IIC0 (g) When arbitration loss occurs due to a stop condition when attempting to generate a restart condition (i) When WTIM0 = 0 STT0 = 1 ↓ AD6 to AD0 R/W ACK D7 to D0 1: IICS0 = 1000×110B 2: IICS0 = 1000×000B (Sets WTIM0 to 1) 3: IICS0 = 1000××00B (Sets STT0 to 1) 4: IICS0 = 01000001B...
Page 469 CHAPTER 17 SERIAL INTERFACE IIC0 (h) When arbitration loss occurs due to low-level data when attempting to generate a stop condition (i) When WTIM0 = 0 SPT0 = 1 ↓ AD6 to AD0 R/W ACK D7 to D0 D7 to D0 D7 to D0 1: IICS0 = 1000×110B 2: IICS0 = 1000×000B (Sets WTIM0 to 1)
Page 470: Timing Charts
CHAPTER 17 SERIAL INTERFACE IIC0 17.6 Timing Charts When using the I C bus mode, the master device outputs an address via the serial bus to select one of several slave devices as its communication partner. After outputting the slave address, the master device transmits the TRC0 bit (bit 3 of IIC status register 0 (IICS0)), which specifies the data transfer direction, and then starts serial communication with the slave device.
Page 471 CHAPTER 17 SERIAL INTERFACE IIC0 Figure 17-27. Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (1/3) (1) Start condition ~ address Processing by master device ← ← IIC0 address IIC0 data IIC0 ACKD0 STD0 SPD0...
Page 472 CHAPTER 17 SERIAL INTERFACE IIC0 Figure 17-27. Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (2/3) (2) Data Processing by master device ← ← IIC0 data IIC0 data IIC0 ACKD0 STD0 SPD0 WTIM0 ACKE0 MSTS0...
Page 473 CHAPTER 17 SERIAL INTERFACE IIC0 Figure 17-27. Example of Master to Slave Communication (When 9-Clock Wait Is Selected for Both Master and Slave) (3/3) (3) Stop condition Processing by master device ← ← IIC0 data IIC0 address IIC0 ACKD0 STD0 SPD0 WTIM0 ACKE0...
Page 474 CHAPTER 17 SERIAL INTERFACE IIC0 Figure 17-28. Example of Slave to Master Communication (When 8-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (1/3) (1) Start condition ~ address Processing by master device ← ← IIC0 IIC0 address IIC0 FFH Note...
Page 475 CHAPTER 17 SERIAL INTERFACE IIC0 Figure 17-28. Example of Slave to Master Communication (When 8-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (2/3) (2) Data Processing by master device IIC0 ← FFH Note IIC0 ← FFH Note IIC0 ACKD0 STD0...
Page 476 CHAPTER 17 SERIAL INTERFACE IIC0 Figure 17-28. Example of Slave to Master Communication (When 8-Clock and 9-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (3/3) (3) Stop condition Processing by master device ← IIC0 address ← FFH IIC0 IIC0 Note...
Page 477: Chapter 18 Multiplier/Divider Pd78F0534, 78F0535, 78F0536, 78F0537, And 78F0537D Only)
CHAPTER 18 MULTIPLIER/DIVIDER µ PD78F0534, 78F0535, 78F0536, 78F0537, AND 78F0537D ONLY) µ Only for the PD78F0534, 78F0535, 78F0536, 78F0537, and 78F0537D, the multiplier/divider is provided. 18.1 Functions of Multiplier/Divider The multiplier/divider has the following functions. • 16 bits × 16 bits = 32 bits (multiplication) •...
Page 478 Figure 18-1. Block Diagram of Multiplier/Divider Internal bus Multiplier/divider control register 0 (DMUC0) Multiplication/division data register B0 Remainder data register 0 Multiplication/division data register A0 DMUSEL0 DMUE (MDB0 (MDB0H + MDB0L) (SDR0 (SDR0H + SDR0L) (MDA0H (MDA0HH + MDA0HL) + MDA0L (MDA0LH + MDA0LL) ) Start MDA000 INTDMU...
Page 479 µ CHAPTER 18 MULTIPLIER/DIVIDER ( PD78F0534, 78F0535, 78F0536, 78F0537, AND 78F0537D ONLY) (1) Remainder data register 0 (SDR0) SDR0 is a 16-bit register that stores a remainder. This register stores 0 in the multiplication mode and the remainder of an operation result in the division mode. SDR0 can be read by an 8-bit or 16-bit memory manipulation instruction.
Page 480 µ CHAPTER 18 MULTIPLIER/DIVIDER ( PD78F0534, 78F0535, 78F0536, 78F0537, AND 78F0537D ONLY) The functions of MDA0 when an operation is executed are shown in the table below. Table 18-2. Functions of MDA0 During Operation Execution DMUSEL0 Operation Mode Setting Operation Result Division mode Dividend Division result (quotient)
Page 481: Register Controlling Multiplier/Divider
µ CHAPTER 18 MULTIPLIER/DIVIDER ( PD78F0534, 78F0535, 78F0536, 78F0537, AND 78F0537D ONLY) 18.3 Register Controlling Multiplier/Divider The multiplier/divider is controlled by multiplier/divider control register 0 (DMUC0). (1) Multiplier/divider control register 0 (DMUC0) DMUC0 is an 8-bit register that controls the operation of the multiplier/divider. DMUC0 can be set by a 1-bit or 8-bit memory manipulation instruction.
Page 482: Operations Of Multiplier/Divider
µ CHAPTER 18 MULTIPLIER/DIVIDER ( PD78F0534, 78F0535, 78F0536, 78F0537, AND 78F0537D ONLY) 18.4 Operations of Multiplier/Divider 18.4.1 Multiplication operation • Initial setting 1. Set operation data to multiplication/division data register A0L (MDA0L) and multiplication/division data register B0 (MDB0). 2. Set bits 0 (DMUSEL0) and 7 (DMUE) of multiplier/divider control register 0 (DMUC0) to 1. Operation will start. •...
Page 483 Figure 18-6. Timing Chart of Multiplication Operation (00DAH × 0093H) Operation clock DMUE DMUSEL0 Internal clock Counter XXXX 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 SDR0 0000 0049 0024 005B 0077 003B 0067...
Page 484: Division Operation
µ CHAPTER 18 MULTIPLIER/DIVIDER ( PD78F0534, 78F0535, 78F0536, 78F0537, AND 78F0537D ONLY) 18.4.2 Division operation • Initial setting 1. Set operation data to multiplication/division data register A0 (MDA0L and MDA0H) and multiplication/division data register B0 (MDB0). 2. Set bits 0 (DMUSEL0) and 7 (DMUE) of multiplier/divider control register 0 (DMUC0) to 0 and 1, respectively. Operation will start.
Page 485 Figure 18-7. Timing Chart of Division Operation (DCBA2586H ÷ 0018H) Operation clock DMUE DMUSEL0 Internal clock Counter 1B 1C 1D 1E XXXX 0000 0001 0003 0006 000D 0003 0007 000E 0004 000B 0016 0014 0010 0008 0011 000B 0016 SDR0 0932 XXXX DCBA...
Page 486: Chapter 19 Interrupt Functions
CHAPTER 19 INTERRUPT FUNCTIONS 19.1 Interrupt Function Types The following two types of interrupt functions are used. (1) Maskable interrupts These interrupts undergo mask control. Maskable interrupts can be divided into a high interrupt priority group and a low interrupt priority group by setting the priority specification flag registers (PR0L, PR0H, PR1L, PR1H). Multiple interrupt servicing can be applied to low-priority interrupts when high-priority interrupts are generated.
Page 487 CHAPTER 19 INTERRUPT FUNCTIONS Table 19-1. Interrupt Source List (1/2) Interrupt Default Interrupt Source Internal/ Vector Basic Note 1 Type Priority External Table Configuration Name Trigger Note 2 Address Type Note 3 Maskable INTLVI Low-voltage detection Internal 0004H INTP0 Pin input edge detection External 0006H INTP1...
Page 488 CHAPTER 19 INTERRUPT FUNCTIONS Table 19-1. Interrupt Source List (2/2) Interrupt Default Interrupt Source Internal/ Vector Basic Note 1 Type Priority External Table Configuration Name Trigger Note 2 Address Type Maskable INTIIC0/ End of IIC0 communication/end of Internal 0034H Note 3 INTDMU multiply/divide operation Note 3...
Page 489 CHAPTER 19 INTERRUPT FUNCTIONS Figure 19-1. Basic Configuration of Interrupt Function (1/2) (A) Internal maskable interrupt Internal bus Vector table Priority controller Interrupt address generator request Standby release signal (B) External maskable interrupt (INTP0 to INTP7) Internal bus External interrupt edge enable register (EGP, EGN) Vector table...
Page 490 CHAPTER 19 INTERRUPT FUNCTIONS Figure 19-1. Basic Configuration of Interrupt Function (2/2) (C) External maskable interrupt (INTKR) Internal bus Interrupt Vector table Priority controller request address generator interrupt detector 1 when KRMn = 1 (n = 0 to 7) Standby release signal (D) Software interrupt Internal bus Interrupt...
Page 491: Registers Controlling Interrupt Functions
CHAPTER 19 INTERRUPT FUNCTIONS 19.3 Registers Controlling Interrupt Functions The following 6 types of registers are used to control the interrupt functions. • Interrupt request flag register (IF0L, IF0H, IF1L, IF1H) • Interrupt mask flag register (MK0L, MK0H, MK1L, MK1H) •...
Page 492 CHAPTER 19 INTERRUPT FUNCTIONS Table 19-2. Flags Corresponding to Interrupt Request Sources Interrupt Interrupt Request Flag Interrupt Mask Flag Priority Specification Flag Source Register Register Register INTLVI LVIIF IF0L LVIMK MK0L LVIPR PR0L INTP0 PIF0 PMK0 PPR0 INTP1 PIF1 PMK1 PPR1 INTP2 PIF2...
Page 493 CHAPTER 19 INTERRUPT FUNCTIONS (1) Interrupt request flag registers (IF0L, IF0H, IF1L, IF1H) The interrupt request flags are set to 1 when the corresponding interrupt request is generated or an instruction is executed. They are cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon reset signal generation.
Page 494 CHAPTER 19 INTERRUPT FUNCTIONS Cautions 3. When manipulating a flag of the interrupt request flag register, use a 1-bit memory manipulation instruction (CLR1). When describing in C language, use a bit manipulation instruction such as “IF0L.0 = 0;” or “_asm(“clr1 IF0L, 0”);” because the compiled assembler must be a 1-bit memory manipulation instruction (CLR1).
Page 495 CHAPTER 19 INTERRUPT FUNCTIONS (2) Interrupt mask flag registers (MK0L, MK0H, MK1L, MK1H) The interrupt mask flags are used to enable/disable the corresponding maskable interrupt servicing. MK0L, MK0H, MK1L, and MK1H are set by a 1-bit or 8-bit memory manipulation instruction. When MK0L and MK0H, and MK1L and MK1H are combined to form 16-bit registers MK0 and MK1, they are set by a 16-bit memory manipulation instruction.
Page 496 CHAPTER 19 INTERRUPT FUNCTIONS (3) Priority specification flag registers (PR0L, PR0H, PR1L, PR1H) The priority specification flag registers are used to set the corresponding maskable interrupt priority order. PR0L, PR0H, PR1L, and PR1H are set by a 1-bit or 8-bit memory manipulation instruction. If PR0L and PR0H, and PR1L and PR1H are combined to form 16-bit registers PR0 and PR1, they are set by a 16-bit memory manipulation instruction.
Page 497 CHAPTER 19 INTERRUPT FUNCTIONS (4) External interrupt rising edge enable register (EGP), external interrupt falling edge enable register (EGN) These registers specify the valid edge for INTP0 to INTP7. EGP and EGN are set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets these registers to 00H.
Page 498 CHAPTER 19 INTERRUPT FUNCTIONS (5) Program status word (PSW) The program status word is a register used to hold the instruction execution result and the current status for an interrupt request. The IE flag that sets maskable interrupt enable/disable and the ISP flag that controls multiple interrupt servicing are mapped to the PSW.
Page 499: Interrupt Servicing Operations
CHAPTER 19 INTERRUPT FUNCTIONS 19.4 Interrupt Servicing Operations 19.4.1 Maskable interrupt acknowledgement A maskable interrupt becomes acknowledgeable when the interrupt request flag is set to 1 and the mask (MK) flag corresponding to that interrupt request is cleared to 0. A vectored interrupt request is acknowledged if interrupts are in the interrupt enabled state (when the IE flag is set to 1).
Page 500 CHAPTER 19 INTERRUPT FUNCTIONS Figure 19-7. Interrupt Request Acknowledgement Processing Algorithm Start ××IF = 1? Yes (interrupt request generation) ××MK = 0? Interrupt request held pending Yes (High priority) ××PR = 0? No (Low priority) Any high-priority Any high-priority interrupt request among those interrupt request among simultaneously generated with ××PR = 0?
Page 501: Software Interrupt Request Acknowledgement
CHAPTER 19 INTERRUPT FUNCTIONS Figure 19-8. Interrupt Request Acknowledgement Timing (Minimum Time) 6 clocks PSW and PC saved, Interrupt servicing CPU processing Instruction Instruction jump to interrupt program servicing ××IF (××PR = 1) 8 clocks ××IF (××PR = 0) 7 clocks Remark 1 clock: 1/f : CPU clock) Figure 19-9.
Page 502: Multiple Interrupt Servicing
CHAPTER 19 INTERRUPT FUNCTIONS 19.4.3 Multiple interrupt servicing Multiple interrupt servicing occurs when another interrupt request is acknowledged during execution of an interrupt. Multiple interrupt servicing does not occur unless the interrupt request acknowledgement enabled state is selected (IE = 1). When an interrupt request is acknowledged, interrupt request acknowledgement becomes disabled (IE = 0). Therefore, to enable multiple interrupt servicing, it is necessary to set (1) the IE flag with the EI instruction during interrupt servicing to enable interrupt acknowledgement.
Page 503 CHAPTER 19 INTERRUPT FUNCTIONS Figure 19-10. Examples of Multiple Interrupt Servicing (1/2) Example 1. Multiple interrupt servicing occurs twice Main processing INTxx servicing INTyy servicing INTzz servicing IE = 0 IE = 0 IE = 0 INTxx INTyy INTzz (PR = 1) (PR = 0) (PR = 0) RETI...
Page 504 CHAPTER 19 INTERRUPT FUNCTIONS Figure 19-10. Examples of Multiple Interrupt Servicing (2/2) Example 3. Multiple interrupt servicing does not occur because interrupts are not enabled Main processing INTxx servicing INTyy servicing IE = 0 INTyy (PR = 0) INTxx (PR = 0) RETI IE = 1 IE = 0...
Page 505: Interrupt Request Hold
CHAPTER 19 INTERRUPT FUNCTIONS 19.4.4 Interrupt request hold There are instructions where, even if an interrupt request is issued for them while another instruction is being executed, request acknowledgement is held pending until the end of execution of the next instruction. These instructions (interrupt request hold instructions) are listed below.
Page 506: Chapter 20 Key Interrupt Function
CHAPTER 20 KEY INTERRUPT FUNCTION 20.1 Functions of Key Interrupt A key interrupt (INTKR) can be generated by setting the key return mode register (KRM) and inputting a falling edge to the key interrupt input pins (KR0 to KR7). Table 20-1. Assignment of Key Interrupt Detection Pins Flag Description KRM0...
Page 507: Register Controlling Key Interrupt
CHAPTER 20 KEY INTERRUPT FUNCTION 20.3 Register Controlling Key Interrupt (1) Key return mode register (KRM) This register controls the KRM0 to KRM7 bits using the KR0 to KR7 signals, respectively. KRM is set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets KRM to 00H.
Page 508: Chapter 21 Standby Function
CHAPTER 21 STANDBY FUNCTION 21.1 Standby Function and Configuration 21.1.1 Standby function The standby function is designed to reduce the operating current of the system. The following two modes are available. (1) HALT mode HALT instruction execution sets the HALT mode. In the HALT mode, the CPU operation clock is stopped. If the high-speed system clock oscillator, internal high-speed oscillator, internal low-speed oscillator, or subsystem clock oscillator is operating before the HALT mode is set, oscillation of each clock continues.
Page 509 CHAPTER 21 STANDBY FUNCTION (1) Oscillation stabilization time counter status register (OSTC) This is the register that indicates the count status of the X1 clock oscillation stabilization time counter. When X1 clock oscillation starts with the internal high-speed oscillation clock or subsystem clock used as the CPU clock, the X1 clock oscillation stabilization time can be checked.
Page 510 CHAPTER 21 STANDBY FUNCTION (2) Oscillation stabilization time select register (OSTS) This register is used to select the X1 clock oscillation stabilization wait time when the STOP mode is released. When the X1 clock is selected as the CPU clock, the operation waits for the time set using OSTS after the STOP mode is released.
Page 511: Standby Function Operation
CHAPTER 21 STANDBY FUNCTION 21.2 Standby Function Operation 21.2.1 HALT mode (1) HALT mode The HALT mode is set by executing the HALT instruction. HALT mode can be set regardless of whether the CPU clock before the setting was the high-speed system clock, internal high-speed oscillation clock, or subsystem clock.
Page 512 CHAPTER 21 STANDBY FUNCTION Table 21-1. Operating Statuses in HALT Mode (1/2) HALT Mode Setting When HALT Instruction Is Executed While CPU Is Operating on Main System Clock When CPU Is Operating on When CPU Is Operating on When CPU Is Operating on Internal High-Speed X1 Clock (f External Main System Clock...
Page 513 CHAPTER 21 STANDBY FUNCTION Table 21-1. Operating Statuses in HALT Mode (2/2) HALT Mode Setting When HALT Instruction Is Executed While CPU Is Operating on Subsystem Clock When CPU Is Operating on XT1 Clock (f When CPU Is Operating on External Subsystem Clock (f Item EXCLKS...
Page 514 CHAPTER 21 STANDBY FUNCTION (2) HALT mode release The HALT mode can be released by the following two sources. (a) Release by unmasked interrupt request When an unmasked interrupt request is generated, the HALT mode is released. If interrupt acknowledgement is enabled, vectored interrupt servicing is carried out. If interrupt acknowledgement is disabled, the next address instruction is executed.
Page 515 CHAPTER 21 STANDBY FUNCTION (b) Release by reset signal generation When the reset signal is generated, HALT mode is released, and then, as in the case with a normal reset operation, the program is executed after branching to the reset vector address. Figure 21-4.
Page 516: Stop Mode
CHAPTER 21 STANDBY FUNCTION Table 21-2. Operation in Response to Interrupt Request in HALT Mode Release Source MK×× PR×× Operation × Maskable interrupt Next address request instruction execution × Interrupt servicing execution Next address instruction execution × Interrupt servicing execution ×...
Page 517 CHAPTER 21 STANDBY FUNCTION Table 21-3. Operating Statuses in STOP Mode STOP Mode Setting When STOP Instruction Is Executed While CPU Is Operating on Main System Clock When CPU Is Operating on When CPU Is Operating on When CPU Is Operating on Internal High-Speed X1 Clock (f External Main System Clock...
Page 518 CHAPTER 21 STANDBY FUNCTION Cautions 1. To use the peripheral hardware that stops operation in the STOP mode, and the peripheral hardware for which the clock that stops oscillating in the STOP mode after the STOP mode is released, restart the peripheral hardware. 2.
Page 519 CHAPTER 21 STANDBY FUNCTION (a) Release by unmasked interrupt request When an unmasked interrupt request is generated, the STOP mode is released. After the oscillation stabilization time has elapsed, if interrupt acknowledgment is enabled, vectored interrupt servicing is carried out. If interrupt acknowledgment is disabled, the next address instruction is executed. Figure 21-6.
Page 520 CHAPTER 21 STANDBY FUNCTION (b) Release by reset signal generation When the reset signal is generated, STOP mode is released, and then, as in the case with a normal reset operation, the program is executed after branching to the reset vector address. Figure 21-7.
Page 521: Chapter 22 Reset Function
CHAPTER 22 RESET FUNCTION The following four operations are available to generate a reset signal. (1) External reset input via RESET pin (2) Internal reset by watchdog timer program loop detection (3) Internal reset by comparison of supply voltage and detection voltage of power-on-clear (POC) circuit (4) Internal reset by comparison of supply voltage and detection voltage of low-power-supply detector (LVI) External and internal resets have no functional differences.
Page 522 Figure 22-1. Block Diagram of Reset Function Internal bus Reset control flag register (RESF) WDTRF LVIRF Watchdog timer reset signal Clear Clear Reset signal to LVIM/LVIS register RESET Power-on-clear circuit reset signal Reset signal Low-voltage detector reset signal Caution An LVI circuit internal reset does not reset the LVI circuit. Remarks 1.
Page 523 CHAPTER 22 RESET FUNCTION Figure 22-2. Timing of Reset by RESET Input Wait for oscillation accuracy stabilization Internal high-speed oscillation clock Starting X1 oscillation is specified by software. High-speed system clock (when X1 oscillation is selected) Reset processing Normal operation Reset period CPU clock Normal operation...
Page 524 CHAPTER 22 RESET FUNCTION Figure 22-4. Timing of Reset in STOP Mode by RESET Input Wait for oscillation STOP instruction execution accuracy stabilization Internal high-speed oscillation clock Starting X1 oscillation is specified by software. High-speed system clock (when X1 oscillation is selected) Reset processing Normal...
Page 525 CHAPTER 22 RESET FUNCTION Table 22-1. Operation Statuses During Reset Period Item During Reset Period System clock Clock supply to the CPU is stopped. Main system clock Operation stopped Operation stopped (pin is I/O port mode) Clock input invalid (pin is I/O port mode) EXCLK Subsystem clock Operation stopped (pin is I/O port mode)
Page 526 CHAPTER 22 RESET FUNCTION Table 22-2. Hardware Statuses After Reset Acknowledgment (1/3) Hardware After Reset Note 1 Acknowledgment Program counter (PC) The contents of the reset vector table (0000H, 0001H) are set. Stack pointer (SP) Undefined Program status word (PSW) Note 2 Data memory Undefined...
Page 527 CHAPTER 22 RESET FUNCTION Table 22-2. Hardware Statuses After Reset Acknowledgment (2/3) Hardware Status After Reset Note 1 Acknowledgment 8-bit timer/event Timer counters 50, 51 (TM50, TM51) counters 50, 51 Compare registers 50, 51 (CR50, CR51) Timer clock selection registers 50, 51 (TCL50, TCL51) Mode control registers 50, 51 (TMC50, TMC51) 8-bit timers H0, H1 Compare registers 00, 10, 01, 11 (CMP00, CMP10, CMP01, CMP11)
Page 528 CHAPTER 22 RESET FUNCTION Table 22-2. Hardware Statuses After Reset Acknowledgment (3/3) Hardware Status After Reset Note 1 Acknowledgment Serial interface IIC0 Shift register 0 (IIC0) Control register 0 (IICC0) Slave address register 0 (SVA0) Clock selection register 0 (IICCL0) Function expansion register 0 (IICX0) Status register 0 (IICS0) Flag register 0 (IICF0)
Page 529: Register For Confirming Reset Source
CHAPTER 22 RESET FUNCTION 22.1 Register for Confirming Reset Source Many internal reset generation sources exist in the 78K0/KE2. The reset control flag register (RESF) is used to store which source has generated the reset request. RESF can be read by an 8-bit memory manipulation instruction. RESET input, reset by power-on-clear (POC) circuit, and reading RESF set RESF to 00H.
Page 530: Chapter 23 Power-On-Clear Circuit
CHAPTER 23 POWER-ON-CLEAR CIRCUIT 23.1 Functions of Power-on-Clear Circuit The power-on-clear circuit (POC) has the following functions. • Generates internal reset signal at power on. In the 1.59 V POC mode (option byte: POCMODE = 0), the reset signal is released when the supply voltage ) exceeds 1.59 V ±0.15 V.
Page 531: Configuration Of Power-On-Clear Circuit
CHAPTER 23 POWER-ON-CLEAR CIRCUIT 23.2 Configuration of Power-on-Clear Circuit The block diagram of the power-on-clear circuit is shown in Figure 23-1. Figure 23-1. Block Diagram of Power-on-Clear Circuit Internal reset signal − Reference voltage source 23.3 Operation of Power-on-Clear Circuit (1) In 1.59 V POC mode (option byte: POCMODE = 0) •...
Page 532 CHAPTER 23 POWER-ON-CLEAR CIRCUIT Figure 23-2. Timing of Generation of Internal Reset Signal by Power-on-Clear Circuit and Low-Voltage Detector (1/2) (1) In 1.59 V POC mode (option byte: POCMODE = 0) Set LVI to be Set LVI to be Set LVI to be used for reset used for interrupt used for reset...
Page 533 CHAPTER 23 POWER-ON-CLEAR CIRCUIT Figure 23-2. Timing of Generation of Internal Reset Signal by Power-on-Clear Circuit and Low-Voltage Detector (2/2) (2) In 2.7 V/1.59 V POC mode (option byte: POCMODE = 1) Set LVI to be Set LVI to be Set LVI to be used for reset used for interrupt...
Page 534: Cautions For Power-On-Clear Circuit
CHAPTER 23 POWER-ON-CLEAR CIRCUIT 23.4 Cautions for Power-on-Clear Circuit In a system where the supply voltage (V ) fluctuates for a certain period in the vicinity of the POC detection voltage (V ), the system may be repeatedly reset and released from the reset status. In this case, the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking the following action.
Page 535 CHAPTER 23 POWER-ON-CLEAR CIRCUIT Figure 23-3. Example of Software Processing After Reset Release (2/2) • Checking reset source Check reset source WDTRF of RESF register = 1? Reset processing by watchdog timer LVIRF of RESF register = 1? Reset processing by low-voltage detector Power-on-clear/external reset generated...
Page 536: Chapter 24 Low-Voltage Detector
CHAPTER 24 LOW-VOLTAGE DETECTOR 24.1 Functions of Low-Voltage Detector The low-voltage detector (LVI) has the following functions. • Compares supply voltage (V ) and detection voltage (V ), and generates an internal interrupt signal or internal reset signal when V <...
Page 537: Registers Controlling Low-Voltage Detector
CHAPTER 24 LOW-VOLTAGE DETECTOR 24.3 Registers Controlling Low-Voltage Detector The low-voltage detector is controlled by the following registers. • Low-voltage detection register (LVIM) • Low-voltage detection level selection register (LVIS) • Port mode register 12 (PM12) Preliminary User’s Manual U17260EJ3V1UD...
Page 538 CHAPTER 24 LOW-VOLTAGE DETECTOR (1) Low-voltage detection register (LVIM) This register sets low-voltage detection and the operation mode. This register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets LVIM to 00H. Figure 24-2. Format of Low-Voltage Detection Register (LVIM) Note 1 Address: FFBEH After reset: 00H...
Page 539 CHAPTER 24 LOW-VOLTAGE DETECTOR (2) Low-voltage detection level selection register (LVIS) This register selects the low-voltage detection level. This register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation input sets LVIS to 00H. Figure 24-3. Format of Low-Voltage Detection Level Selection Register (LVIS) Address: FFBFH After reset: 00H Symbol...
Page 540: Operation Of Low-Voltage Detector
CHAPTER 24 LOW-VOLTAGE DETECTOR (3) Port mode register 12 (PM12) When using the P120/EXLVI/INTP0 pin for external low-voltage detection potential input, set PM120 to 1. At this time, the output latch of P120 may be 0 or 1. PM12 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets PM12 to FFH.
Page 541: When Used As Reset
CHAPTER 24 LOW-VOLTAGE DETECTOR 24.4.1 When used as reset (1) When detecting level of supply voltage (V • When starting operation <1> Mask the LVI interrupt (LVIMK = 1). <2> Clear bit 2 (LVISEL) of the low-voltage detection register (LVIM) to 0 (detects level of supply voltage )) (default value).
Page 542 CHAPTER 24 LOW-VOLTAGE DETECTOR Figure 24-5. Timing of Low-Voltage Detector Internal Reset Signal Generation (Detects Level of Supply Voltage (V )) (1/2) (1) In 1.59 V POC mode (option byte: POCMODE = 0) Supply voltage (V = 1.59 V (TYP.) Time LVIMK flag Note 1...
Page 543 CHAPTER 24 LOW-VOLTAGE DETECTOR Figure 24-5. Timing of Low-Voltage Detector Internal Reset Signal Generation (Detects Level of Supply Voltage (V )) (2/2) (2) In 2.7 V/1.59 V POC mode (option byte: POCMODE = 1) Supply voltage (V 2.7 V (TYP.) = 1.59 V (TYP.) Time LVIMK flag...
Page 544 CHAPTER 24 LOW-VOLTAGE DETECTOR (2) When detecting level of input voltage from external input pin (EXLVI) • When starting operation <1> Mask the LVI interrupt (LVIMK = 1). <2> Set bit 2 (LVISEL) of the low-voltage detection register (LVIM) to 1 (detects level of input voltage from external input pin (EXLVI)).
Page 545 CHAPTER 24 LOW-VOLTAGE DETECTOR Figure 24-6. Timing of Low-Voltage Detector Internal Reset Signal Generation (Detects Level of Input Voltage from External Input Pin (EXLVI)) Input voltage from external input pin (EXLVI) LVI detection voltage EXLVI Time LVIMK flag Note 1 (set by software) <1>...
Page 546: When Used As Interrupt
CHAPTER 24 LOW-VOLTAGE DETECTOR 24.4.2 When

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