Processor Reset# Routing Example; Processor And Gmch Host Clock Signals; Figure 19. Processor Reset# Signal Routing Example With Itp700Flex Debug Port; Table 17. Processor Reset# Signal Routing Guidelines With Itp700Flex Connector - Intel 855GM Design Manual

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Table 17. Processor RESET# Signal Routing Guidelines with ITP700FLEX Connector

L1
1.0" – 6.0"
4.1.5.1.

Processor RESET# Routing Example

Figure 19 illustrates a board routing example for the RESET# signal with an ITP700FLEX debug port
implemented. It illustrates how the CPURST# pin of GMCH forks out into two branches on Layer 6 of
the motherboard. One branch is routed directly to the processor RESET# pin amongst the rest of the
common clock signals. Another branch routes below the address signals and vias down to the secondary
side that route to the Rs and Rtt resistors. These resistors are placed in the vicinity of the ITP700FLEX
debug port.
Note: The placement of Rs and Rtt next to each other is to minimize the routing between Rs and Rtt as well as
the minimal routing between Rs and the ITP700FLEX connector. Also, since a transition between Layer
6 and the secondary side occurs, a GND stitching via is added to guarantee continuous ground reference
of the secondary side routing of the RESET# signal to ITP700FLEX connector.

Figure 19. Processor RESET# Signal Routing Example with ITP700FLEX Debug Port

GMCH
MCH - M
CPURESET#
4.1.6.

Processor and GMCH Host Clock Signals

Figure 20 illustrates processor and GMCH host clock signal routing. Both the processor and the
GMCH's BCLK[1:0] signals are initially routed from the CK-408 clock generator on Layer 3.In the
recommended routing example (Figure 20) secondary side layer routing of BCLK[1:0] is 507 mils long.
To meet length-matching requirements between the processor and GMCH's BCLK[1:0] signals, a
similar transition from Layer 3 to the secondary side layer is done next to the GMCH package outline.
Routing of the GMCH's BCLK[1:0] signals on the secondary side is also trace tuned to 507 mils.
®
Intel 855GM/855GME Chipset Platform Design Guide
Intel Pentium M/Celeron M Front Side Bus Design Guidelines
L2 + L3
6.0" max
Layer 6
L1
VCCP
Rtt
Rs
L2
L3
L3 Rs
Rs = 22.6 Ω ± 1%
0.5" max
CPU
GND VIA
CPU
ITPFLEX
Connector
RESET#
ITPFLEX
CONNECTOR
RESET#
Rtt
Rtt = 220 Ω ± 5%
Secondary
Side
Rtt
Rs
VCCP
57