Processor Reset# Routing Example; Processor Reset# Signal Routing Topology With Itp700Flex Connector; Processor Reset# Signal Routing Example With Itp700Flex Debug Port; Processor Reset# Signal Routing Guidelines With Itp700Flex Connector - Intel 855GME Design Manual

®
Intel 855GME Chipset and Intel
Figure 24. Processor RESET# Signal Routing Topology With ITP700FLEX Connector
Table 17. Processor RESET# Signal Routing Guidelines with ITP700FLEX Connector
L1
1.0" – 6.0"
4.1.6.1

Processor RESET# Routing Example

Figure 25
port implemented.
branches on Layer 6 of the motherboard. One branch is routed directly to the Intel Pentium
M/Celeron M processor RESET# pin among the rest of the common clock signals. Another branch
routes below the address signals and vias down to the secondary side that route to the Rs and Rtt
resistors. These resistors are placed in the vicinity of the ITP700FLEX debug port.
Note: The placement of Rs and Rtt next to each other is to minimize the routing between Rs and Rtt as
well as the minimal routing between Rs and the ITP700FLEX connector. Also, because a transition
between Layer 6 and the secondary side occurs, a GND stitching via is added to ensure continuous
ground reference of the secondary side routing of the RESET# signal to ITP700FLEX connector.
Figure 25. Processor RESET# Signal Routing Example with ITP700FLEX Debug Port
FORK
GMCH -
CPURESET#
G M C H
C P U R E S E T #
L 2
L2 + L3
6.0" max
illustrates a board routing example for the RESET# signal with an ITP700FLEX debug
Figure 25 illustrates how the CPURST# pin of GMCH forks out into two
COMMON
Clock Signals
®
Intel
855GME
Chipset
ADDR
L1
VCCP
Rtt
Rs
L2
January 2007
®
6300ESB ICH Embedded Platform Design Guide
L 1
V C C P
R t t
R s
L3
Rs = 22.6 Ω ± 1%
0.5" max
®
Intel Pentium
Layer 6
Processor
VIA
ITPFLEX
CPU
RESET#
connector
GND
ITPFLEX
CONNECTOR
L3
RESET#
C P U
R E S E T #
IT P F L E X
C O N N E C T O R
L 3
R E S E T #
Rs Rtt
Rtt = 220 ± 5%
Secondary
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M
Side
Rtt
Rs
VCCP
65