Ddr2 Address, Command And Control Signal Routing Topology; Address And Command Signals - Intel EP80579 Manual

System Memory Interface (Memory Down)—Intel
B.6.5 Address, Command and Control Signals
The address, command and control signals shown in
signals.
Table B-30. Address and Command Signals
System Memory Address Signals
Bank Addresses
Row Address Select
Column Address Select
Write Enable
Chip Select
Clock Enable
On-Die-Termination (ODT)
The address, command and control signals are source-clocked signals. The signals are
"clocked" into the SDRAM devices using the positive edge of the clock signals. The
EP80579 drives the address/command and clock signals together.
Figure B-26, and
guidelines for the DDR2-SDRAM address, command and control signals. A maximum of
6 vias should be used for layer changes over the entire route from the EP80579 pin to
SDRAM pin.
Figure B-12. DDR2 Address, Command and Control Signal Routing Topology
EP80579
®
Intel EP80579 Integrated Processor Product Line
Order Number: 320068-005US
®
EP80579 Integrated Processor Product Line
Signal Description
Table B-31 show the recommended topology and layout routing
DDR_VTT
Rtt
TL1
Pkg L0 L1
Lp
= Stripline Routing
= Microstrip Routing
Table B-30
Signal Name
DDR_MA[14:0]
DDR_BA[2:0]
DDR_RAS#
DDR_CAS#
DDR_WE#
DDR_CS[0]#
DDR_CKE[0]
DDR_ODT[0]
L3
L2
L3
L-ECC
L4
L2
L3
L3
are source-clocked
L4
SDRAM0
L4
SDRAM1
L4
SDRAM2
L4
SDRAM3
L4
SDRAM-ECC
L4
SDRAM4
L4
SDRAM5
L4
SDRAM6
L4
SDRAM7
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