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ASZ[1:0]#
0
0
0
1
1
0
1
1
If the memory access is within the 0-to-(4GByte -1) address space, ASZ[1:0]# must be 00B. If
the memory access is within the 4Gbyte-to-(64GByte -1) address space, ASZ[1:0]# must be
01B. All observing bus agents that support the 4Gbyte (32 bit) address space must respond to
the transaction only when ASZ[1:0]# equals 00B. All observing bus agents that support the
64GByte (36- bit) address space must respond to the transaction when ASZ[1:0]# equals 00B or
01B.
LEN[1:0]#
0
0
0
1
1
0
1
1
The LEN[1:0]# signals determine the length of the transfer. The Pentium Pro processor will not
issue a request for a 16 byte data transfer.
In the clock that ADS# is asserted, the Aa[35:3]# signals provide a 36-bit, active-low
address as part of the request. The Pentium Pro processor physical address space is 2
or 64-Gigabytes (64 Gbyte). Address bits 2, 1, and 0 are mapped into byte enable signals
for 0 to 8 byte transfers.
The address signals are protected by the AP[1:0]# pins. AP1# covers A[35:24]#, AP0# covers
A[23:3]#. AP[1:0]# must be valid for two clocks beginning when ADS# is asserted. A parity
error detected on AP[1:0]# is indicated in the Error Phase. A parity signal on the Pentium Pro
processor bus is correct if there are an even number of electrically low signals in the set consist-
ing of the covered signals plus the parity signal. Parity is computed using voltage levels, regard-
less of whether the covered signals are active high or active low.
The Request Parity pin RP# covers the request pins REQ[4:0]# and the address strobe, ADS#.
RP# must be valid for two clocks beginning when ADS# is asserted. A parity error detected on
RP# is indicated in the Error Phase.
In the clock after ADS# is asserted, the A[35:3]# pins supply cache attribute information, a
deferred ID, the byte enables and other information regarding the transaction. Specifically,
the following signals are supported: ATTR[7:0]#, DID[7:0]#, BE[7:0]#, and EXF[4:0]#. The
description for these signals follows.
Table 3-6. Address Space Size
Memory Address Space
32-bit
36-bit
Reserved
Reserved
Table 3-7. Length of Data Transfer
Length
0-8-bytes
16-bytes
32-bytes
Reserved
BUS OVERVIEW
Observing Agents
32 & 36 bit agents
36 bit agents only
None
None
BE[7:0]#
Specify granularity
All active
All active
36
bytes
3-15
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