Data To Strobe Length Matching Requirements; Sdq To Sdqs Mapping; Table 21. Sdq/Sdm To Sdqs Mapping - Intel 852GME Design Manual

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6.3.2.3.

Data to Strobe Length Matching Requirements

The data bit signals, SDQ[71:0] are grouped by byte lanes and associated with a data mask signal
SDM[8:0], and a data strobe, SDQS[8:0].
The data and mask signals must be length matched to their associated strobe within ± 25 mils,
including package.
For SO-DIMM0 this length matching includes the motherboard trace length to the pads of the SO-
DIMM0 connector (L1 + L2 + S0) plus package length.
For SO-DIMM1, the motherboard trace length to the pads of the SO-DIMM1 connector (L1 + L2 +
L3 + S1) plus package length.
Refer to Section 6.2 for more details on package length compensation.
Length range formula for SDQ and SDM,
X = SDQS total length, including package length, as defined previously
Y = SDQ, SDM total length, including package length, within same byte lane as show in Figure 25,
where: ( X – 25 mils )
Length matching is not required from the SO-DIMM1 to the parallel termination resistors. Figure 25 on
the following page depicts the length matching requirements between the SDQ, SDM, and SDQS
signals within a byte lane. Byte lane mapping is defined in Table 21 below.
6.3.2.4.

SDQ to SDQS Mapping

Table 21 below defines the mapping between the nine byte lanes, nine mask bits, and the nine SDQS
signals, as required to do the required length matching.

Table 21. SDQ/SDM to SDQS Mapping

Signal
SDQ[7:0]
SDQ[15:8]
SDQ[23:16]
SDQ[31:24]
SDQ[39:32]
SDQ[56:40]
SDQ[55:48]
SDQ[63:56]
SDQ[71:64]
® ®
Intel 852GME, Intel 852GMV and Intel
System Memory Design Guidelines (DDR-SDRAM)
Y ( X + 25 mils )
Mask Relative To
SDM[0] SDQS[0]
SDM[1] SDQS[1]
SDM[2] SDQS[2]
SDM[3] SDQS[3]
SDM[4] SDQS[4]
SDM[5] SDQS[5]
SDM[6] SDQS[6]
SDM[7] SDQS[7]
SDM[8] SDQS[8]
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852PM Chipset Platforms Design Guide
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