Rdram Trace Length Matching Example - Intel VC820 - Desktop Board Motherboard Design Manual

Layout/Routing Guidelines
Equation 2-2. RDRAM RSL Signal Trace Length Calculation
Figure 2-23. RDRAM Trace Length Matching Example
MCH Package
NOTE: Refer to the Intel
package dimensions.
The RDRAM clocks (CTM, CTM#, CFM and CFM#) must be longer than the RDRAM signals
due to their increased trace velocity (because they are routed as a differential pair). To calculate the
length for each clock, the following formula should be used:
Equation 2-3. RDRAM Clock Signal Trace Length Calculation
Using this formula, the clock signals will be 21 mils/inch longer than the Nominal Length. The
lengthening of the clock signals, to compensate for their trace velocity change, ONLY applies to
routing between the MCH and the first RIMM. The clock signals should be matched in length to
the RSL signals between RIMMs. Refer to
guidelines.
The high-speed CMOS signals must be length matched to the RSL signals within 1200 mils
(1.2 in) due to a timing requirement between CMOS and RSL signals during NAP Exit and PDN
Exit.
It is necessary to compensate for the slight difference in electrical characteristics between a dummy
via and a real via. Refer to the following section for more information on Via Compensation.
2-22
Package Dimension + Board Trace Length = Nominal RSL Length ± 10mils
L1, L2 -> Package Dimensions
L3, L4 -> Board Trace Length
L1
MCH MCH
Die Die
L2
L1 + L3 = Nominal RSL Length ±10 mils
L2 + L4 = Nominal RSL Length ±10 mils
®
820 Chipset: Intel
Clock Length = Nominal RSL Signal Length (package + board) * 1.021
Ball
L3
L4
®
82820 Memory Controller Hub (MCH) Datasheet for component
Chapter 4, "Clocking"
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for more detailed clock routing
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Intel 820 Chipset Design Guide
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