Trace Length From Ixp28Xx Network Processor To Sram (C, K, Sa, D, And R/W_Bw); Trace Length From Sram To Ixp28Xx Network Processor (Q Data) - Intel IXP28XX Manual

Figure 50.
Figure 51.
Hardware Design Guide
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Trace Length from IXP28XX Network Processor to SRAM (C, K, SA, D, and R/W_BW)

Intel
Network Processor
Die
Internal Package

Trace Length from SRAM to IXP28XX Network Processor (Q Data)

Intel
Network Processor
Die
Internal Package
In Figure 50 and Figure 51 L# is the length of etch on the printed circuit board (PCB). The label,
eL# is the effective length of internal etch. Effective length must be considered since the signals
propagate faster in the package than on the PCB, due to the materials used in each. The QDRII
SRAM internal package length need not be considered, because the package is internally matched
by length.
Each channel is independent; therefore, only one channel needs to be considered at a time. Ideally,
the rising edge of the CIN clock is coincident with the rising edge of Q data, i.e., the loopback
clock should arrive at the network processor die at the same time as the Q data, even though they
follow different paths.
In the case of the loopback clock, only the C clock length from the IXP28XX network processor to
SRAM and the Q data length from SRAM to the network processor need to be considered. It is
assumed that the total C and C_N etch lengths are identical. In practice, they may vary by a mil or
®
IXP2800
eL1 L2
Length
®
IXP2800
eL6
L5
Length
IXP28XX Network Processor
QDR SRAM
L3
QDR-II
SRAM1
QDR-II
L3
SRAM1
3361-01
L4
QDR-II
SRAM1
QDR-II
L4
SRAM1
3362-01
87