Figure 6-3. Write Cycle Timing Diagram - Motorola MC68302 User Manual

Integrated multiprotocol processor
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Electrical Characteristics
CLKO
FC2-FC0
A23-A1
AS
CS
LDS-UDS
R/W
DTACK
DATA OUT
BERR / BR
(NOTE 2)
HALT / RESET
ASYNCHRONOUS
INPUTS (NOTE 1)
NOTES:
1. Timing measurements are referenced to and from a low voltage of 0.8 volt and a high voltage of 2.0 volts,
unless otherwise noted. The voltage swing through this range should start outside and pass through the
range such that the rise or fall is linear between between 0.8 volt and 2.0 volts.
2. Because of loading variations, R/W may be valid after AS even though both are initiated by the rising edge
of S2 (specification #20A)
3. Each wait state is a full clock cycle inserted between S4 and S5.
6-10
S0
S1
S2
S3
8
6
7
15
9
13
11
174
152
150
173
20A
177
18
20
176
17
22
21
55
26
7
23
47
32
56

Figure 6-3. Write Cycle Timing Diagram

MC68302 USER'S MANUAL
S4
S5
S6
S7
14
9
151
175
14A
47
172
25
48
47
47
32
47
12
28
53
30
MOTOROLA

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