Sram Interface - Motorola MC68341 User Manual

* Timer register offsets from timer1 base address
IR EQU
CR EQU
SR EQU
CNTR EQU
PRLD1 EQU
COM EQU
On page 8-27, change the last code line from "CLR.W SR(A0)" to "ORI.W #$7000,SR(A0)". The TO, TG, and
TC interrupt status bits are cleared by writing a "1" to the corresponding bit, allowing individual bits to be
cleared without affecting the other bits.
On page 8-28, second code line down, the "MOVE.W #$020F,IR(A0)" initializes the interrupt vector to the Un-
initialized vector - change the $0F to a user-definable vector number. Repeat this correction on page 8-29,
just past mid-page.
61. MC68341 BSDL File
An electronic copy of the BSDL file for the MC68341 is maintained on the AESOP BBS - refer to the beginning
of this document for information on accessing AESOP.
62. Additional Note on Oscillator Layout Guidelines
Add to the Processor Clock Circuitry (page 11-1) and Serial Interface (page 11-4) sections: In general, use
short connections and place external oscillator components close to the processor. Do not route other signals
through or near the oscillator circuit, especially high frequency signals like CLKOUT, AS, and DREQ1 (see
note above on DREQ1 and serial oscillator for page7-5). Place a ground shield around the oscillator logic; use
a separate trace for ground to the oscillator so that it does not carry any of the digital switching noise.
63. Recommended 32KHz Oscillator Circuit
On page 11-2, Figure 11-2, a 10M resistor can be substituted for the 20M R2 bias resistor as shown below.

64. SRAM Interface

The SRAM interface shown in Figure 11-5 on page 11-4 does not support 2-clock accesses, since UWE and
LWE do not assert for 2-clock writes.
MOTOROLA
$4 interrupt register
$6 control register
$8 status register
$A counter register
$C preload register 1
$10 compare register
XTAL
MC683xx
EXTAL
Figure 11-2. Sample Crystal Circuit
MC68341 USER'S MANUAL ADDENDUM
C1
R1
22 pF
330 k
R2 X1
10 M 32.768 kHz
C2
15 pF
15