System Status Bits; Table 3-9. Scr Register Bits - Motorola MC68302 User Manual

Bit
IPA
HWT
WPV
ADC
ERRE
VGE
WPVE
RMCST
EMWS
ADCE
BCLM
FRZW
FRZ1
FRZ2
SAM
HWDEN
HWDCN
LPREC
LPP16
LPEN
LPCD

3.8.2 System Status Bits

The eight most significant bits of the SCR are used to report events recognized by the sys-
tem control logic. On recognition of an event, this logic sets the corresponding bit in the
SCR. The bits may be read at any time. A bit is reset by one and is left unchanged by zero.
More than one bit may be reset at a time.
After system reset (simultaneous assertion of RESET and HALT), these bits are cleared.
IPA—Interrupt Priority Active
This bit is set when the M68000 core has an unmasked interrupt request. When bus clear
mask (BCLM) is set, BCLR and the internal bus clear to the IDMA are asserted.
If BCLM is set, an interrupt handler will normally clear IPA at the
end of the interrupt routine to allow an alternate bus master to
regain the bus; however, if BCLM is cleared, no additional action
need be taken in the interrupt handler.
In the case of nested interrupts, the user may wish to clear the
IPA bit only at the end of the original lower priority interrupt rou-
tine to keep BCLR asserted until it completes. To guarantee that
MOTOROLA

Table 3-9. SCR Register Bits

Name
Interrupt Priority Active
Hardware Watchdog Timeout
Write Protect Violation
Address Decode Conflict
External RISC Request Enable
Vector Generation Enable
Write Protect Violation Enable
Read-Modify-Write Cycle Special Treatment
External Master Wait State
Address Decode Conflict Enable
Bus Clear Mask
Freeze Watchdog Timer Enable
Freeze Timer 1 Enable
Freeze Timer 2 Enable
Synchronous Access Mode
Hardware Watchdog Enable
Hardware Watchdog Count
Low-Power Recovery
Low-Power Clock Prescale Divide by 16
Low-Power Enable
Low-Power Clock Divider Selects
NOTE
MC68302 USER'S MANUAL
System Integration Block (SIB)
Section(s)
3.8.2
3.8.2, 3.8.6
3.8.2
3.8.2
3.9
3.8.4
3.8.3
3.8.3
3.8.3, 3.8.4
3.8.3
3.8.2, 3.8.3, 3.8.5
3.8.8
3.8.8
3.8.8
3.8.3, 3.8.4
3.8.6
3.8.6
3.8.7
3.8.7
3.8.7
3.8.7
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