Annex; A Hardware Interfaces; Gpib Bus Interface - R&S SMB100A Operating Manual

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R&S SMB100A

Annex

A Hardware Interfaces

This section covers hardware related topics, like pin assignment of the GPIB bus inter-
face.
The remote control interfaces are described in detailes in
Basics",
All other interfaces are described in sections "Legend of Front Planel" and "Legend of
Rear Panel" in the Quick Start Guide.
For specifications refer to the data sheet.
A.1 GPIB Bus Interface
Pin assignment
Figure A-1: Pin assignment of GPIB bus interface
Bus lines
●
Data bus with 8 lines D0 to D7:
The transmission is bit-parallel and byte-serial in the ASCII/ISO code. D0 is the
least significant bit, D7 the most significant bit.
●
Control bus with five lines:
Operating Manual 1407.0806.32 ─ 21
on page 235.
Hardware Interfaces

GPIB Bus Interface

Chapter 6, "Remote Control
490