Table Of Contents - Intel 80386 Reference Manual

.TABLE OF CONTENTS
APPENDIX A
LOCAL BUS CONTROL PAL DESCRIPTIONS
PAl-1 Functions .................................................................................................. .
PAl-2 Functions .................................................................................................. .
~Al
Equations .......................................................... : ......................................... .
APPENDIX B
80387 EMULATOR PAL DESCRIPTION
APPENDIX C
DRAM PAL DESCRIPTIONS
Page
A-1
A-2
A-2
DRAM State PAL ................................................................ :................................ C-1
DRAM Control PAL ............................................................................................... C-13
Refresh Interval Counter PAL ............................................................................... C-13
Refresh Address Counter PAL ............................................................................. C-13
Timing Parameters ............................................................................................... C-25
Figures
Figure Title Page
1-1 80386 System Block Diagram ................................................................ 1-2
2-1 Instruction Pipelining ............................................................................... 2-1
2-2 80386 Functional Units .................................... :...................................... .2-2
3-1 ClK2 and ClK Relationship .......... ...... .............................. ..................... 3-5
3-2 80386 Bus States Timing Example .................................. ...................... 3-6
3-3 Bus State Diagram (Does Not Include Address Pipelining) ..................... 3-7
3-4 Non-Pipelined Address and Pipelined Address Differences .................... 3-8
3-5 Consecutive Bytes in Hardware Implementation .................................... 3-9
3-6 Address, Data Bus, and Byte Enables for 32-Bit Bus ............................ 3-9
3-7 MisalignedTransfer ........................................................................ ;....... 3-11
3-8 Non-Pipelined Address Read Cycles . ..................................................... 3-12
3-9 Non-Pipelined Address Write Cycles . ..................................................... 3-15
3-10 Pipelined Address Cycles .................................................... ,.................. 3-16
3-:.11
Interrupt Acknowledge Bus Cycles ......................................................... 3-18
3-12 Internal NA# and BS16# logic .......................... ................................... 3-20
3-13 32-Bit and 16-Bit Bus Cycle Timing ........................................................ 3-21
3-14 32-Bit and 16-Bit Data Addressing ................................. :............. .......... 3-22
3-15 Connecting 82384 to 80386 ..................................................... .............. 3-27
3-16 Using ClK to Determine Bus Cycle Start ............................................... 3-28
3-17 Error Condition Caused by Unlocked Cycles .......................................... 3-31
3-18 lOCK# Signal during Address Pipelining ............................................... 3-32
3-19 Bus State Diagram with HOLD State ..................................................... 3-34
3-20 Typical RC .RESET Timing Circuit ........... ..................................... ........... 3-36
3-21 RESET, ClK, and ClK2 Timing ....... ,..................................................... 3-37
5-1 80386 System with 80287 Coprocessor ........... ..................................... 5-3
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