Branch Instructions (Extended Isa) - NEC uPD98502 User Manual

Instruction
Branch On Equal Likely BEQL rs, rt, offset
If the contents of register rs are equal to that of register rt, the program branches to the target address.
If the branch condition is not met, the instruction in the delay slot is discarded.
Branch On Not Equal BNEL rs, rt, offset
Likely
If the contents of register rs are not equal to that of register rt, the program branches to the target
address. If the branch condition is not met, the instruction in the delay slot is discarded.
Branch On Less Than BLEZL rs, offset
Or Equal To Zero Likely If the contents of register rs are less than or equal to zero, the program branches to the target address.
If the branch condition is not met, the instruction in the delay slot is discarded.
Branch On Greater BGTZL rs, offset
Than Zero Likely If the contents of register rs are greater than zero, the program branches to the target address. If the
branch condition is not met, the instruction in the delay slot is discarded.
Instruction
Branch On Less Than BLTZL rs, offset
Zero Likely If the contents of register rs are less than zero, the program branches to the target address. If the
branch condition is not met, the instruction in the delay slot is discarded.
Branch On Greater BGEZL rs, offset
Than Or Equal To Zero If the contents of register rs are greater than or equal to zero, the program branches to the target
Likely address. If the branch condition is not met, the instruction in the delay slot is discarded.
Branch On Less Than BLTZALL rs, offset
Zero And Link Likely The address of the instruction that follows delay slot is stored to register r31 (link register).
If the contents of register rs are less than zero, the program branches to the target address. If the
branch condition is not met, the instruction in the delay slot is discarded.
Branch On Greater BGEZALL rs, offset
Than Or Equal To Zero The address of the instruction that follows delay slot is stored to register r31 (link register).
And Link Likely If the contents of register rs are greater than or equal to zero, the program branches to the target
address. If the branch condition is not met, the instruction in the delay slot is discarded.
Instruction
Branch On BC0TL offset
Coprocessor 0 True Adds the 16-bit offset (shifted left by two bits and sign extended to 32 bits) to the address of the
Likely instruction in the delay slot to calculate the branch target address.
If the conditional signal of the coprocessor 0 is true, the program branches to the target address with
one-instruction delay.
If the branch condition is not met, the instruction in the delay slot is discarded.
Branch On BC0FL offset
Coprocessor 0 False Adds the 16-bit offset (shifted left by two bits and sign extended to 32 bits) to the address of the
Likely instruction in the delay slot to calculate the branch target address.
If the conditional signal of the coprocessor 0 is false, the program branches to the target address with
one-instruction delay.
If the branch condition is not met, the instruction in the delay slot is discarded.
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CHAPTER 2 V
Table 2-18. Branch Instructions (Extended ISA)
Format and Description
Format and Description
Format and Description
Preliminary User's Manual S15543EJ1V0UM
4120A
R
rs
op
rs
sub
REGIMM
br
COP0 BC
rt offset
offset
offset