Common Exception Handling - NEC uPD98502 User Manual

(a) Handling Exceptions other than Cold Reset, Soft Reset, NMI, and TLB/XTLB Refill (Hardware)
BD bit ← 1
EPC ← PC − 4
= 0 (Normal)
PC ← FFFF FFFF 8000 0000H +180H
(Unmapped, cacheable space)
Remark The interrupts can be masked by setting the IE or IM bit.
The Watch exception can be set to pending state by setting the EXL bit to 1.
CHAPTER 2 V
Figure 2-61. Common Exception Handling (1/2)
Start
Entry Hi ← VPN2, ASID
X/Context ← VPN2
Set Cause register (ExcCode, CE)
)
Yes
EXL = 1?
(SR1)
No
Yes
M16 = 1?
(config20)
No
Yes No
Instruction
in branch delay
slot?
Kernel mode is set and interrupts
are disabled.
EXL ← 1
BEV
PC ← FFFF FFFF BFC0 0200H +180H
To guideline to common exception handler
Preliminary User's Manual S15543EJ1V0UM
4120A
R
• EntryHi and X/Context registers are set only
when a TLB Refill, TLB Invalid, or TLB
Modified exception occurs.
• Check for multiple exceptions
Yes
BD bit ← 1
EPC ← PC − 4
EPC ← EIM
BD bit ← 0
EPC ← PC
• Kernel mode is set and interrupts are
disabled.
BadVAddr is set only when a TLB Refill, TLB
•
Invalid, or TLB Modified exception occurs
(BadVAddr is not set when a Bus Error exception
occurs).
= 1 (bootstrap)
(Unmapped, uncached space)
No
Instruction
in delay slot?
BD bit ← 0
EPC ← PC
EPC ← EIM
159