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MTC0
31
26 25
COP0
0 1 0 0 0 0
6
Format:
MTC0 rt, rd
Description:
The contents of general register rt are loaded into coprocessor register rd of coprocessor 0.
Because the state of the virtual address translation system may be altered by this instruction, the operation of load
instructions, store instructions, and TLB operations immediately prior to and after this instruction are undefined.
When using a register used by the MTC0 by means of instructions before and after it, refer to APPENDIX B
V
4120A COPROCESSOR 0 HAZARDS and place the instructions in the appropriate location.
R
Operation:
data ← GPR [rt]
32, 64 T:
CPR [0, rd] ← data
T+1:
Exceptions:
Coprocessor unusable exception (in 64-bit/32-bit user and supervisor mode if CP0 not enabled)
530
APPENDIX A MIPS III INSTRUCTION SET DETAILS
Move To Coprocessor0
21 20
MT
rt
0 0 1 0 0
5
5
Preliminary User's Manual S15543EJ1V0UM
16 15
11 10
rd
5
MTC0
0
0 0 0 0 0 0 0 0 0 0 0
11
0
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