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2.5.3.8 WatchLo (18) and WatchHi (19) registers
The V
4120A processor provides a debugging feature to detect references to a selected physical address; load
R
and store instructions to the location specified by the WatchLo and WatchHi registers cause a Watch exception.
Figures 2-55 and 2-56 show the format of the WatchLo and WatchHi registers.
31
PAddr0 : Specifies physical address bits 31 to 3.
R
: If this bit is set to 1, an exception will occur when a load instruction is executed.
W
: If this bit is set to 1, an exception will occur when a store instruction is executed.
0
: RFU. Write 0 in a write operation. When this field is read, 0 is read.
31
0
: RFU. Write 0 in a write operation. When this field is read, 0 is read.
CHAPTER 2 V
4120A
R
Figure 2-55. WatchLo Register Format
WatchLo Register
PAddr0
29
Figure 2-56. WatchHi Register Format
WatchHi Register
0
32
Preliminary User's Manual S15543EJ1V0UM
3
2
1
0
0
R
W
1
1
1
0
139
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