NEC uPD98502 User Manual page 589

23...21
25, 24 0
0 MF
1 BC
2
3
18...16
20...19 0
0 BCF
γ
1
γ
2
γ
3
2...0
5...3 0
φ
0
1 TLBP
ξ
2
ERET χ
3
φ
4
φ
5
φ
6
φ
7
Key:
* Operation codes marked with an asterisk cause reserved instruction exceptions in all current
implementations and are reserved for future versions of the architecture.
γ
Operation codes marked with a gamma cause a reserved instruction exception. They are reserved for future
versions of the architecture.
δ
Operation codes marked with a delta are valid only for V
cause a reserved instruction exception on other processors.
φ Operation codes marked with a phi are invalid but do not cause reserved instruction exceptions in V
implementations.
ξ
Operation codes marked with a xi cause a reserved instruction exception on V
χ Operation codes marked with a chi are valid on V
ε
Operation codes marked with epsilon are valid when the processor operating as a 64-bit processor. These
instructions will cause a reserved instruction exception if 64-bit operation is not enabled.
π Operation codes marked with a pi are invalid and cause coprocessor unusable exception.
θ Operation codes marked with a theta are valid when MIPS16 instruction execution is enabled, and cause a
reserved instruction exception when MIPS16 instruction execution is disabled.
APPENDIX A MIPS III INSTRUCTION SET DETAILS
Figure A-1. V 4120AOpcode Bit Encoding (2/2)
R
1 2
γ
DMFε
γ γ
1 2
BCT BCFL BCTL
γ γ
γ γ
γ γ
CP0 Function
1 2
TLBR TLBWI
φ φ
φ φ
φ φ
STANDBY SUSPEND HIBERNAT
φ φ
φ φ
φ φ
Preliminary User's Manual S15543EJ1V0UM
COP0 rs
3 4 5
γ
MT DMTε
γ γ γ
CO
COP0 rt
3 4 5
γ γ
γ γ γ
γ γ γ
γ γ γ
3 4 5
φ φ φ
φ φ φ
φ φ φ
φ φ φ
φ φ
φ φ φ
φ φ φ
φ φ φ
4400 Series processors with CP0 enabled, and
R
4000 Series only.
R
6 7
γ γ
γ γ
6 7
γ γ
γ γ
γ γ
γ γ
6 7
φ
TLBWR
φ φ
φ φ
φ φ
φ φ
φ φ
φ φ
φ φ
4121
R
4121 processor.
R
589