NEC uPD98502 User Manual page 160

Execute MFC0 instruction
X/Context register
Execute MFC0 instruction
(Status bit setting)
Check the Cause register, and jump
Servicing by each exception routine
Execute MTC0 instruction
160
CHAPTER 2 V
Figure 2-61. Common Exception Handling (2/2)
(b) Servicing Common Exceptions (Software)
• The occurrence of TLB Refill, TLB Invalid, and TLB Modified
• The occurrence of the Watch and Interrupt exceptions is
EPC register
Status register
• Other exceptions are avoided in the OS programs.
Cause register
• However, the Cold Reset, Soft Reset, and NMI exceptions are
(In Kernel mode, interrupts are enabled.)
KSU bit ← 00
EXL bit ← 0
IE bit ← 1
• After EXL = 0 is set, all exceptions are enabled (although the
to each routine
No
TS bit = 0?
The processor is reset.
Yes
• The register files are saved.
EXL = 1
EPC register
Status register
• The execution of the ERET instruction is disabled in the
• The processor does not execute an instruction in the branch
ERET
• PC ← EPC, EXL ← 0
Preliminary User's Manual S15543EJ1V0UM
4120A
R
exceptions is disabled by using an unmapped space.
disabled by setting EXL = 1.
enabled.
Interrupt exception can be masked by the IE and IM bits, and the
Cache Error exception can be masked by the DE bit.)
delay slots for the other jump instructions.
delay slot for the ERET instruction.